src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Tom Stellard <thomas.stellard@amd.com>
  24  *
  25  */
  26 #include "radeon_llvm.h"
  27
  28 #include "gallivm/lp_bld_const.h"
  29 #include "gallivm/lp_bld_gather.h"
  30 #include "gallivm/lp_bld_flow.h"
  31 #include "gallivm/lp_bld_init.h"
  32 #include "gallivm/lp_bld_intr.h"
  33 #include "gallivm/lp_bld_swizzle.h"
  34 #include "tgsi/tgsi_info.h"
  35 #include "tgsi/tgsi_parse.h"
  36 #include "util/u_math.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_debug.h"
  39
  40 #include <llvm-c/Core.h>
  41 #include <llvm-c/Transforms/Scalar.h>
  42
  43 static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx)
  44 {
  45         return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL;
  46 }
  47
  48 static struct radeon_llvm_branch * get_current_branch(
  49         struct radeon_llvm_context * ctx)
  50 {
  51         return ctx->branch_depth > 0 ?
  52                         ctx->branch + (ctx->branch_depth - 1) : NULL;
  53 }
  54
  55 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
  56 {
  57  return (index * 4) + chan;
  58 }
  59
  60 static LLVMValueRef emit_swizzle(
  61         struct lp_build_tgsi_context * bld_base,
  62         LLVMValueRef value,
  63         unsigned swizzle_x,
  64         unsigned swizzle_y,
  65         unsigned swizzle_z,
  66         unsigned swizzle_w)
  67 {
  68         LLVMValueRef swizzles[4];
  69         LLVMTypeRef i32t =
  70                 LLVMInt32TypeInContext(bld_base->base.gallivm->context);
  71
  72         swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0);
  73         swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0);
  74         swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0);
  75         swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0);
  76
  77         return LLVMBuildShuffleVector(bld_base->base.gallivm->builder,
  78                 value,
  79                 LLVMGetUndef(LLVMTypeOf(value)),
  80                 LLVMConstVector(swizzles, 4), "");
  81 }
  82
  83 static LLVMValueRef
  84 emit_array_index(
  85         struct lp_build_tgsi_soa_context *bld,
  86         const struct tgsi_full_src_register *reg,
  87         unsigned swizzle)
  88 {
  89         struct gallivm_state * gallivm = bld->bld_base.base.gallivm;
  90
  91         LLVMValueRef addr = LLVMBuildLoad(gallivm->builder,
  92         bld->addr[reg->Indirect.Index][swizzle], "");
  93         LLVMValueRef offset = lp_build_const_int32(gallivm, reg->Register.Index);
  94         LLVMValueRef hw_index = LLVMBuildAdd(gallivm->builder, addr, offset, "");
  95         LLVMValueRef soa_index = LLVMBuildMul(gallivm->builder, hw_index,
  96         lp_build_const_int32(gallivm, 4), "");
  97         LLVMValueRef array_index = LLVMBuildAdd(gallivm->builder, soa_index,
  98         lp_build_const_int32(gallivm, swizzle), "");
  99
 100         return array_index;
 101 }
 102
 103 static LLVMValueRef
 104 emit_fetch_immediate(
 105         struct lp_build_tgsi_context *bld_base,
 106         const struct tgsi_full_src_register *reg,
 107         enum tgsi_opcode_type type,
 108         unsigned swizzle)
 109 {
 110         LLVMTypeRef ctype;
 111         LLVMContextRef ctx = bld_base->base.gallivm->context;
 112
 113         switch (type) {
 114         case TGSI_TYPE_UNSIGNED:
 115         case TGSI_TYPE_SIGNED:
 116                 ctype = LLVMInt32TypeInContext(ctx);
 117                 break;
 118         case TGSI_TYPE_UNTYPED:
 119         case TGSI_TYPE_FLOAT:
 120                 ctype = LLVMFloatTypeInContext(ctx);
 121                 break;
 122         default:
 123                 ctype = 0;
 124                 break;
 125         }
 126
 127         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
 128         return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
 129 }
 130
 131 static LLVMValueRef
 132 emit_fetch_input(
 133         struct lp_build_tgsi_context *bld_base,
 134         const struct tgsi_full_src_register *reg,
 135         enum tgsi_opcode_type type,
 136         unsigned swizzle)
 137 {
 138         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 139         if (swizzle == ~0) {
 140                 LLVMValueRef values[TGSI_NUM_CHANNELS] = {};
 141                 unsigned chan;
 142                 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 143                         values[chan] = ctx->inputs[radeon_llvm_reg_index_soa(
 144                                                 reg->Register.Index, chan)];
 145                 }
 146                 return lp_build_gather_values(bld_base->base.gallivm, values,
 147                                                 TGSI_NUM_CHANNELS);
 148         } else {
 149                 return bitcast(bld_base, type, ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]);
 150         }
 151 }
 152
 153 static LLVMValueRef
 154 emit_fetch_temporary(
 155         struct lp_build_tgsi_context *bld_base,
 156         const struct tgsi_full_src_register *reg,
 157         enum tgsi_opcode_type type,
 158         unsigned swizzle)
 159 {
 160         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
 161         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 162         if (reg->Register.Indirect) {
 163                 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
 164                 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->temps_array, &array_index,
 165                                                 1, "");
 166         return LLVMBuildLoad(builder, ptr, "");
 167         } else {
 168                 LLVMValueRef temp_ptr;
 169                 temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
 170                 return bitcast(bld_base,type,LLVMBuildLoad(builder, temp_ptr, ""));
 171         }
 172 }
 173
 174 static LLVMValueRef
 175 emit_fetch_output(
 176         struct lp_build_tgsi_context *bld_base,
 177         const struct tgsi_full_src_register *reg,
 178         enum tgsi_opcode_type type,
 179         unsigned swizzle)
 180 {
 181         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
 182         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 183          if (reg->Register.Indirect) {
 184                 LLVMValueRef array_index = emit_array_index(bld, reg, swizzle);
 185                 LLVMValueRef ptr = LLVMBuildGEP(builder, bld->outputs_array, &array_index,
 186                                                 1, "");
 187                 return LLVMBuildLoad(builder, ptr, "");
 188         } else {
 189                 LLVMValueRef temp_ptr;
 190                 temp_ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle);
 191                 return LLVMBuildLoad(builder, temp_ptr, "");
 192          }
 193 }
 194
 195 static void emit_declaration(
 196         struct lp_build_tgsi_context * bld_base,
 197         const struct tgsi_full_declaration *decl)
 198 {
 199         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 200         switch(decl->Declaration.File) {
 201         case TGSI_FILE_ADDRESS:
 202         {
 203                  unsigned idx;
 204                 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
 205                         unsigned chan;
 206                         for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 207                                  ctx->soa.addr[idx][chan] = lp_build_alloca(
 208                                         &ctx->gallivm,
 209                                         ctx->soa.bld_base.uint_bld.elem_type, "");
 210                         }
 211                 }
 212                 break;
 213         }
 214
 215         case TGSI_FILE_TEMPORARY:
 216                 lp_emit_declaration_soa(bld_base, decl);
 217                 break;
 218
 219         case TGSI_FILE_INPUT:
 220         {
 221                 unsigned idx;
 222                 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
 223                         ctx->load_input(ctx, idx, decl);
 224                 }
 225         }
 226         break;
 227
 228         case TGSI_FILE_SYSTEM_VALUE:
 229         {
 230                 unsigned idx;
 231                 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
 232                         ctx->load_system_value(ctx, idx, decl);
 233                 }
 234         }
 235         break;
 236
 237         case TGSI_FILE_OUTPUT:
 238         {
 239                 unsigned idx;
 240                 for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) {
 241                         unsigned chan;
 242                         assert(idx < RADEON_LLVM_MAX_OUTPUTS);
 243                         for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
 244                                 ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm,
 245                                         ctx->soa.bld_base.base.elem_type, "");
 246                         }
 247                 }
 248
 249                 ctx->output_reg_count = MAX2(ctx->output_reg_count,
 250                                                          decl->Range.Last + 1);
 251                 break;
 252         }
 253
 254         default:
 255                 break;
 256         }
 257 }
 258
 259 static void
 260 emit_store(
 261         struct lp_build_tgsi_context * bld_base,
 262         const struct tgsi_full_instruction * inst,
 263         const struct tgsi_opcode_info * info,
 264         LLVMValueRef dst[4])
 265 {
 266         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
 267         struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
 268         struct lp_build_context base = bld->bld_base.base;
 269         const struct tgsi_full_dst_register *reg = &inst->Dst[0];
 270         LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
 271         LLVMValueRef temp_ptr;
 272         unsigned chan, chan_index;
 273         boolean is_vec_store = FALSE;
 274         if (dst[0]) {
 275                 LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
 276                 is_vec_store = (k == LLVMVectorTypeKind);
 277         }
 278
 279         if (is_vec_store) {
 280                 LLVMValueRef values[4] = {};
 281                 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) {
 282                         LLVMValueRef index = lp_build_const_int32(gallivm, chan);
 283                         values[chan]  = LLVMBuildExtractElement(gallivm->builder,
 284                                                         dst[0], index, "");
 285                 }
 286                 bld_base->emit_store(bld_base, inst, info, values);
 287                 return;
 288         }
 289
 290         TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
 291                 LLVMValueRef value = dst[chan_index];
 292
 293                 if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
 294                         struct lp_build_emit_data clamp_emit_data;
 295
 296                         memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
 297                         clamp_emit_data.arg_count = 3;
 298                         clamp_emit_data.args[0] = value;
 299                         clamp_emit_data.args[2] = base.one;
 300
 301                         switch(inst->Instruction.Saturate) {
 302                         case TGSI_SAT_ZERO_ONE:
 303                                 clamp_emit_data.args[1] = base.zero;
 304                                 break;
 305                         case TGSI_SAT_MINUS_PLUS_ONE:
 306                                 clamp_emit_data.args[1] = LLVMConstReal(
 307                                                 base.elem_type, -1.0f);
 308                                 break;
 309                         default:
 310                                 assert(0);
 311                         }
 312                         value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
 313                                                 &clamp_emit_data);
 314                 }
 315
 316                 switch(reg->Register.File) {
 317                 case TGSI_FILE_OUTPUT:
 318                         temp_ptr = bld->outputs[reg->Register.Index][chan_index];
 319                         break;
 320
 321                 case TGSI_FILE_TEMPORARY:
 322                         temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index);
 323                         break;
 324
 325                 default:
 326                         return;
 327                 }
 328
 329                 value = bitcast(bld_base, TGSI_TYPE_FLOAT, value);
 330
 331                 LLVMBuildStore(builder, value, temp_ptr);
 332         }
 333 }
 334
 335 static void bgnloop_emit(
 336         const struct lp_build_tgsi_action * action,
 337         struct lp_build_tgsi_context * bld_base,
 338         struct lp_build_emit_data * emit_data)
 339 {
 340         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 341         struct gallivm_state * gallivm = bld_base->base.gallivm;
 342         LLVMBasicBlockRef loop_block;
 343         LLVMBasicBlockRef endloop_block;
 344         endloop_block = LLVMAppendBasicBlockInContext(gallivm->context,
 345                                                 ctx->main_fn, "ENDLOOP");
 346         loop_block = LLVMInsertBasicBlockInContext(gallivm->context,
 347                                                 endloop_block, "LOOP");
 348         LLVMBuildBr(gallivm->builder, loop_block);
 349         LLVMPositionBuilderAtEnd(gallivm->builder, loop_block);
 350         ctx->loop_depth++;
 351         ctx->loop[ctx->loop_depth - 1].loop_block = loop_block;
 352         ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block;
 353 }
 354
 355 static void brk_emit(
 356         const struct lp_build_tgsi_action * action,
 357         struct lp_build_tgsi_context * bld_base,
 358         struct lp_build_emit_data * emit_data)
 359 {
 360         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 361         struct gallivm_state * gallivm = bld_base->base.gallivm;
 362         struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
 363
 364         LLVMBuildBr(gallivm->builder, current_loop->endloop_block);
 365 }
 366
 367 static void cont_emit(
 368         const struct lp_build_tgsi_action * action,
 369         struct lp_build_tgsi_context * bld_base,
 370         struct lp_build_emit_data * emit_data)
 371 {
 372         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 373         struct gallivm_state * gallivm = bld_base->base.gallivm;
 374         struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
 375
 376         LLVMBuildBr(gallivm->builder, current_loop->loop_block);
 377 }
 378
 379 static void else_emit(
 380         const struct lp_build_tgsi_action * action,
 381         struct lp_build_tgsi_context * bld_base,
 382         struct lp_build_emit_data * emit_data)
 383 {
 384         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 385         struct gallivm_state * gallivm = bld_base->base.gallivm;
 386         struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
 387         LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
 388
 389         /* We need to add a terminator to the current block if the previous
 390          * instruction was an ENDIF.Example:
 391          * IF
 392          *   [code]
 393          *   IF
 394          *     [code]
 395          *   ELSE
 396          *    [code]
 397          *   ENDIF <--
 398          * ELSE<--
 399          *   [code]
 400          * ENDIF
 401          */
 402
 403         if (current_block != current_branch->if_block) {
 404                 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
 405         }
 406         if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
 407                 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
 408         }
 409         current_branch->has_else = 1;
 410         LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
 411 }
 412
 413 static void endif_emit(
 414         const struct lp_build_tgsi_action * action,
 415         struct lp_build_tgsi_context * bld_base,
 416         struct lp_build_emit_data * emit_data)
 417 {
 418         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 419         struct gallivm_state * gallivm = bld_base->base.gallivm;
 420         struct radeon_llvm_branch * current_branch = get_current_branch(ctx);
 421         LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder);
 422
 423         /* If we have consecutive ENDIF instructions, then the first ENDIF
 424          * will not have a terminator, so we need to add one. */
 425         if (current_block != current_branch->if_block
 426                         && current_block != current_branch->else_block
 427                         && !LLVMGetBasicBlockTerminator(current_block)) {
 428
 429                  LLVMBuildBr(gallivm->builder, current_branch->endif_block);
 430         }
 431         if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) {
 432                 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block);
 433                 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
 434         }
 435
 436         if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) {
 437                 LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block);
 438                 LLVMBuildBr(gallivm->builder, current_branch->endif_block);
 439         }
 440
 441         LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block);
 442         ctx->branch_depth--;
 443 }
 444
 445 static void endloop_emit(
 446         const struct lp_build_tgsi_action * action,
 447         struct lp_build_tgsi_context * bld_base,
 448         struct lp_build_emit_data * emit_data)
 449 {
 450         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 451         struct gallivm_state * gallivm = bld_base->base.gallivm;
 452         struct radeon_llvm_loop * current_loop = get_current_loop(ctx);
 453
 454         if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) {
 455                  LLVMBuildBr(gallivm->builder, current_loop->loop_block);
 456         }
 457
 458         LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block);
 459         ctx->loop_depth--;
 460 }
 461
 462 static void if_emit(
 463         const struct lp_build_tgsi_action * action,
 464         struct lp_build_tgsi_context * bld_base,
 465         struct lp_build_emit_data * emit_data)
 466 {
 467         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 468         struct gallivm_state * gallivm = bld_base->base.gallivm;
 469         LLVMValueRef cond;
 470         LLVMBasicBlockRef if_block, else_block, endif_block;
 471
 472         cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
 473                 bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
 474                         bld_base->int_bld.zero, "");
 475
 476         endif_block = LLVMAppendBasicBlockInContext(gallivm->context,
 477                                                 ctx->main_fn, "ENDIF");
 478         if_block = LLVMInsertBasicBlockInContext(gallivm->context,
 479                                                 endif_block, "IF");
 480         else_block = LLVMInsertBasicBlockInContext(gallivm->context,
 481                                                 endif_block, "ELSE");
 482         LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block);
 483         LLVMPositionBuilderAtEnd(gallivm->builder, if_block);
 484
 485         ctx->branch_depth++;
 486         ctx->branch[ctx->branch_depth - 1].endif_block = endif_block;
 487         ctx->branch[ctx->branch_depth - 1].if_block = if_block;
 488         ctx->branch[ctx->branch_depth - 1].else_block = else_block;
 489         ctx->branch[ctx->branch_depth - 1].has_else = 0;
 490 }
 491
 492 static void kil_emit(
 493         const struct lp_build_tgsi_action * action,
 494         struct lp_build_tgsi_context * bld_base,
 495         struct lp_build_emit_data * emit_data)
 496 {
 497         unsigned i;
 498         for (i = 0; i < emit_data->arg_count; i++) {
 499                 emit_data->output[i] = lp_build_intrinsic_unary(
 500                         bld_base->base.gallivm->builder,
 501                         action->intr_name,
 502                         emit_data->dst_type, emit_data->args[i]);
 503         }
 504 }
 505
 506
 507 static void emit_prepare_cube_coords(
 508                 struct lp_build_tgsi_context * bld_base,
 509                 struct lp_build_emit_data * emit_data)
 510 {
 511         boolean shadowcube = (emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE);
 512         struct gallivm_state * gallivm = bld_base->base.gallivm;
 513         LLVMBuilderRef builder = gallivm->builder;
 514         LLVMTypeRef type = bld_base->base.elem_type;
 515         LLVMValueRef coords[4];
 516         LLVMValueRef mad_args[3];
 517         unsigned i, cnt;
 518
 519         LLVMValueRef v = build_intrinsic(builder, "llvm.AMDGPU.cube",
 520                         LLVMVectorType(type, 4),
 521                         &emit_data->args[0],1, LLVMReadNoneAttribute);
 522
 523         /* save src.w for shadow cube */
 524         cnt = shadowcube ? 3 : 4;
 525
 526         for (i = 0; i < cnt; ++i) {
 527                 LLVMValueRef idx = lp_build_const_int32(gallivm, i);
 528                 coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
 529         }
 530
 531         coords[2] = build_intrinsic(builder, "llvm.AMDIL.fabs.",
 532                         type, &coords[2], 1, LLVMReadNoneAttribute);
 533         coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp",
 534                         type, &coords[2], 1, LLVMReadNoneAttribute);
 535
 536         mad_args[1] = coords[2];
 537         mad_args[2] = LLVMConstReal(type, 1.5);
 538
 539         mad_args[0] = coords[0];
 540         coords[0] = build_intrinsic(builder, "llvm.AMDIL.mad.",
 541                         type, mad_args, 3, LLVMReadNoneAttribute);
 542
 543         mad_args[0] = coords[1];
 544         coords[1] = build_intrinsic(builder, "llvm.AMDIL.mad.",
 545                         type, mad_args, 3, LLVMReadNoneAttribute);
 546
 547         /* apply yxwy swizzle to cooords */
 548         coords[2] = coords[3];
 549         coords[3] = coords[1];
 550         coords[1] = coords[0];
 551         coords[0] = coords[3];
 552
 553         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 554                                                 coords, 4);
 555 }
 556
 557 static void txd_fetch_args(
 558         struct lp_build_tgsi_context * bld_base,
 559         struct lp_build_emit_data * emit_data)
 560 {
 561         const struct tgsi_full_instruction * inst = emit_data->inst;
 562
 563         LLVMValueRef coords[4];
 564         unsigned chan, src;
 565         for (src = 0; src < 3; src++) {
 566                 for (chan = 0; chan < 4; chan++)
 567                         coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan);
 568
 569                 emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm,
 570                                 coords, 4);
 571         }
 572         emit_data->arg_count = 3;
 573         emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 574 }
 575
 576
 577 static void txp_fetch_args(
 578         struct lp_build_tgsi_context * bld_base,
 579         struct lp_build_emit_data * emit_data)
 580 {
 581         const struct tgsi_full_instruction * inst = emit_data->inst;
 582         LLVMValueRef src_w;
 583         unsigned chan;
 584         LLVMValueRef coords[4];
 585
 586         emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 587         src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
 588
 589         for (chan = 0; chan < 3; chan++ ) {
 590                 LLVMValueRef arg = lp_build_emit_fetch(bld_base,
 591                                                 emit_data->inst, 0, chan);
 592                 coords[chan] = lp_build_emit_llvm_binary(bld_base,
 593                                         TGSI_OPCODE_DIV, arg, src_w);
 594         }
 595         coords[3] = bld_base->base.one;
 596         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 597                                                 coords, 4);
 598         emit_data->arg_count = 1;
 599
 600         if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
 601              inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
 602             inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
 603                 emit_prepare_cube_coords(bld_base, emit_data);
 604         }
 605 }
 606
 607 static void tex_fetch_args(
 608         struct lp_build_tgsi_context * bld_base,
 609         struct lp_build_emit_data * emit_data)
 610 {
 611         /* XXX: lp_build_swizzle_aos() was failing with wrong arg types,
 612          * when we used CHAN_ALL.  We should be able to get this to work,
 613          * but for now we will swizzle it ourselves
 614         emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
 615                                                  0, CHAN_ALL);
 616
 617         */
 618
 619         const struct tgsi_full_instruction * inst = emit_data->inst;
 620
 621         LLVMValueRef coords[4];
 622         unsigned chan;
 623         for (chan = 0; chan < 4; chan++) {
 624                 coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
 625         }
 626
 627         emit_data->arg_count = 1;
 628         emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm,
 629                                                 coords, 4);
 630         emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
 631
 632         if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
 633              inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
 634             inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
 635                 emit_prepare_cube_coords(bld_base, emit_data);
 636         }
 637 }
 638
 639 static void txf_fetch_args(
 640         struct lp_build_tgsi_context * bld_base,
 641         struct lp_build_emit_data * emit_data)
 642 {
 643         const struct tgsi_full_instruction * inst = emit_data->inst;
 644         struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
 645         const struct tgsi_texture_offset * off = inst->TexOffsets;
 646         LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
 647
 648         /* fetch tex coords */
 649         tex_fetch_args(bld_base, emit_data);
 650
 651         /* fetch tex offsets */
 652         if (inst->Texture.NumOffsets) {
 653                 assert(inst->Texture.NumOffsets == 1);
 654
 655                 emit_data->args[1] = LLVMConstBitCast(
 656                         bld->immediates[off->Index][off->SwizzleX],
 657                         offset_type);
 658                 emit_data->args[2] = LLVMConstBitCast(
 659                         bld->immediates[off->Index][off->SwizzleY],
 660                         offset_type);
 661                 emit_data->args[3] = LLVMConstBitCast(
 662                         bld->immediates[off->Index][off->SwizzleZ],
 663                         offset_type);
 664         } else {
 665                 emit_data->args[1] = bld_base->int_bld.zero;
 666                 emit_data->args[2] = bld_base->int_bld.zero;
 667                 emit_data->args[3] = bld_base->int_bld.zero;
 668         }
 669
 670         emit_data->arg_count = 4;
 671 }
 672
 673 static void emit_icmp(
 674                 const struct lp_build_tgsi_action * action,
 675                 struct lp_build_tgsi_context * bld_base,
 676                 struct lp_build_emit_data * emit_data)
 677 {
 678         unsigned pred;
 679         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 680         LLVMContextRef context = bld_base->base.gallivm->context;
 681
 682         switch (emit_data->inst->Instruction.Opcode) {
 683         case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break;
 684         case TGSI_OPCODE_USNE: pred = LLVMIntNE; break;
 685         case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break;
 686         case TGSI_OPCODE_USLT: pred = LLVMIntULT; break;
 687         case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break;
 688         case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break;
 689         default:
 690                 assert(!"unknown instruction");
 691         }
 692
 693         LLVMValueRef v = LLVMBuildICmp(builder, pred,
 694                         emit_data->args[0], emit_data->args[1],"");
 695
 696         v = LLVMBuildSExtOrBitCast(builder, v,
 697                         LLVMInt32TypeInContext(context), "");
 698
 699         emit_data->output[emit_data->chan] = v;
 700 }
 701
 702 static void emit_cmp(
 703                 const struct lp_build_tgsi_action *action,
 704                 struct lp_build_tgsi_context * bld_base,
 705                 struct lp_build_emit_data * emit_data)
 706 {
 707         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 708         LLVMRealPredicate pred;
 709         LLVMValueRef cond;
 710
 711         /* XXX I'm not sure whether to do unordered or ordered comparisons,
 712          * but llvmpipe uses unordered comparisons, so for consistency we use
 713          * unordered.  (The authors of llvmpipe aren't sure about using
 714          * unordered vs ordered comparisons either.
 715          */
 716         switch (emit_data->inst->Instruction.Opcode) {
 717         case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break;
 718         case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break;
 719         case TGSI_OPCODE_SLE: pred = LLVMRealULE; break;
 720         case TGSI_OPCODE_SLT: pred = LLVMRealULT; break;
 721         case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
 722         case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break;
 723         default: assert(!"unknown instruction");
 724         }
 725
 726         cond = LLVMBuildFCmp(builder,
 727                 pred, emit_data->args[0], emit_data->args[1], "");
 728
 729         emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
 730                 cond, bld_base->base.one, bld_base->base.zero, "");
 731 }
 732
 733 static void emit_not(
 734                 const struct lp_build_tgsi_action * action,
 735                 struct lp_build_tgsi_context * bld_base,
 736                 struct lp_build_emit_data * emit_data)
 737 {
 738         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 739         LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
 740                         emit_data->args[0]);
 741         emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
 742 }
 743
 744 static void emit_and(
 745                 const struct lp_build_tgsi_action * action,
 746                 struct lp_build_tgsi_context * bld_base,
 747                 struct lp_build_emit_data * emit_data)
 748 {
 749         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 750         emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
 751                         emit_data->args[0], emit_data->args[1], "");
 752 }
 753
 754 static void emit_or(
 755                 const struct lp_build_tgsi_action * action,
 756                 struct lp_build_tgsi_context * bld_base,
 757                 struct lp_build_emit_data * emit_data)
 758 {
 759         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 760         emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
 761                         emit_data->args[0], emit_data->args[1], "");
 762 }
 763
 764 static void emit_uadd(
 765                 const struct lp_build_tgsi_action * action,
 766                 struct lp_build_tgsi_context * bld_base,
 767                 struct lp_build_emit_data * emit_data)
 768 {
 769         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 770         emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
 771                         emit_data->args[0], emit_data->args[1], "");
 772 }
 773
 774 static void emit_udiv(
 775                 const struct lp_build_tgsi_action * action,
 776                 struct lp_build_tgsi_context * bld_base,
 777                 struct lp_build_emit_data * emit_data)
 778 {
 779         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 780         emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
 781                         emit_data->args[0], emit_data->args[1], "");
 782 }
 783
 784 static void emit_idiv(
 785                 const struct lp_build_tgsi_action * action,
 786                 struct lp_build_tgsi_context * bld_base,
 787                 struct lp_build_emit_data * emit_data)
 788 {
 789         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 790         emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
 791                         emit_data->args[0], emit_data->args[1], "");
 792 }
 793
 794 static void emit_mod(
 795                 const struct lp_build_tgsi_action * action,
 796                 struct lp_build_tgsi_context * bld_base,
 797                 struct lp_build_emit_data * emit_data)
 798 {
 799         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 800         emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
 801                         emit_data->args[0], emit_data->args[1], "");
 802 }
 803
 804 static void emit_umod(
 805                 const struct lp_build_tgsi_action * action,
 806                 struct lp_build_tgsi_context * bld_base,
 807                 struct lp_build_emit_data * emit_data)
 808 {
 809         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 810         emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
 811                         emit_data->args[0], emit_data->args[1], "");
 812 }
 813
 814 static void emit_shl(
 815                 const struct lp_build_tgsi_action * action,
 816                 struct lp_build_tgsi_context * bld_base,
 817                 struct lp_build_emit_data * emit_data)
 818 {
 819         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 820         emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
 821                         emit_data->args[0], emit_data->args[1], "");
 822 }
 823
 824 static void emit_ushr(
 825                 const struct lp_build_tgsi_action * action,
 826                 struct lp_build_tgsi_context * bld_base,
 827                 struct lp_build_emit_data * emit_data)
 828 {
 829         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 830         emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
 831                         emit_data->args[0], emit_data->args[1], "");
 832 }
 833 static void emit_ishr(
 834                 const struct lp_build_tgsi_action * action,
 835                 struct lp_build_tgsi_context * bld_base,
 836                 struct lp_build_emit_data * emit_data)
 837 {
 838         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 839         emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
 840                         emit_data->args[0], emit_data->args[1], "");
 841 }
 842
 843 static void emit_xor(
 844                 const struct lp_build_tgsi_action * action,
 845                 struct lp_build_tgsi_context * bld_base,
 846                 struct lp_build_emit_data * emit_data)
 847 {
 848         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 849         emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
 850                         emit_data->args[0], emit_data->args[1], "");
 851 }
 852
 853 static void emit_ssg(
 854                 const struct lp_build_tgsi_action * action,
 855                 struct lp_build_tgsi_context * bld_base,
 856                 struct lp_build_emit_data * emit_data)
 857 {
 858         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 859
 860         LLVMValueRef cmp, val;
 861
 862         if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
 863                 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
 864                 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
 865                 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
 866                 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
 867         } else { // float SSG
 868                 cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->int_bld.zero, "");
 869                 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
 870                 cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, "");
 871                 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
 872         }
 873
 874         emit_data->output[emit_data->chan] = val;
 875 }
 876
 877 static void emit_ineg(
 878                 const struct lp_build_tgsi_action * action,
 879                 struct lp_build_tgsi_context * bld_base,
 880                 struct lp_build_emit_data * emit_data)
 881 {
 882         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 883         emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
 884                         emit_data->args[0], "");
 885 }
 886
 887 static void emit_f2i(
 888                 const struct lp_build_tgsi_action * action,
 889                 struct lp_build_tgsi_context * bld_base,
 890                 struct lp_build_emit_data * emit_data)
 891 {
 892         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 893         emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
 894                         emit_data->args[0], bld_base->int_bld.elem_type, "");
 895 }
 896
 897 static void emit_f2u(
 898                 const struct lp_build_tgsi_action * action,
 899                 struct lp_build_tgsi_context * bld_base,
 900                 struct lp_build_emit_data * emit_data)
 901 {
 902         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 903         emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
 904                         emit_data->args[0], bld_base->uint_bld.elem_type, "");
 905 }
 906
 907 static void emit_i2f(
 908                 const struct lp_build_tgsi_action * action,
 909                 struct lp_build_tgsi_context * bld_base,
 910                 struct lp_build_emit_data * emit_data)
 911 {
 912         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 913         emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
 914                         emit_data->args[0], bld_base->base.elem_type, "");
 915 }
 916
 917 static void emit_u2f(
 918                 const struct lp_build_tgsi_action * action,
 919                 struct lp_build_tgsi_context * bld_base,
 920                 struct lp_build_emit_data * emit_data)
 921 {
 922         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
 923         emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
 924                         emit_data->args[0], bld_base->base.elem_type, "");
 925 }
 926
 927 static void emit_immediate(struct lp_build_tgsi_context * bld_base,
 928                 const struct tgsi_full_immediate *imm)
 929 {
 930         unsigned i;
 931         struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 932
 933         for (i = 0; i < 4; ++i) {
 934                 ctx->soa.immediates[ctx->soa.num_immediates][i] =
 935                                 LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false   );
 936         }
 937
 938         ctx->soa.num_immediates++;
 939 }
 940
 941 LLVMValueRef
 942 build_intrinsic(LLVMBuilderRef builder,
 943                    const char *name,
 944                    LLVMTypeRef ret_type,
 945                    LLVMValueRef *args,
 946                    unsigned num_args,
 947                    LLVMAttribute attr)
 948 {
 949    LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder)));
 950    LLVMValueRef function;
 951
 952    function = LLVMGetNamedFunction(module, name);
 953    if(!function) {
 954       LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS];
 955       unsigned i;
 956
 957       assert(num_args <= LP_MAX_FUNC_ARGS);
 958
 959       for(i = 0; i < num_args; ++i) {
 960          assert(args[i]);
 961          arg_types[i] = LLVMTypeOf(args[i]);
 962       }
 963
 964       function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args);
 965
 966       if (attr)
 967           LLVMAddFunctionAttr(function, attr);
 968    }
 969
 970    return LLVMBuildCall(builder, function, args, num_args, "");
 971 }
 972
 973 void
 974 build_tgsi_intrinsic_nomem(
 975  const struct lp_build_tgsi_action * action,
 976  struct lp_build_tgsi_context * bld_base,
 977  struct lp_build_emit_data * emit_data)
 978 {
 979    struct lp_build_context * base = &bld_base->base;
 980    emit_data->output[emit_data->chan] = build_intrinsic(
 981                base->gallivm->builder, action->intr_name,
 982                emit_data->dst_type, emit_data->args,
 983                emit_data->arg_count, LLVMReadNoneAttribute);
 984 }
 985
 986 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 987 {
 988         struct lp_type type;
 989         LLVMTypeRef main_fn_type;
 990         LLVMBasicBlockRef main_fn_body;
 991
 992         /* Initialize the gallivm object:
 993          * We are only using the module, context, and builder fields of this struct.
 994          * This should be enough for us to be able to pass our gallivm struct to the
 995          * helper functions in the gallivm module.
 996          */
 997         memset(&ctx->gallivm, 0, sizeof (ctx->gallivm));
 998         memset(&ctx->soa, 0, sizeof(ctx->soa));
 999         ctx->gallivm.context = LLVMContextCreate();
1000         ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi",
1001                                                 ctx->gallivm.context);
1002         ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context);
1003
1004         /* Setup the module */
1005         main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context),
1006                                          NULL, 0, 0);
1007         ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type);
1008         main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context,
1009                         ctx->main_fn, "main_body");
1010          LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
1011
1012         ctx->store_output_intr = "llvm.AMDGPU.store.output.";
1013         ctx->swizzle_intr = "llvm.AMDGPU.swizzle";
1014         struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
1015
1016         /* XXX: We need to revisit this.I think the correct way to do this is
1017          * to use length = 4 here and use the elem_bld for everything. */
1018         type.floating = TRUE;
1019         type.sign = TRUE;
1020         type.width = 32;
1021         type.length = 1;
1022
1023         lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
1024         lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type));
1025         lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type));
1026
1027         bld_base->soa = 1;
1028         bld_base->emit_store = emit_store;
1029         bld_base->emit_swizzle = emit_swizzle;
1030         bld_base->emit_declaration = emit_declaration;
1031         bld_base->emit_immediate = emit_immediate;
1032
1033         bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch_immediate;
1034         bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch_input;
1035         bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch_temporary;
1036         bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch_output;
1037
1038         /* Allocate outputs */
1039         ctx->soa.outputs = ctx->outputs;
1040
1041         /* XXX: Is there a better way to initialize all this ? */
1042
1043         lp_set_default_actions(bld_base);
1044
1045         bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem;
1046         bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs.";
1047         bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
1048         bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
1049         bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
1050         bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
1051         bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
1052         bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
1053         bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
1054         bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
1055         bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
1056         bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
1057         bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
1058         bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
1059         bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
1060         bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
1061         bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
1062         bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
1063         bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
1064         bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
1065         bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
1066         bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx";
1067         bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
1068         bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
1069         bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
1070         bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
1071         bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
1072         bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
1073         bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
1074         bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
1075         bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
1076         bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
1077         bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
1078         bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
1079         bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
1080         bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
1081         bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
1082         bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem;
1083         bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin";
1084         bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem;
1085         bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax";
1086         bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem;
1087         bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
1088         bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
1089         bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
1090         bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
1091         bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
1092         bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
1093         bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
1094         bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
1095         bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf.";
1096
1097
1098
1099         bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
1100         bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.AMDIL.fabs.";
1101         bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
1102         bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
1103         bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
1104         bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;
1105         bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit;
1106         bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem;
1107         bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
1108         bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
1109         bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
1110         bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
1111         bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos";
1112         bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
1113         bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
1114         bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
1115         bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
1116         bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
1117         bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
1118         bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
1119         bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
1120         bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor";
1121         bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
1122         bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction.";
1123         bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;
1124         bld_base->op_actions[TGSI_OPCODE_KIL].emit = kil_emit;
1125         bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
1126         bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
1127         bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
1128         bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
1129         bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log.";
1130         bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
1131         bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
1132         bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
1133         bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
1134         bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
1135         bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
1136         bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
1137         bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
1138         bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
1139         bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
1140         bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
1141         bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.AMDGPU.pow";
1142         bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
1143         bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
1144         bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;
1145         bld_base->op_actions[TGSI_OPCODE_SSG].intr_name = "llvm.AMDGPU.ssg";
1146         bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
1147         bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;
1148         bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp;
1149         bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
1150         bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp;
1151         bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp;
1152         bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
1153         bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.AMDGPU.sin";
1154         bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args;
1155         bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex";
1156         bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args;
1157         bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb";
1158         bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args;
1159         bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd";
1160         bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args;
1161         bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl";
1162         bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args;
1163         bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex";
1164         bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
1165         bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc";
1166
1167         bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
1168         bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
1169 }
1170
1171 void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx)
1172 {
1173         struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm;
1174         /* End the main function with Return*/
1175         LLVMBuildRetVoid(gallivm->builder);
1176
1177         /* Create the pass manager */
1178         ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule(
1179                                                         gallivm->module);
1180
1181         /* This pass should eliminate all the load and store instructions */
1182         LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
1183
1184         /* Add some optimization passes */
1185         LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
1186         LLVMAddCFGSimplificationPass(gallivm->passmgr);
1187
1188         /* Run the passs */
1189         LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
1190
1191         LLVMDisposeBuilder(gallivm->builder);
1192         LLVMDisposePassManager(gallivm->passmgr);
1193
1194 }
1195
1196 void radeon_llvm_dispose(struct radeon_llvm_context * ctx)
1197 {
1198         LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
1199         LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
1200 }