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gallium/radeon: remove radeon_surf_level::pitch_bytes
[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_codec.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "r600_pipe_common.h"
49 #include "radeon_video.h"
50 #include "radeon_uvd.h"
51
52 #define NUM_BUFFERS 4
53
54 #define NUM_MPEG2_REFS 6
55 #define NUM_H264_REFS 17
56 #define NUM_VC1_REFS 5
57
58 #define FB_BUFFER_OFFSET 0x1000
59 #define FB_BUFFER_SIZE 2048
60 #define FB_BUFFER_SIZE_TONGA (2048 * 64)
61 #define IT_SCALING_TABLE_SIZE 992
62 #define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
63
64 /* UVD decoder representation */
65 struct ruvd_decoder {
66 struct pipe_video_codec base;
67
68 ruvd_set_dtb set_dtb;
69
70 unsigned stream_handle;
71 unsigned stream_type;
72 unsigned frame_number;
73
74 struct pipe_screen *screen;
75 struct radeon_winsys* ws;
76 struct radeon_winsys_cs* cs;
77
78 unsigned cur_buffer;
79
80 struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
81 struct ruvd_msg *msg;
82 uint32_t *fb;
83 unsigned fb_size;
84 uint8_t *it;
85
86 struct rvid_buffer bs_buffers[NUM_BUFFERS];
87 void* bs_ptr;
88 unsigned bs_size;
89
90 struct rvid_buffer dpb;
91 bool use_legacy;
92 struct rvid_buffer ctx;
93 struct rvid_buffer sessionctx;
94 };
95
96 /* flush IB to the hardware */
97 static int flush(struct ruvd_decoder *dec, unsigned flags)
98 {
99 return dec->ws->cs_flush(dec->cs, flags, NULL);
100 }
101
102 /* add a new set register command to the IB */
103 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
104 {
105 radeon_emit(dec->cs, RUVD_PKT0(reg >> 2, 0));
106 radeon_emit(dec->cs, val);
107 }
108
109 /* send a command to the VCPU through the GPCOM registers */
110 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
111 struct pb_buffer* buf, uint32_t off,
112 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
113 {
114 int reloc_idx;
115
116 reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
117 domain,
118 RADEON_PRIO_UVD);
119 if (!dec->use_legacy) {
120 uint64_t addr;
121 addr = dec->ws->buffer_get_virtual_address(buf);
122 addr = addr + off;
123 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
124 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
125 } else {
126 off += dec->ws->buffer_get_reloc_offset(buf);
127 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
128 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
129 }
130 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
131 }
132
133 /* do the codec needs an IT buffer ?*/
134 static bool have_it(struct ruvd_decoder *dec)
135 {
136 return dec->stream_type == RUVD_CODEC_H264_PERF ||
137 dec->stream_type == RUVD_CODEC_H265;
138 }
139
140 /* map the next available message/feedback/itscaling buffer */
141 static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
142 {
143 struct rvid_buffer* buf;
144 uint8_t *ptr;
145
146 /* grab the current message/feedback buffer */
147 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
148
149 /* and map it for CPU access */
150 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
151
152 /* calc buffer offsets */
153 dec->msg = (struct ruvd_msg *)ptr;
154 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
155 if (have_it(dec))
156 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
157 }
158
159 /* unmap and send a message command to the VCPU */
160 static void send_msg_buf(struct ruvd_decoder *dec)
161 {
162 struct rvid_buffer* buf;
163
164 /* ignore the request if message/feedback buffer isn't mapped */
165 if (!dec->msg || !dec->fb)
166 return;
167
168 /* grab the current message buffer */
169 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
170
171 /* unmap the buffer */
172 dec->ws->buffer_unmap(buf->res->buf);
173 dec->msg = NULL;
174 dec->fb = NULL;
175 dec->it = NULL;
176
177
178 if (dec->sessionctx.res)
179 send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER,
180 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
181 RADEON_DOMAIN_VRAM);
182
183 /* and send it to the hardware */
184 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0,
185 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
186 }
187
188 /* cycle to the next set of buffers */
189 static void next_buffer(struct ruvd_decoder *dec)
190 {
191 ++dec->cur_buffer;
192 dec->cur_buffer %= NUM_BUFFERS;
193 }
194
195 /* convert the profile into something UVD understands */
196 static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
197 {
198 switch (u_reduce_video_profile(dec->base.profile)) {
199 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
200 return (family >= CHIP_TONGA) ?
201 RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
202
203 case PIPE_VIDEO_FORMAT_VC1:
204 return RUVD_CODEC_VC1;
205
206 case PIPE_VIDEO_FORMAT_MPEG12:
207 return RUVD_CODEC_MPEG2;
208
209 case PIPE_VIDEO_FORMAT_MPEG4:
210 return RUVD_CODEC_MPEG4;
211
212 case PIPE_VIDEO_FORMAT_HEVC:
213 return RUVD_CODEC_H265;
214
215 default:
216 assert(0);
217 return 0;
218 }
219 }
220
221 static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
222 {
223 unsigned width_in_mb, height_in_mb, ctx_size;
224 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
225 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
226
227 unsigned max_references = dec->base.max_references + 1;
228
229 // picture width & height in 16 pixel units
230 width_in_mb = width / VL_MACROBLOCK_WIDTH;
231 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
232
233 if (!dec->use_legacy) {
234 unsigned fs_in_mb = width_in_mb * height_in_mb;
235 unsigned num_dpb_buffer;
236 switch(dec->base.level) {
237 case 30:
238 num_dpb_buffer = 8100 / fs_in_mb;
239 break;
240 case 31:
241 num_dpb_buffer = 18000 / fs_in_mb;
242 break;
243 case 32:
244 num_dpb_buffer = 20480 / fs_in_mb;
245 break;
246 case 41:
247 num_dpb_buffer = 32768 / fs_in_mb;
248 break;
249 case 42:
250 num_dpb_buffer = 34816 / fs_in_mb;
251 break;
252 case 50:
253 num_dpb_buffer = 110400 / fs_in_mb;
254 break;
255 case 51:
256 num_dpb_buffer = 184320 / fs_in_mb;
257 break;
258 default:
259 num_dpb_buffer = 184320 / fs_in_mb;
260 break;
261 }
262 num_dpb_buffer++;
263 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
264 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
265 } else {
266 // the firmware seems to always assume a minimum of ref frames
267 max_references = MAX2(NUM_H264_REFS, max_references);
268 // macroblock context buffer
269 ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
270 }
271
272 return ctx_size;
273 }
274
275 static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
276 {
277 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
278 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
279
280 unsigned max_references = dec->base.max_references + 1;
281
282 if (dec->base.width * dec->base.height >= 4096*2000)
283 max_references = MAX2(max_references, 8);
284 else
285 max_references = MAX2(max_references, 17);
286
287 width = align (width, 16);
288 height = align (height, 16);
289 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
290 }
291
292 static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_h265_picture_desc *pic)
293 {
294 unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
295 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
296 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
297
298 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
299 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
300 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
301
302 unsigned max_references = dec->base.max_references + 1;
303
304 if (dec->base.width * dec->base.height >= 4096*2000)
305 max_references = MAX2(max_references, 8);
306 else
307 max_references = MAX2(max_references, 17);
308
309 block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
310 log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
311
312 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
313 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
314
315 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
316 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
317 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
318
319 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
320 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
321
322 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
323 }
324
325 /* calculate size of reference picture buffer */
326 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
327 {
328 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
329
330 // always align them to MB size for dpb calculation
331 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
332 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
333
334 // always one more for currently decoded picture
335 unsigned max_references = dec->base.max_references + 1;
336
337 // aligned size of a single frame
338 image_size = width * height;
339 image_size += image_size / 2;
340 image_size = align(image_size, 1024);
341
342 // picture width & height in 16 pixel units
343 width_in_mb = width / VL_MACROBLOCK_WIDTH;
344 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
345
346 switch (u_reduce_video_profile(dec->base.profile)) {
347 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
348 if (!dec->use_legacy) {
349 unsigned fs_in_mb = width_in_mb * height_in_mb;
350 unsigned alignment = 64, num_dpb_buffer;
351
352 if (dec->stream_type == RUVD_CODEC_H264_PERF)
353 alignment = 256;
354 switch(dec->base.level) {
355 case 30:
356 num_dpb_buffer = 8100 / fs_in_mb;
357 break;
358 case 31:
359 num_dpb_buffer = 18000 / fs_in_mb;
360 break;
361 case 32:
362 num_dpb_buffer = 20480 / fs_in_mb;
363 break;
364 case 41:
365 num_dpb_buffer = 32768 / fs_in_mb;
366 break;
367 case 42:
368 num_dpb_buffer = 34816 / fs_in_mb;
369 break;
370 case 50:
371 num_dpb_buffer = 110400 / fs_in_mb;
372 break;
373 case 51:
374 num_dpb_buffer = 184320 / fs_in_mb;
375 break;
376 default:
377 num_dpb_buffer = 184320 / fs_in_mb;
378 break;
379 }
380 num_dpb_buffer++;
381 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
382 dpb_size = image_size * max_references;
383 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
384 (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
385 dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
386 dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
387 }
388 } else {
389 // the firmware seems to allways assume a minimum of ref frames
390 max_references = MAX2(NUM_H264_REFS, max_references);
391 // reference picture buffer
392 dpb_size = image_size * max_references;
393 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
394 (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
395 // macroblock context buffer
396 dpb_size += width_in_mb * height_in_mb * max_references * 192;
397 // IT surface buffer
398 dpb_size += width_in_mb * height_in_mb * 32;
399 }
400 }
401 break;
402 }
403
404 case PIPE_VIDEO_FORMAT_HEVC:
405 if (dec->base.width * dec->base.height >= 4096*2000)
406 max_references = MAX2(max_references, 8);
407 else
408 max_references = MAX2(max_references, 17);
409
410 width = align (width, 16);
411 height = align (height, 16);
412 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
413 dpb_size = align((width * height * 9) / 4, 256) * max_references;
414 else
415 dpb_size = align((width * height * 3) / 2, 256) * max_references;
416 break;
417
418 case PIPE_VIDEO_FORMAT_VC1:
419 // the firmware seems to allways assume a minimum of ref frames
420 max_references = MAX2(NUM_VC1_REFS, max_references);
421
422 // reference picture buffer
423 dpb_size = image_size * max_references;
424
425 // CONTEXT_BUFFER
426 dpb_size += width_in_mb * height_in_mb * 128;
427
428 // IT surface buffer
429 dpb_size += width_in_mb * 64;
430
431 // DB surface buffer
432 dpb_size += width_in_mb * 128;
433
434 // BP
435 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
436 break;
437
438 case PIPE_VIDEO_FORMAT_MPEG12:
439 // reference picture buffer, must be big enough for all frames
440 dpb_size = image_size * NUM_MPEG2_REFS;
441 break;
442
443 case PIPE_VIDEO_FORMAT_MPEG4:
444 // reference picture buffer
445 dpb_size = image_size * max_references;
446
447 // CM
448 dpb_size += width_in_mb * height_in_mb * 64;
449
450 // IT surface buffer
451 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
452
453 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
454 break;
455
456 default:
457 // something is missing here
458 assert(0);
459
460 // at least use a sane default value
461 dpb_size = 32 * 1024 * 1024;
462 break;
463 }
464 return dpb_size;
465 }
466
467 /* free associated data in the video buffer callback */
468 static void ruvd_destroy_associated_data(void *data)
469 {
470 /* NOOP, since we only use an intptr */
471 }
472
473 /* get h264 specific message bits */
474 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
475 {
476 struct ruvd_h264 result;
477
478 memset(&result, 0, sizeof(result));
479 switch (pic->base.profile) {
480 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
481 result.profile = RUVD_H264_PROFILE_BASELINE;
482 break;
483
484 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
485 result.profile = RUVD_H264_PROFILE_MAIN;
486 break;
487
488 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
489 result.profile = RUVD_H264_PROFILE_HIGH;
490 break;
491
492 default:
493 assert(0);
494 break;
495 }
496
497 result.level = dec->base.level;
498
499 result.sps_info_flags = 0;
500 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
501 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
502 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
503 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
504
505 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
506 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
507 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
508 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
509 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
510
511 switch (dec->base.chroma_format) {
512 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
513 /* TODO: assert? */
514 break;
515 case PIPE_VIDEO_CHROMA_FORMAT_400:
516 result.chroma_format = 0;
517 break;
518 case PIPE_VIDEO_CHROMA_FORMAT_420:
519 result.chroma_format = 1;
520 break;
521 case PIPE_VIDEO_CHROMA_FORMAT_422:
522 result.chroma_format = 2;
523 break;
524 case PIPE_VIDEO_CHROMA_FORMAT_444:
525 result.chroma_format = 3;
526 break;
527 }
528
529 result.pps_info_flags = 0;
530 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
531 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
532 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
533 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
534 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
535 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
536 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
537 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
538
539 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
540 result.slice_group_map_type = pic->pps->slice_group_map_type;
541 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
542 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
543 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
544 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
545
546 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
547 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
548
549 if (dec->stream_type == RUVD_CODEC_H264_PERF) {
550 memcpy(dec->it, result.scaling_list_4x4, 6*16);
551 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
552 }
553
554 result.num_ref_frames = pic->num_ref_frames;
555
556 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
557 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
558
559 result.frame_num = pic->frame_num;
560 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
561 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
562 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
563 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
564
565 result.decoded_pic_idx = pic->frame_num;
566
567 return result;
568 }
569
570 /* get h265 specific message bits */
571 static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video_buffer *target,
572 struct pipe_h265_picture_desc *pic)
573 {
574 struct ruvd_h265 result;
575 unsigned i;
576
577 memset(&result, 0, sizeof(result));
578
579 result.sps_info_flags = 0;
580 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
581 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
582 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
583 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
584 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
585 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
586 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
587 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
588 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
589 if (((struct r600_common_screen*)dec->screen)->family == CHIP_CARRIZO)
590 result.sps_info_flags |= 1 << 9;
591 if (pic->UseRefPicList == true)
592 result.sps_info_flags |= 1 << 10;
593
594 result.chroma_format = pic->pps->sps->chroma_format_idc;
595 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
596 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
597 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
598 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
599 result.log2_min_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_luma_coding_block_size_minus3;
600 result.log2_diff_max_min_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
601 result.log2_min_transform_block_size_minus2 = pic->pps->sps->log2_min_transform_block_size_minus2;
602 result.log2_diff_max_min_transform_block_size = pic->pps->sps->log2_diff_max_min_transform_block_size;
603 result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
604 result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
605 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
606 result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
607 result.log2_min_pcm_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
608 result.log2_diff_max_min_pcm_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
609 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
610
611 result.pps_info_flags = 0;
612 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
613 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
614 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
615 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
616 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
617 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
618 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
619 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
620 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
621 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
622 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
623 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
624 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
625 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
626 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
627 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
628 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
629 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
630 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
631 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
632 //result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag; ???
633
634 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
635 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
636 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
637 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
638 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
639 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
640 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
641 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
642 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
643 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
644 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
645 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
646 result.init_qp_minus26 = pic->pps->init_qp_minus26;
647
648 for (i = 0; i < 19; ++i)
649 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
650
651 for (i = 0; i < 21; ++i)
652 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
653
654 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
655 result.curr_idx = pic->CurrPicOrderCntVal;
656 result.curr_poc = pic->CurrPicOrderCntVal;
657
658 vl_video_buffer_set_associated_data(target, &dec->base,
659 (void *)(uintptr_t)pic->CurrPicOrderCntVal,
660 &ruvd_destroy_associated_data);
661
662 for (i = 0; i < 16; ++i) {
663 struct pipe_video_buffer *ref = pic->ref[i];
664 uintptr_t ref_pic = 0;
665
666 result.poc_list[i] = pic->PicOrderCntVal[i];
667
668 if (ref)
669 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
670 else
671 ref_pic = 0x7F;
672 result.ref_pic_list[i] = ref_pic;
673 }
674
675 for (i = 0; i < 8; ++i) {
676 result.ref_pic_set_st_curr_before[i] = 0xFF;
677 result.ref_pic_set_st_curr_after[i] = 0xFF;
678 result.ref_pic_set_lt_curr[i] = 0xFF;
679 }
680
681 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
682 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
683
684 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
685 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
686
687 for (i = 0; i < pic->NumPocLtCurr; ++i)
688 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
689
690 for (i = 0; i < 6; ++i)
691 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
692
693 for (i = 0; i < 2; ++i)
694 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
695
696 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
697 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
698 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
699 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
700
701 for (i = 0 ; i < 2 ; i++) {
702 for (int j = 0 ; j < 15 ; j++)
703 result.direct_reflist[i][j] = pic->RefPicList[i][j];
704 }
705
706 if ((pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) &&
707 (target->buffer_format == PIPE_FORMAT_NV12)) {
708 result.p010_mode = 0;
709 result.luma_10to8 = 5;
710 result.chroma_10to8 = 5;
711 result.sclr_luma10to8 = 4;
712 result.sclr_chroma10to8 = 4;
713 }
714
715 /* TODO
716 result.highestTid;
717 result.isNonRef;
718
719 IDRPicFlag;
720 RAPPicFlag;
721 NumPocTotalCurr;
722 NumShortTermPictureSliceHeaderBits;
723 NumLongTermPictureSliceHeaderBits;
724
725 IsLongTerm[16];
726 */
727
728 return result;
729 }
730
731 /* get vc1 specific message bits */
732 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
733 {
734 struct ruvd_vc1 result;
735
736 memset(&result, 0, sizeof(result));
737
738 switch(pic->base.profile) {
739 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
740 result.profile = RUVD_VC1_PROFILE_SIMPLE;
741 result.level = 1;
742 break;
743
744 case PIPE_VIDEO_PROFILE_VC1_MAIN:
745 result.profile = RUVD_VC1_PROFILE_MAIN;
746 result.level = 2;
747 break;
748
749 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
750 result.profile = RUVD_VC1_PROFILE_ADVANCED;
751 result.level = 4;
752 break;
753
754 default:
755 assert(0);
756 }
757
758 /* fields common for all profiles */
759 result.sps_info_flags |= pic->postprocflag << 7;
760 result.sps_info_flags |= pic->pulldown << 6;
761 result.sps_info_flags |= pic->interlace << 5;
762 result.sps_info_flags |= pic->tfcntrflag << 4;
763 result.sps_info_flags |= pic->finterpflag << 3;
764 result.sps_info_flags |= pic->psf << 1;
765
766 result.pps_info_flags |= pic->range_mapy_flag << 31;
767 result.pps_info_flags |= pic->range_mapy << 28;
768 result.pps_info_flags |= pic->range_mapuv_flag << 27;
769 result.pps_info_flags |= pic->range_mapuv << 24;
770 result.pps_info_flags |= pic->multires << 21;
771 result.pps_info_flags |= pic->maxbframes << 16;
772 result.pps_info_flags |= pic->overlap << 11;
773 result.pps_info_flags |= pic->quantizer << 9;
774 result.pps_info_flags |= pic->panscan_flag << 7;
775 result.pps_info_flags |= pic->refdist_flag << 6;
776 result.pps_info_flags |= pic->vstransform << 0;
777
778 /* some fields only apply to main/advanced profile */
779 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
780 result.pps_info_flags |= pic->syncmarker << 20;
781 result.pps_info_flags |= pic->rangered << 19;
782 result.pps_info_flags |= pic->loopfilter << 5;
783 result.pps_info_flags |= pic->fastuvmc << 4;
784 result.pps_info_flags |= pic->extended_mv << 3;
785 result.pps_info_flags |= pic->extended_dmv << 8;
786 result.pps_info_flags |= pic->dquant << 1;
787 }
788
789 result.chroma_format = 1;
790
791 #if 0
792 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
793 uint32_t slice_count
794 uint8_t picture_type
795 uint8_t frame_coding_mode
796 uint8_t deblockEnable
797 uint8_t pquant
798 #endif
799
800 return result;
801 }
802
803 /* extract the frame number from a referenced video buffer */
804 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
805 {
806 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
807 uint32_t max = MAX2(dec->frame_number, 1) - 1;
808 uintptr_t frame;
809
810 /* seems to be the most sane fallback */
811 if (!ref)
812 return max;
813
814 /* get the frame number from the associated data */
815 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
816
817 /* limit the frame number to a valid range */
818 return MAX2(MIN2(frame, max), min);
819 }
820
821 /* get mpeg2 specific msg bits */
822 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
823 struct pipe_mpeg12_picture_desc *pic)
824 {
825 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
826 struct ruvd_mpeg2 result;
827 unsigned i;
828
829 memset(&result, 0, sizeof(result));
830 result.decoded_pic_idx = dec->frame_number;
831 for (i = 0; i < 2; ++i)
832 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
833
834 result.load_intra_quantiser_matrix = 1;
835 result.load_nonintra_quantiser_matrix = 1;
836
837 for (i = 0; i < 64; ++i) {
838 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
839 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
840 }
841
842 result.profile_and_level_indication = 0;
843 result.chroma_format = 0x1;
844
845 result.picture_coding_type = pic->picture_coding_type;
846 result.f_code[0][0] = pic->f_code[0][0] + 1;
847 result.f_code[0][1] = pic->f_code[0][1] + 1;
848 result.f_code[1][0] = pic->f_code[1][0] + 1;
849 result.f_code[1][1] = pic->f_code[1][1] + 1;
850 result.intra_dc_precision = pic->intra_dc_precision;
851 result.pic_structure = pic->picture_structure;
852 result.top_field_first = pic->top_field_first;
853 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
854 result.concealment_motion_vectors = pic->concealment_motion_vectors;
855 result.q_scale_type = pic->q_scale_type;
856 result.intra_vlc_format = pic->intra_vlc_format;
857 result.alternate_scan = pic->alternate_scan;
858
859 return result;
860 }
861
862 /* get mpeg4 specific msg bits */
863 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
864 struct pipe_mpeg4_picture_desc *pic)
865 {
866 struct ruvd_mpeg4 result;
867 unsigned i;
868
869 memset(&result, 0, sizeof(result));
870 result.decoded_pic_idx = dec->frame_number;
871 for (i = 0; i < 2; ++i)
872 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
873
874 result.variant_type = 0;
875 result.profile_and_level_indication = 0xF0; // ASP Level0
876
877 result.video_object_layer_verid = 0x5; // advanced simple
878 result.video_object_layer_shape = 0x0; // rectangular
879
880 result.video_object_layer_width = dec->base.width;
881 result.video_object_layer_height = dec->base.height;
882
883 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
884
885 result.flags |= pic->short_video_header << 0;
886 //result.flags |= obmc_disable << 1;
887 result.flags |= pic->interlaced << 2;
888 result.flags |= 1 << 3; // load_intra_quant_mat
889 result.flags |= 1 << 4; // load_nonintra_quant_mat
890 result.flags |= pic->quarter_sample << 5;
891 result.flags |= 1 << 6; // complexity_estimation_disable
892 result.flags |= pic->resync_marker_disable << 7;
893 //result.flags |= data_partitioned << 8;
894 //result.flags |= reversible_vlc << 9;
895 result.flags |= 0 << 10; // newpred_enable
896 result.flags |= 0 << 11; // reduced_resolution_vop_enable
897 //result.flags |= scalability << 12;
898 //result.flags |= is_object_layer_identifier << 13;
899 //result.flags |= fixed_vop_rate << 14;
900 //result.flags |= newpred_segment_type << 15;
901
902 result.quant_type = pic->quant_type;
903
904 for (i = 0; i < 64; ++i) {
905 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
906 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
907 }
908
909 /*
910 int32_t trd [2]
911 int32_t trb [2]
912 uint8_t vop_coding_type
913 uint8_t vop_fcode_forward
914 uint8_t vop_fcode_backward
915 uint8_t rounding_control
916 uint8_t alternate_vertical_scan_flag
917 uint8_t top_field_first
918 */
919
920 return result;
921 }
922
923 /**
924 * destroy this video decoder
925 */
926 static void ruvd_destroy(struct pipe_video_codec *decoder)
927 {
928 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
929 unsigned i;
930
931 assert(decoder);
932
933 map_msg_fb_it_buf(dec);
934 memset(dec->msg, 0, sizeof(*dec->msg));
935 dec->msg->size = sizeof(*dec->msg);
936 dec->msg->msg_type = RUVD_MSG_DESTROY;
937 dec->msg->stream_handle = dec->stream_handle;
938 send_msg_buf(dec);
939
940 flush(dec, 0);
941
942 dec->ws->cs_destroy(dec->cs);
943
944 for (i = 0; i < NUM_BUFFERS; ++i) {
945 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
946 rvid_destroy_buffer(&dec->bs_buffers[i]);
947 }
948
949 rvid_destroy_buffer(&dec->dpb);
950 rvid_destroy_buffer(&dec->ctx);
951 rvid_destroy_buffer(&dec->sessionctx);
952
953 FREE(dec);
954 }
955
956 /**
957 * start decoding of a new frame
958 */
959 static void ruvd_begin_frame(struct pipe_video_codec *decoder,
960 struct pipe_video_buffer *target,
961 struct pipe_picture_desc *picture)
962 {
963 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
964 uintptr_t frame;
965
966 assert(decoder);
967
968 frame = ++dec->frame_number;
969 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
970 &ruvd_destroy_associated_data);
971
972 dec->bs_size = 0;
973 dec->bs_ptr = dec->ws->buffer_map(
974 dec->bs_buffers[dec->cur_buffer].res->buf,
975 dec->cs, PIPE_TRANSFER_WRITE);
976 }
977
978 /**
979 * decode a macroblock
980 */
981 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
982 struct pipe_video_buffer *target,
983 struct pipe_picture_desc *picture,
984 const struct pipe_macroblock *macroblocks,
985 unsigned num_macroblocks)
986 {
987 /* not supported (yet) */
988 assert(0);
989 }
990
991 /**
992 * decode a bitstream
993 */
994 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
995 struct pipe_video_buffer *target,
996 struct pipe_picture_desc *picture,
997 unsigned num_buffers,
998 const void * const *buffers,
999 const unsigned *sizes)
1000 {
1001 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
1002 unsigned i;
1003
1004 assert(decoder);
1005
1006 if (!dec->bs_ptr)
1007 return;
1008
1009 for (i = 0; i < num_buffers; ++i) {
1010 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1011 unsigned new_size = dec->bs_size + sizes[i];
1012
1013 if (new_size > buf->res->buf->size) {
1014 dec->ws->buffer_unmap(buf->res->buf);
1015 if (!rvid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1016 RVID_ERR("Can't resize bitstream buffer!");
1017 return;
1018 }
1019
1020 dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1021 PIPE_TRANSFER_WRITE);
1022 if (!dec->bs_ptr)
1023 return;
1024
1025 dec->bs_ptr += dec->bs_size;
1026 }
1027
1028 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1029 dec->bs_size += sizes[i];
1030 dec->bs_ptr += sizes[i];
1031 }
1032 }
1033
1034 /**
1035 * end decoding of the current frame
1036 */
1037 static void ruvd_end_frame(struct pipe_video_codec *decoder,
1038 struct pipe_video_buffer *target,
1039 struct pipe_picture_desc *picture)
1040 {
1041 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
1042 struct pb_buffer *dt;
1043 struct rvid_buffer *msg_fb_it_buf, *bs_buf;
1044 unsigned bs_size;
1045
1046 assert(decoder);
1047
1048 if (!dec->bs_ptr)
1049 return;
1050
1051 msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
1052 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1053
1054 bs_size = align(dec->bs_size, 128);
1055 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
1056 dec->ws->buffer_unmap(bs_buf->res->buf);
1057
1058 map_msg_fb_it_buf(dec);
1059 dec->msg->size = sizeof(*dec->msg);
1060 dec->msg->msg_type = RUVD_MSG_DECODE;
1061 dec->msg->stream_handle = dec->stream_handle;
1062 dec->msg->status_report_feedback_number = dec->frame_number;
1063
1064 dec->msg->body.decode.stream_type = dec->stream_type;
1065 dec->msg->body.decode.decode_flags = 0x1;
1066 dec->msg->body.decode.width_in_samples = dec->base.width;
1067 dec->msg->body.decode.height_in_samples = dec->base.height;
1068
1069 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
1070 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
1071 dec->msg->body.decode.width_in_samples = align(dec->msg->body.decode.width_in_samples, 16) / 16;
1072 dec->msg->body.decode.height_in_samples = align(dec->msg->body.decode.height_in_samples, 16) / 16;
1073 }
1074
1075 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1076 dec->msg->body.decode.bsd_size = bs_size;
1077 dec->msg->body.decode.db_pitch = align(dec->base.width, 16);
1078
1079 if (dec->stream_type == RUVD_CODEC_H264_PERF &&
1080 ((struct r600_common_screen*)dec->screen)->family >= CHIP_POLARIS10)
1081 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1082
1083 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
1084 if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
1085 dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
1086
1087 switch (u_reduce_video_profile(picture->profile)) {
1088 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1089 dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
1090 break;
1091
1092 case PIPE_VIDEO_FORMAT_HEVC:
1093 dec->msg->body.decode.codec.h265 = get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
1094 if (dec->ctx.res == NULL) {
1095 unsigned ctx_size;
1096 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1097 ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc*)picture);
1098 else
1099 ctx_size = calc_ctx_size_h265_main(dec);
1100 if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1101 RVID_ERR("Can't allocated context buffer.\n");
1102 }
1103 rvid_clear_buffer(decoder->context, &dec->ctx);
1104 }
1105
1106 if (dec->ctx.res)
1107 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1108 break;
1109
1110 case PIPE_VIDEO_FORMAT_VC1:
1111 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
1112 break;
1113
1114 case PIPE_VIDEO_FORMAT_MPEG12:
1115 dec->msg->body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
1116 break;
1117
1118 case PIPE_VIDEO_FORMAT_MPEG4:
1119 dec->msg->body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
1120 break;
1121
1122 default:
1123 assert(0);
1124 return;
1125 }
1126
1127 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
1128 dec->msg->body.decode.extension_support = 0x1;
1129
1130 /* set at least the feedback buffer size */
1131 dec->fb[0] = dec->fb_size;
1132
1133 send_msg_buf(dec);
1134
1135 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1136 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1137 if (dec->ctx.res)
1138 send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1139 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1140 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1141 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1142 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
1143 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1144 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf,
1145 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1146 if (have_it(dec))
1147 send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
1148 FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1149 set_reg(dec, RUVD_ENGINE_CNTL, 1);
1150
1151 flush(dec, RADEON_FLUSH_ASYNC);
1152 next_buffer(dec);
1153 }
1154
1155 /**
1156 * flush any outstanding command buffers to the hardware
1157 */
1158 static void ruvd_flush(struct pipe_video_codec *decoder)
1159 {
1160 }
1161
1162 /**
1163 * create and UVD decoder
1164 */
1165 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
1166 const struct pipe_video_codec *templ,
1167 ruvd_set_dtb set_dtb)
1168 {
1169 struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
1170 struct r600_common_context *rctx = (struct r600_common_context*)context;
1171 unsigned dpb_size;
1172 unsigned width = templ->width, height = templ->height;
1173 unsigned bs_buf_size;
1174 struct radeon_info info;
1175 struct ruvd_decoder *dec;
1176 int r, i;
1177
1178 ws->query_info(ws, &info);
1179
1180 switch(u_reduce_video_profile(templ->profile)) {
1181 case PIPE_VIDEO_FORMAT_MPEG12:
1182 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
1183 return vl_create_mpeg12_decoder(context, templ);
1184
1185 /* fall through */
1186 case PIPE_VIDEO_FORMAT_MPEG4:
1187 width = align(width, VL_MACROBLOCK_WIDTH);
1188 height = align(height, VL_MACROBLOCK_HEIGHT);
1189 break;
1190 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1191 width = align(width, VL_MACROBLOCK_WIDTH);
1192 height = align(height, VL_MACROBLOCK_HEIGHT);
1193 break;
1194
1195 default:
1196 break;
1197 }
1198
1199
1200 dec = CALLOC_STRUCT(ruvd_decoder);
1201
1202 if (!dec)
1203 return NULL;
1204
1205 if (info.drm_major < 3)
1206 dec->use_legacy = true;
1207
1208 dec->base = *templ;
1209 dec->base.context = context;
1210 dec->base.width = width;
1211 dec->base.height = height;
1212
1213 dec->base.destroy = ruvd_destroy;
1214 dec->base.begin_frame = ruvd_begin_frame;
1215 dec->base.decode_macroblock = ruvd_decode_macroblock;
1216 dec->base.decode_bitstream = ruvd_decode_bitstream;
1217 dec->base.end_frame = ruvd_end_frame;
1218 dec->base.flush = ruvd_flush;
1219
1220 dec->stream_type = profile2stream_type(dec, info.family);
1221 dec->set_dtb = set_dtb;
1222 dec->stream_handle = rvid_alloc_stream_handle();
1223 dec->screen = context->screen;
1224 dec->ws = ws;
1225 dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL);
1226 if (!dec->cs) {
1227 RVID_ERR("Can't get command submission context.\n");
1228 goto error;
1229 }
1230
1231 dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
1232 FB_BUFFER_SIZE;
1233 bs_buf_size = width * height * (512 / (16 * 16));
1234 for (i = 0; i < NUM_BUFFERS; ++i) {
1235 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
1236 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
1237 if (have_it(dec))
1238 msg_fb_it_size += IT_SCALING_TABLE_SIZE;
1239 if (!rvid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
1240 msg_fb_it_size, PIPE_USAGE_STAGING)) {
1241 RVID_ERR("Can't allocated message buffers.\n");
1242 goto error;
1243 }
1244
1245 if (!rvid_create_buffer(dec->screen, &dec->bs_buffers[i],
1246 bs_buf_size, PIPE_USAGE_STAGING)) {
1247 RVID_ERR("Can't allocated bitstream buffers.\n");
1248 goto error;
1249 }
1250
1251 rvid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
1252 rvid_clear_buffer(context, &dec->bs_buffers[i]);
1253 }
1254
1255 dpb_size = calc_dpb_size(dec);
1256
1257 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1258 RVID_ERR("Can't allocated dpb.\n");
1259 goto error;
1260 }
1261
1262 rvid_clear_buffer(context, &dec->dpb);
1263
1264 if (dec->stream_type == RUVD_CODEC_H264_PERF && info.family >= CHIP_POLARIS10) {
1265 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1266 if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1267 RVID_ERR("Can't allocated context buffer.\n");
1268 goto error;
1269 }
1270 rvid_clear_buffer(context, &dec->ctx);
1271 }
1272
1273 if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
1274 if (!rvid_create_buffer(dec->screen, &dec->sessionctx,
1275 UVD_SESSION_CONTEXT_SIZE,
1276 PIPE_USAGE_DEFAULT)) {
1277 RVID_ERR("Can't allocated session ctx.\n");
1278 goto error;
1279 }
1280 rvid_clear_buffer(context, &dec->sessionctx);
1281 }
1282
1283 map_msg_fb_it_buf(dec);
1284 dec->msg->size = sizeof(*dec->msg);
1285 dec->msg->msg_type = RUVD_MSG_CREATE;
1286 dec->msg->stream_handle = dec->stream_handle;
1287 dec->msg->body.create.stream_type = dec->stream_type;
1288 dec->msg->body.create.width_in_samples = dec->base.width;
1289 dec->msg->body.create.height_in_samples = dec->base.height;
1290 dec->msg->body.create.dpb_size = dpb_size;
1291 send_msg_buf(dec);
1292 r = flush(dec, 0);
1293 if (r)
1294 goto error;
1295
1296 next_buffer(dec);
1297
1298 return &dec->base;
1299
1300 error:
1301 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1302
1303 for (i = 0; i < NUM_BUFFERS; ++i) {
1304 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
1305 rvid_destroy_buffer(&dec->bs_buffers[i]);
1306 }
1307
1308 rvid_destroy_buffer(&dec->dpb);
1309 rvid_destroy_buffer(&dec->ctx);
1310 rvid_destroy_buffer(&dec->sessionctx);
1311
1312 FREE(dec);
1313
1314 return NULL;
1315 }
1316
1317 /* calculate top/bottom offset */
1318 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
1319 {
1320 return surface->level[0].offset +
1321 layer * surface->level[0].slice_size;
1322 }
1323
1324 /* hw encode the aspect of macro tiles */
1325 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1326 {
1327 switch (macro_tile_aspect) {
1328 default:
1329 case 1: macro_tile_aspect = 0; break;
1330 case 2: macro_tile_aspect = 1; break;
1331 case 4: macro_tile_aspect = 2; break;
1332 case 8: macro_tile_aspect = 3; break;
1333 }
1334 return macro_tile_aspect;
1335 }
1336
1337 /* hw encode the bank width and height */
1338 static unsigned bank_wh(unsigned bankwh)
1339 {
1340 switch (bankwh) {
1341 default:
1342 case 1: bankwh = 0; break;
1343 case 2: bankwh = 1; break;
1344 case 4: bankwh = 2; break;
1345 case 8: bankwh = 3; break;
1346 }
1347 return bankwh;
1348 }
1349
1350 /**
1351 * fill decoding target field from the luma and chroma surfaces
1352 */
1353 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
1354 struct radeon_surf *chroma)
1355 {
1356 msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
1357 switch (luma->level[0].mode) {
1358 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1359 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1360 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1361 break;
1362 case RADEON_SURF_MODE_1D:
1363 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1364 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1365 break;
1366 case RADEON_SURF_MODE_2D:
1367 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1368 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1369 break;
1370 default:
1371 assert(0);
1372 break;
1373 }
1374
1375 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
1376 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
1377 if (msg->body.decode.dt_field_mode) {
1378 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
1379 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
1380 } else {
1381 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1382 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1383 }
1384
1385 assert(luma->bankw == chroma->bankw);
1386 assert(luma->bankh == chroma->bankh);
1387 assert(luma->mtilea == chroma->mtilea);
1388
1389 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
1390 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
1391 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
1392 }