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[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_codec.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "r600_pipe_common.h"
49 #include "radeon_video.h"
50 #include "radeon_uvd.h"
51
52 #define NUM_BUFFERS 4
53
54 #define NUM_MPEG2_REFS 6
55 #define NUM_H264_REFS 17
56 #define NUM_VC1_REFS 5
57
58 #define FB_BUFFER_OFFSET 0x1000
59 #define FB_BUFFER_SIZE 2048
60
61 /* UVD decoder representation */
62 struct ruvd_decoder {
63 struct pipe_video_codec base;
64
65 ruvd_set_dtb set_dtb;
66
67 unsigned stream_handle;
68 unsigned frame_number;
69
70 struct pipe_screen *screen;
71 struct radeon_winsys* ws;
72 struct radeon_winsys_cs* cs;
73
74 unsigned cur_buffer;
75
76 struct rvid_buffer msg_fb_buffers[NUM_BUFFERS];
77 struct ruvd_msg *msg;
78 uint32_t *fb;
79
80 struct rvid_buffer bs_buffers[NUM_BUFFERS];
81 void* bs_ptr;
82 unsigned bs_size;
83
84 struct rvid_buffer dpb;
85 bool use_legacy;
86 };
87
88 /* flush IB to the hardware */
89 static void flush(struct ruvd_decoder *dec)
90 {
91 dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL, 0);
92 }
93
94 /* add a new set register command to the IB */
95 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
96 {
97 uint32_t *pm4 = dec->cs->buf;
98 pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0);
99 pm4[dec->cs->cdw++] = val;
100 }
101
102 /* send a command to the VCPU through the GPCOM registers */
103 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
104 struct radeon_winsys_cs_handle* cs_buf, uint32_t off,
105 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
106 {
107 int reloc_idx;
108
109 reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain,
110 RADEON_PRIO_MIN);
111 if (!dec->use_legacy) {
112 uint64_t addr;
113 addr = dec->ws->buffer_get_virtual_address(cs_buf);
114 addr = addr + off;
115 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
116 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
117 } else {
118 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
119 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
120 }
121 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
122 }
123
124 /* map the next available message/feedback buffer */
125 static void map_msg_fb_buf(struct ruvd_decoder *dec)
126 {
127 struct rvid_buffer* buf;
128 uint8_t *ptr;
129
130 /* grab the current message/feedback buffer */
131 buf = &dec->msg_fb_buffers[dec->cur_buffer];
132
133 /* and map it for CPU access */
134 ptr = dec->ws->buffer_map(buf->res->cs_buf, dec->cs, PIPE_TRANSFER_WRITE);
135
136 /* calc buffer offsets */
137 dec->msg = (struct ruvd_msg *)ptr;
138 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
139 }
140
141 /* unmap and send a message command to the VCPU */
142 static void send_msg_buf(struct ruvd_decoder *dec)
143 {
144 struct rvid_buffer* buf;
145
146 /* ignore the request if message/feedback buffer isn't mapped */
147 if (!dec->msg || !dec->fb)
148 return;
149
150 /* grab the current message buffer */
151 buf = &dec->msg_fb_buffers[dec->cur_buffer];
152
153 /* unmap the buffer */
154 dec->ws->buffer_unmap(buf->res->cs_buf);
155 dec->msg = NULL;
156 dec->fb = NULL;
157
158 /* and send it to the hardware */
159 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->cs_buf, 0,
160 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
161 }
162
163 /* cycle to the next set of buffers */
164 static void next_buffer(struct ruvd_decoder *dec)
165 {
166 ++dec->cur_buffer;
167 dec->cur_buffer %= NUM_BUFFERS;
168 }
169
170 /* convert the profile into something UVD understands */
171 static uint32_t profile2stream_type(enum pipe_video_profile profile)
172 {
173 switch (u_reduce_video_profile(profile)) {
174 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
175 return RUVD_CODEC_H264;
176
177 case PIPE_VIDEO_FORMAT_VC1:
178 return RUVD_CODEC_VC1;
179
180 case PIPE_VIDEO_FORMAT_MPEG12:
181 return RUVD_CODEC_MPEG2;
182
183 case PIPE_VIDEO_FORMAT_MPEG4:
184 return RUVD_CODEC_MPEG4;
185
186 default:
187 assert(0);
188 return 0;
189 }
190 }
191
192 /* calculate size of reference picture buffer */
193 static unsigned calc_dpb_size(const struct pipe_video_codec *templ)
194 {
195 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
196
197 // always align them to MB size for dpb calculation
198 unsigned width = align(templ->width, VL_MACROBLOCK_WIDTH);
199 unsigned height = align(templ->height, VL_MACROBLOCK_HEIGHT);
200
201 // always one more for currently decoded picture
202 unsigned max_references = templ->max_references + 1;
203
204 // aligned size of a single frame
205 image_size = width * height;
206 image_size += image_size / 2;
207 image_size = align(image_size, 1024);
208
209 // picture width & height in 16 pixel units
210 width_in_mb = width / VL_MACROBLOCK_WIDTH;
211 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
212
213 switch (u_reduce_video_profile(templ->profile)) {
214 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
215 // the firmware seems to allways assume a minimum of ref frames
216 max_references = MAX2(NUM_H264_REFS, max_references);
217
218 // reference picture buffer
219 dpb_size = image_size * max_references;
220
221 // macroblock context buffer
222 dpb_size += width_in_mb * height_in_mb * max_references * 192;
223
224 // IT surface buffer
225 dpb_size += width_in_mb * height_in_mb * 32;
226 break;
227
228 case PIPE_VIDEO_FORMAT_VC1:
229 // the firmware seems to allways assume a minimum of ref frames
230 max_references = MAX2(NUM_VC1_REFS, max_references);
231
232 // reference picture buffer
233 dpb_size = image_size * max_references;
234
235 // CONTEXT_BUFFER
236 dpb_size += width_in_mb * height_in_mb * 128;
237
238 // IT surface buffer
239 dpb_size += width_in_mb * 64;
240
241 // DB surface buffer
242 dpb_size += width_in_mb * 128;
243
244 // BP
245 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
246 break;
247
248 case PIPE_VIDEO_FORMAT_MPEG12:
249 // reference picture buffer, must be big enough for all frames
250 dpb_size = image_size * NUM_MPEG2_REFS;
251 break;
252
253 case PIPE_VIDEO_FORMAT_MPEG4:
254 // reference picture buffer
255 dpb_size = image_size * max_references;
256
257 // CM
258 dpb_size += width_in_mb * height_in_mb * 64;
259
260 // IT surface buffer
261 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
262 break;
263
264 default:
265 // something is missing here
266 assert(0);
267
268 // at least use a sane default value
269 dpb_size = 32 * 1024 * 1024;
270 break;
271 }
272 return dpb_size;
273 }
274
275 /* get h264 specific message bits */
276 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
277 {
278 struct ruvd_h264 result;
279
280 memset(&result, 0, sizeof(result));
281 switch (pic->base.profile) {
282 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
283 result.profile = RUVD_H264_PROFILE_BASELINE;
284 break;
285
286 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
287 result.profile = RUVD_H264_PROFILE_MAIN;
288 break;
289
290 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
291 result.profile = RUVD_H264_PROFILE_HIGH;
292 break;
293
294 default:
295 assert(0);
296 break;
297 }
298 if (((dec->base.width * dec->base.height) >> 8) <= 1620)
299 result.level = 30;
300 else
301 result.level = 41;
302
303 result.sps_info_flags = 0;
304 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
305 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
306 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
307 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
308
309 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
310 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
311 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
312 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
313 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
314
315 switch (dec->base.chroma_format) {
316 case PIPE_VIDEO_CHROMA_FORMAT_400:
317 result.chroma_format = 0;
318 break;
319 case PIPE_VIDEO_CHROMA_FORMAT_420:
320 result.chroma_format = 1;
321 break;
322 case PIPE_VIDEO_CHROMA_FORMAT_422:
323 result.chroma_format = 2;
324 break;
325 case PIPE_VIDEO_CHROMA_FORMAT_444:
326 result.chroma_format = 3;
327 break;
328 }
329
330 result.pps_info_flags = 0;
331 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
332 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
333 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
334 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
335 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
336 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
337 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
338 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
339
340 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
341 result.slice_group_map_type = pic->pps->slice_group_map_type;
342 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
343 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
344 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
345 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
346
347 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
348 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
349
350 result.num_ref_frames = pic->num_ref_frames;
351
352 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
353 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
354
355 result.frame_num = pic->frame_num;
356 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
357 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
358 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
359 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
360
361 result.decoded_pic_idx = pic->frame_num;
362
363 return result;
364 }
365
366 /* get vc1 specific message bits */
367 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
368 {
369 struct ruvd_vc1 result;
370
371 memset(&result, 0, sizeof(result));
372
373 switch(pic->base.profile) {
374 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
375 result.profile = RUVD_VC1_PROFILE_SIMPLE;
376 result.level = 1;
377 break;
378
379 case PIPE_VIDEO_PROFILE_VC1_MAIN:
380 result.profile = RUVD_VC1_PROFILE_MAIN;
381 result.level = 2;
382 break;
383
384 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
385 result.profile = RUVD_VC1_PROFILE_ADVANCED;
386 result.level = 4;
387 break;
388
389 default:
390 assert(0);
391 }
392
393 /* fields common for all profiles */
394 result.sps_info_flags |= pic->postprocflag << 7;
395 result.sps_info_flags |= pic->pulldown << 6;
396 result.sps_info_flags |= pic->interlace << 5;
397 result.sps_info_flags |= pic->tfcntrflag << 4;
398 result.sps_info_flags |= pic->finterpflag << 3;
399 result.sps_info_flags |= pic->psf << 1;
400
401 result.pps_info_flags |= pic->range_mapy_flag << 31;
402 result.pps_info_flags |= pic->range_mapy << 28;
403 result.pps_info_flags |= pic->range_mapuv_flag << 27;
404 result.pps_info_flags |= pic->range_mapuv << 24;
405 result.pps_info_flags |= pic->multires << 21;
406 result.pps_info_flags |= pic->maxbframes << 16;
407 result.pps_info_flags |= pic->overlap << 11;
408 result.pps_info_flags |= pic->quantizer << 9;
409 result.pps_info_flags |= pic->panscan_flag << 7;
410 result.pps_info_flags |= pic->refdist_flag << 6;
411 result.pps_info_flags |= pic->vstransform << 0;
412
413 /* some fields only apply to main/advanced profile */
414 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
415 result.pps_info_flags |= pic->syncmarker << 20;
416 result.pps_info_flags |= pic->rangered << 19;
417 result.pps_info_flags |= pic->loopfilter << 5;
418 result.pps_info_flags |= pic->fastuvmc << 4;
419 result.pps_info_flags |= pic->extended_mv << 3;
420 result.pps_info_flags |= pic->extended_dmv << 8;
421 result.pps_info_flags |= pic->dquant << 1;
422 }
423
424 result.chroma_format = 1;
425
426 #if 0
427 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
428 uint32_t slice_count
429 uint8_t picture_type
430 uint8_t frame_coding_mode
431 uint8_t deblockEnable
432 uint8_t pquant
433 #endif
434
435 return result;
436 }
437
438 /* extract the frame number from a referenced video buffer */
439 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
440 {
441 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
442 uint32_t max = MAX2(dec->frame_number, 1) - 1;
443 uintptr_t frame;
444
445 /* seems to be the most sane fallback */
446 if (!ref)
447 return max;
448
449 /* get the frame number from the associated data */
450 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
451
452 /* limit the frame number to a valid range */
453 return MAX2(MIN2(frame, max), min);
454 }
455
456 /* get mpeg2 specific msg bits */
457 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
458 struct pipe_mpeg12_picture_desc *pic)
459 {
460 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
461 struct ruvd_mpeg2 result;
462 unsigned i;
463
464 memset(&result, 0, sizeof(result));
465 result.decoded_pic_idx = dec->frame_number;
466 for (i = 0; i < 2; ++i)
467 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
468
469 result.load_intra_quantiser_matrix = 1;
470 result.load_nonintra_quantiser_matrix = 1;
471
472 for (i = 0; i < 64; ++i) {
473 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
474 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
475 }
476
477 result.profile_and_level_indication = 0;
478 result.chroma_format = 0x1;
479
480 result.picture_coding_type = pic->picture_coding_type;
481 result.f_code[0][0] = pic->f_code[0][0] + 1;
482 result.f_code[0][1] = pic->f_code[0][1] + 1;
483 result.f_code[1][0] = pic->f_code[1][0] + 1;
484 result.f_code[1][1] = pic->f_code[1][1] + 1;
485 result.intra_dc_precision = pic->intra_dc_precision;
486 result.pic_structure = pic->picture_structure;
487 result.top_field_first = pic->top_field_first;
488 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
489 result.concealment_motion_vectors = pic->concealment_motion_vectors;
490 result.q_scale_type = pic->q_scale_type;
491 result.intra_vlc_format = pic->intra_vlc_format;
492 result.alternate_scan = pic->alternate_scan;
493
494 return result;
495 }
496
497 /* get mpeg4 specific msg bits */
498 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
499 struct pipe_mpeg4_picture_desc *pic)
500 {
501 struct ruvd_mpeg4 result;
502 unsigned i;
503
504 memset(&result, 0, sizeof(result));
505 result.decoded_pic_idx = dec->frame_number;
506 for (i = 0; i < 2; ++i)
507 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
508
509 result.variant_type = 0;
510 result.profile_and_level_indication = 0xF0; // ASP Level0
511
512 result.video_object_layer_verid = 0x5; // advanced simple
513 result.video_object_layer_shape = 0x0; // rectangular
514
515 result.video_object_layer_width = dec->base.width;
516 result.video_object_layer_height = dec->base.height;
517
518 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
519
520 result.flags |= pic->short_video_header << 0;
521 //result.flags |= obmc_disable << 1;
522 result.flags |= pic->interlaced << 2;
523 result.flags |= 1 << 3; // load_intra_quant_mat
524 result.flags |= 1 << 4; // load_nonintra_quant_mat
525 result.flags |= pic->quarter_sample << 5;
526 result.flags |= 1 << 6; // complexity_estimation_disable
527 result.flags |= pic->resync_marker_disable << 7;
528 //result.flags |= data_partitioned << 8;
529 //result.flags |= reversible_vlc << 9;
530 result.flags |= 0 << 10; // newpred_enable
531 result.flags |= 0 << 11; // reduced_resolution_vop_enable
532 //result.flags |= scalability << 12;
533 //result.flags |= is_object_layer_identifier << 13;
534 //result.flags |= fixed_vop_rate << 14;
535 //result.flags |= newpred_segment_type << 15;
536
537 result.quant_type = pic->quant_type;
538
539 for (i = 0; i < 64; ++i) {
540 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
541 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
542 }
543
544 /*
545 int32_t trd [2]
546 int32_t trb [2]
547 uint8_t vop_coding_type
548 uint8_t vop_fcode_forward
549 uint8_t vop_fcode_backward
550 uint8_t rounding_control
551 uint8_t alternate_vertical_scan_flag
552 uint8_t top_field_first
553 */
554
555 return result;
556 }
557
558 /**
559 * destroy this video decoder
560 */
561 static void ruvd_destroy(struct pipe_video_codec *decoder)
562 {
563 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
564 unsigned i;
565
566 assert(decoder);
567
568 map_msg_fb_buf(dec);
569 memset(dec->msg, 0, sizeof(*dec->msg));
570 dec->msg->size = sizeof(*dec->msg);
571 dec->msg->msg_type = RUVD_MSG_DESTROY;
572 dec->msg->stream_handle = dec->stream_handle;
573 send_msg_buf(dec);
574
575 flush(dec);
576
577 dec->ws->cs_destroy(dec->cs);
578
579 for (i = 0; i < NUM_BUFFERS; ++i) {
580 rvid_destroy_buffer(&dec->msg_fb_buffers[i]);
581 rvid_destroy_buffer(&dec->bs_buffers[i]);
582 }
583
584 rvid_destroy_buffer(&dec->dpb);
585
586 FREE(dec);
587 }
588
589 /* free associated data in the video buffer callback */
590 static void ruvd_destroy_associated_data(void *data)
591 {
592 /* NOOP, since we only use an intptr */
593 }
594
595 /**
596 * start decoding of a new frame
597 */
598 static void ruvd_begin_frame(struct pipe_video_codec *decoder,
599 struct pipe_video_buffer *target,
600 struct pipe_picture_desc *picture)
601 {
602 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
603 uintptr_t frame;
604
605 assert(decoder);
606
607 frame = ++dec->frame_number;
608 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
609 &ruvd_destroy_associated_data);
610
611 dec->bs_size = 0;
612 dec->bs_ptr = dec->ws->buffer_map(
613 dec->bs_buffers[dec->cur_buffer].res->cs_buf,
614 dec->cs, PIPE_TRANSFER_WRITE);
615 }
616
617 /**
618 * decode a macroblock
619 */
620 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
621 struct pipe_video_buffer *target,
622 struct pipe_picture_desc *picture,
623 const struct pipe_macroblock *macroblocks,
624 unsigned num_macroblocks)
625 {
626 /* not supported (yet) */
627 assert(0);
628 }
629
630 /**
631 * decode a bitstream
632 */
633 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
634 struct pipe_video_buffer *target,
635 struct pipe_picture_desc *picture,
636 unsigned num_buffers,
637 const void * const *buffers,
638 const unsigned *sizes)
639 {
640 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
641 unsigned i;
642
643 assert(decoder);
644
645 if (!dec->bs_ptr)
646 return;
647
648 for (i = 0; i < num_buffers; ++i) {
649 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
650 unsigned new_size = dec->bs_size + sizes[i];
651
652 if (new_size > buf->res->buf->size) {
653 dec->ws->buffer_unmap(buf->res->cs_buf);
654 if (!rvid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
655 RVID_ERR("Can't resize bitstream buffer!");
656 return;
657 }
658
659 dec->bs_ptr = dec->ws->buffer_map(buf->res->cs_buf, dec->cs,
660 PIPE_TRANSFER_WRITE);
661 if (!dec->bs_ptr)
662 return;
663
664 dec->bs_ptr += dec->bs_size;
665 }
666
667 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
668 dec->bs_size += sizes[i];
669 dec->bs_ptr += sizes[i];
670 }
671 }
672
673 /**
674 * end decoding of the current frame
675 */
676 static void ruvd_end_frame(struct pipe_video_codec *decoder,
677 struct pipe_video_buffer *target,
678 struct pipe_picture_desc *picture)
679 {
680 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
681 struct radeon_winsys_cs_handle *dt;
682 struct rvid_buffer *msg_fb_buf, *bs_buf;
683 unsigned bs_size;
684
685 assert(decoder);
686
687 if (!dec->bs_ptr)
688 return;
689
690 msg_fb_buf = &dec->msg_fb_buffers[dec->cur_buffer];
691 bs_buf = &dec->bs_buffers[dec->cur_buffer];
692
693 bs_size = align(dec->bs_size, 128);
694 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
695 dec->ws->buffer_unmap(bs_buf->res->cs_buf);
696
697 map_msg_fb_buf(dec);
698 dec->msg->size = sizeof(*dec->msg);
699 dec->msg->msg_type = RUVD_MSG_DECODE;
700 dec->msg->stream_handle = dec->stream_handle;
701 dec->msg->status_report_feedback_number = dec->frame_number;
702
703 dec->msg->body.decode.stream_type = profile2stream_type(dec->base.profile);
704 dec->msg->body.decode.decode_flags = 0x1;
705 dec->msg->body.decode.width_in_samples = dec->base.width;
706 dec->msg->body.decode.height_in_samples = dec->base.height;
707
708 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
709 dec->msg->body.decode.bsd_size = bs_size;
710
711 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
712
713 switch (u_reduce_video_profile(picture->profile)) {
714 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
715 dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
716 break;
717
718 case PIPE_VIDEO_FORMAT_VC1:
719 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
720 break;
721
722 case PIPE_VIDEO_FORMAT_MPEG12:
723 dec->msg->body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
724 break;
725
726 case PIPE_VIDEO_FORMAT_MPEG4:
727 dec->msg->body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
728 break;
729
730 default:
731 assert(0);
732 return;
733 }
734
735 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
736 dec->msg->body.decode.extension_support = 0x1;
737
738 /* set at least the feedback buffer size */
739 dec->fb[0] = FB_BUFFER_SIZE;
740
741 send_msg_buf(dec);
742
743 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->cs_buf, 0,
744 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
745 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->cs_buf,
746 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
747 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
748 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
749 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf->res->cs_buf,
750 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
751 set_reg(dec, RUVD_ENGINE_CNTL, 1);
752
753 flush(dec);
754 next_buffer(dec);
755 }
756
757 /**
758 * flush any outstanding command buffers to the hardware
759 */
760 static void ruvd_flush(struct pipe_video_codec *decoder)
761 {
762 }
763
764 /**
765 * create and UVD decoder
766 */
767 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
768 const struct pipe_video_codec *templ,
769 ruvd_set_dtb set_dtb)
770 {
771 struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
772 unsigned dpb_size = calc_dpb_size(templ);
773 struct r600_common_context *rctx = (struct r600_common_context*)context;
774 unsigned width = templ->width, height = templ->height;
775 unsigned bs_buf_size;
776 struct radeon_info info;
777 struct ruvd_decoder *dec;
778 int i;
779
780 ws->query_info(ws, &info);
781
782 switch(u_reduce_video_profile(templ->profile)) {
783 case PIPE_VIDEO_FORMAT_MPEG12:
784 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
785 return vl_create_mpeg12_decoder(context, templ);
786
787 /* fall through */
788 case PIPE_VIDEO_FORMAT_MPEG4:
789 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
790 width = align(width, VL_MACROBLOCK_WIDTH);
791 height = align(height, VL_MACROBLOCK_HEIGHT);
792 break;
793
794 default:
795 break;
796 }
797
798
799 dec = CALLOC_STRUCT(ruvd_decoder);
800
801 if (!dec)
802 return NULL;
803
804 if (info.drm_major < 3)
805 dec->use_legacy = TRUE;
806
807 dec->base = *templ;
808 dec->base.context = context;
809 dec->base.width = width;
810 dec->base.height = height;
811
812 dec->base.destroy = ruvd_destroy;
813 dec->base.begin_frame = ruvd_begin_frame;
814 dec->base.decode_macroblock = ruvd_decode_macroblock;
815 dec->base.decode_bitstream = ruvd_decode_bitstream;
816 dec->base.end_frame = ruvd_end_frame;
817 dec->base.flush = ruvd_flush;
818
819 dec->set_dtb = set_dtb;
820 dec->stream_handle = rvid_alloc_stream_handle();
821 dec->screen = context->screen;
822 dec->ws = ws;
823 dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL, NULL);
824 if (!dec->cs) {
825 RVID_ERR("Can't get command submission context.\n");
826 goto error;
827 }
828
829 bs_buf_size = width * height * 512 / (16 * 16);
830 for (i = 0; i < NUM_BUFFERS; ++i) {
831 unsigned msg_fb_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
832 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
833 if (!rvid_create_buffer(dec->screen, &dec->msg_fb_buffers[i],
834 msg_fb_size, PIPE_USAGE_STAGING)) {
835 RVID_ERR("Can't allocated message buffers.\n");
836 goto error;
837 }
838
839 if (!rvid_create_buffer(dec->screen, &dec->bs_buffers[i],
840 bs_buf_size, PIPE_USAGE_STAGING)) {
841 RVID_ERR("Can't allocated bitstream buffers.\n");
842 goto error;
843 }
844
845 rvid_clear_buffer(context, &dec->msg_fb_buffers[i]);
846 rvid_clear_buffer(context, &dec->bs_buffers[i]);
847 }
848
849 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
850 RVID_ERR("Can't allocated dpb.\n");
851 goto error;
852 }
853
854 rvid_clear_buffer(context, &dec->dpb);
855
856 map_msg_fb_buf(dec);
857 dec->msg->size = sizeof(*dec->msg);
858 dec->msg->msg_type = RUVD_MSG_CREATE;
859 dec->msg->stream_handle = dec->stream_handle;
860 dec->msg->body.create.stream_type = profile2stream_type(dec->base.profile);
861 dec->msg->body.create.width_in_samples = dec->base.width;
862 dec->msg->body.create.height_in_samples = dec->base.height;
863 dec->msg->body.create.dpb_size = dec->dpb.res->buf->size;
864 send_msg_buf(dec);
865 flush(dec);
866 next_buffer(dec);
867
868 return &dec->base;
869
870 error:
871 if (dec->cs) dec->ws->cs_destroy(dec->cs);
872
873 for (i = 0; i < NUM_BUFFERS; ++i) {
874 rvid_destroy_buffer(&dec->msg_fb_buffers[i]);
875 rvid_destroy_buffer(&dec->bs_buffers[i]);
876 }
877
878 rvid_destroy_buffer(&dec->dpb);
879
880 FREE(dec);
881
882 return NULL;
883 }
884
885 /* calculate top/bottom offset */
886 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
887 {
888 return surface->level[0].offset +
889 layer * surface->level[0].slice_size;
890 }
891
892 /* hw encode the aspect of macro tiles */
893 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
894 {
895 switch (macro_tile_aspect) {
896 default:
897 case 1: macro_tile_aspect = 0; break;
898 case 2: macro_tile_aspect = 1; break;
899 case 4: macro_tile_aspect = 2; break;
900 case 8: macro_tile_aspect = 3; break;
901 }
902 return macro_tile_aspect;
903 }
904
905 /* hw encode the bank width and height */
906 static unsigned bank_wh(unsigned bankwh)
907 {
908 switch (bankwh) {
909 default:
910 case 1: bankwh = 0; break;
911 case 2: bankwh = 1; break;
912 case 4: bankwh = 2; break;
913 case 8: bankwh = 3; break;
914 }
915 return bankwh;
916 }
917
918 /**
919 * fill decoding target field from the luma and chroma surfaces
920 */
921 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
922 struct radeon_surf *chroma)
923 {
924 msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
925 switch (luma->level[0].mode) {
926 case RADEON_SURF_MODE_LINEAR_ALIGNED:
927 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
928 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
929 break;
930 case RADEON_SURF_MODE_1D:
931 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
932 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
933 break;
934 case RADEON_SURF_MODE_2D:
935 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
936 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
937 break;
938 default:
939 assert(0);
940 break;
941 }
942
943 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
944 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
945 if (msg->body.decode.dt_field_mode) {
946 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
947 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
948 } else {
949 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
950 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
951 }
952
953 assert(luma->bankw == chroma->bankw);
954 assert(luma->bankh == chroma->bankh);
955 assert(luma->mtilea == chroma->mtilea);
956
957 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
958 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
959 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
960 }