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radeon/uvd: fix quant scan order for mpeg2
[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_decoder.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "../../winsys/radeon/drm/radeon_winsys.h"
49 #include "radeon_uvd.h"
50
51 #define RUVD_ERR(fmt, args...) \
52 fprintf(stderr, "EE %s:%d %s UVD - "fmt, __FILE__, __LINE__, __func__, ##args)
53
54 #define NUM_BUFFERS 4
55
56 #define NUM_MPEG2_REFS 6
57 #define NUM_H264_REFS 17
58
59 /* UVD buffer representation */
60 struct ruvd_buffer
61 {
62 struct pb_buffer* buf;
63 struct radeon_winsys_cs_handle* cs_handle;
64 };
65
66 /* UVD decoder representation */
67 struct ruvd_decoder {
68 struct pipe_video_decoder base;
69
70 ruvd_set_dtb set_dtb;
71
72 unsigned stream_handle;
73 unsigned frame_number;
74
75 struct radeon_winsys* ws;
76 struct radeon_winsys_cs* cs;
77
78 unsigned cur_buffer;
79
80 struct ruvd_buffer msg_fb_buffers[NUM_BUFFERS];
81 struct ruvd_buffer bs_buffers[NUM_BUFFERS];
82 void* bs_ptr;
83 unsigned bs_size;
84
85 struct ruvd_buffer dpb;
86 };
87
88 /* generate an UVD stream handle */
89 static unsigned alloc_stream_handle()
90 {
91 static unsigned counter = 0;
92 unsigned stream_handle = 0;
93 unsigned pid = getpid();
94 int i;
95
96 for (i = 0; i < 32; ++i)
97 stream_handle |= ((pid >> i) & 1) << (31 - i);
98
99 stream_handle ^= ++counter;
100 return stream_handle;
101 }
102
103 /* flush IB to the hardware */
104 static void flush(struct ruvd_decoder *dec)
105 {
106 uint32_t *pm4 = dec->cs->buf;
107
108 // align IB
109 while(dec->cs->cdw % 16)
110 pm4[dec->cs->cdw++] = RUVD_PKT2();
111
112 dec->ws->cs_flush(dec->cs, 0, 0);
113 }
114
115 /* add a new set register command to the IB */
116 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
117 {
118 uint32_t *pm4 = dec->cs->buf;
119 pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0);
120 pm4[dec->cs->cdw++] = val;
121 }
122
123 /* send a command to the VCPU through the GPCOM registers */
124 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
125 struct radeon_winsys_cs_handle* cs_buf, uint32_t off,
126 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
127 {
128 int reloc_idx;
129
130 reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain);
131 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
132 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
133 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
134 }
135
136 /* send a message command to the VCPU */
137 static void send_msg(struct ruvd_decoder *dec, struct ruvd_msg *msg)
138 {
139 struct ruvd_buffer* buf;
140 void *ptr;
141
142 /* grap a message buffer */
143 buf = &dec->msg_fb_buffers[dec->cur_buffer];
144
145 /* copy the message into it */
146 ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE);
147 if (!ptr)
148 return;
149
150 memcpy(ptr, msg, sizeof(*msg));
151 memset(ptr + sizeof(*msg), 0, buf->buf->size - sizeof(*msg));
152 dec->ws->buffer_unmap(buf->cs_handle);
153
154 /* and send it to the hardware */
155 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->cs_handle, 0,
156 RADEON_USAGE_READ, RADEON_DOMAIN_VRAM);
157 }
158
159 /* create a buffer in the winsys */
160 static bool create_buffer(struct ruvd_decoder *dec,
161 struct ruvd_buffer *buffer,
162 unsigned size)
163 {
164 buffer->buf = dec->ws->buffer_create(dec->ws, size, 4096, false,
165 RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM);
166 if (!buffer->buf)
167 return false;
168
169 buffer->cs_handle = dec->ws->buffer_get_cs_handle(buffer->buf);
170 if (!buffer->cs_handle)
171 return false;
172
173 return true;
174 }
175
176 /* destroy a buffer */
177 static void destroy_buffer(struct ruvd_buffer *buffer)
178 {
179 pb_reference(&buffer->buf, NULL);
180 buffer->cs_handle = NULL;
181 }
182
183 /* reallocate a buffer, preserving its content */
184 static bool resize_buffer(struct ruvd_decoder *dec,
185 struct ruvd_buffer *new_buf,
186 unsigned new_size)
187 {
188 unsigned bytes = MIN2(new_buf->buf->size, new_size);
189 struct ruvd_buffer old_buf = *new_buf;
190 void *src = NULL, *dst = NULL;
191
192 if (!create_buffer(dec, new_buf, new_size))
193 goto error;
194
195 src = dec->ws->buffer_map(old_buf.cs_handle, dec->cs, PIPE_TRANSFER_READ);
196 if (!src)
197 goto error;
198
199 dst = dec->ws->buffer_map(new_buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE);
200 if (!dst)
201 goto error;
202
203 memcpy(dst, src, bytes);
204 if (new_size > bytes) {
205 new_size -= bytes;
206 dst += bytes;
207 memset(dst, 0, new_size);
208 }
209 dec->ws->buffer_unmap(new_buf->cs_handle);
210 dec->ws->buffer_unmap(old_buf.cs_handle);
211 destroy_buffer(&old_buf);
212 return true;
213
214 error:
215 if (src) dec->ws->buffer_unmap(old_buf.cs_handle);
216 destroy_buffer(new_buf);
217 *new_buf = old_buf;
218 return false;
219 }
220
221 /* clear the buffer with zeros */
222 static void clear_buffer(struct ruvd_decoder *dec,
223 struct ruvd_buffer* buffer)
224 {
225 //TODO: let the GPU do the job
226 void *ptr = dec->ws->buffer_map(buffer->cs_handle, dec->cs,
227 PIPE_TRANSFER_WRITE);
228 if (!ptr)
229 return;
230
231 memset(ptr, 0, buffer->buf->size);
232 dec->ws->buffer_unmap(buffer->cs_handle);
233 }
234
235 /* cycle to the next set of buffers */
236 static void next_buffer(struct ruvd_decoder *dec)
237 {
238 ++dec->cur_buffer;
239 dec->cur_buffer %= NUM_BUFFERS;
240 }
241
242 /* convert the profile into something UVD understands */
243 static uint32_t profile2stream_type(enum pipe_video_profile profile)
244 {
245 switch (u_reduce_video_profile(profile)) {
246 case PIPE_VIDEO_CODEC_MPEG4_AVC:
247 return RUVD_CODEC_H264;
248
249 case PIPE_VIDEO_CODEC_VC1:
250 return RUVD_CODEC_VC1;
251
252 case PIPE_VIDEO_CODEC_MPEG12:
253 return RUVD_CODEC_MPEG2;
254
255 case PIPE_VIDEO_CODEC_MPEG4:
256 return RUVD_CODEC_MPEG4;
257
258 default:
259 assert(0);
260 return 0;
261 }
262 }
263
264 /* calculate size of reference picture buffer */
265 static unsigned calc_dpb_size(enum pipe_video_profile profile,
266 unsigned width, unsigned height,
267 unsigned max_references)
268 {
269 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
270
271 // always align them to MB size for dpb calculation
272 width = align(width, VL_MACROBLOCK_WIDTH);
273 height = align(height, VL_MACROBLOCK_HEIGHT);
274
275 // always one more for currently decoded picture
276 max_references += 1;
277
278 // aligned size of a single frame
279 image_size = width * height;
280 image_size += image_size / 2;
281 image_size = align(image_size, 1024);
282
283 // picture width & height in 16 pixel units
284 width_in_mb = width / VL_MACROBLOCK_WIDTH;
285 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
286
287 switch (u_reduce_video_profile(profile)) {
288 case PIPE_VIDEO_CODEC_MPEG4_AVC:
289 // the firmware seems to allways assume a minimum of ref frames
290 max_references = MAX2(NUM_H264_REFS, max_references);
291
292 // reference picture buffer
293 dpb_size = image_size * max_references;
294
295 // macroblock context buffer
296 dpb_size += width_in_mb * height_in_mb * max_references * 192;
297
298 // IT surface buffer
299 dpb_size += width_in_mb * height_in_mb * 32;
300 break;
301
302 case PIPE_VIDEO_CODEC_VC1:
303 // reference picture buffer
304 dpb_size = image_size * max_references;
305
306 // CONTEXT_BUFFER
307 dpb_size += width_in_mb * height_in_mb * 128;
308
309 // IT surface buffer
310 dpb_size += width_in_mb * 64;
311
312 // DB surface buffer
313 dpb_size += width_in_mb * 128;
314
315 // BP
316 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
317 break;
318
319 case PIPE_VIDEO_CODEC_MPEG12:
320 // reference picture buffer, must be big enough for all frames
321 dpb_size = image_size * NUM_MPEG2_REFS;
322 break;
323
324 case PIPE_VIDEO_CODEC_MPEG4:
325 // reference picture buffer
326 dpb_size = image_size * max_references;
327
328 // CM
329 dpb_size += width_in_mb * height_in_mb * 64;
330
331 // IT surface buffer
332 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
333 break;
334
335 default:
336 // something is missing here
337 assert(0);
338
339 // at least use a sane default value
340 dpb_size = 32 * 1024 * 1024;
341 break;
342 }
343 return dpb_size;
344 }
345
346 /* get h264 specific message bits */
347 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
348 {
349 struct ruvd_h264 result;
350
351 memset(&result, 0, sizeof(result));
352 switch (pic->base.profile) {
353 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
354 result.profile = RUVD_H264_PROFILE_BASELINE;
355 break;
356
357 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
358 result.profile = RUVD_H264_PROFILE_MAIN;
359 break;
360
361 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
362 result.profile = RUVD_H264_PROFILE_HIGH;
363 break;
364
365 default:
366 assert(0);
367 break;
368 }
369 if (((dec->base.width * dec->base.height) >> 8) <= 1620)
370 result.level = 30;
371 else
372 result.level = 41;
373
374 result.sps_info_flags = 0;
375 result.sps_info_flags |= pic->direct_8x8_inference_flag << 0;
376 result.sps_info_flags |= pic->mb_adaptive_frame_field_flag << 1;
377 result.sps_info_flags |= pic->frame_mbs_only_flag << 2;
378 result.sps_info_flags |= pic->delta_pic_order_always_zero_flag << 3;
379
380 result.pps_info_flags = 0;
381 result.pps_info_flags |= pic->transform_8x8_mode_flag << 0;
382 result.pps_info_flags |= pic->redundant_pic_cnt_present_flag << 1;
383 result.pps_info_flags |= pic->constrained_intra_pred_flag << 2;
384 result.pps_info_flags |= pic->deblocking_filter_control_present_flag << 3;
385 result.pps_info_flags |= pic->weighted_bipred_idc << 4;
386 result.pps_info_flags |= pic->weighted_pred_flag << 6;
387 result.pps_info_flags |= pic->pic_order_present_flag << 7;
388 result.pps_info_flags |= pic->entropy_coding_mode_flag << 8;
389
390 result.chroma_format = 0x1;
391 result.bit_depth_luma_minus8 = 0;
392 result.bit_depth_chroma_minus8 = 0;
393
394 result.log2_max_frame_num_minus4 = pic->log2_max_frame_num_minus4;
395 result.pic_order_cnt_type = pic->pic_order_cnt_type;
396 result.log2_max_pic_order_cnt_lsb_minus4 = pic->log2_max_pic_order_cnt_lsb_minus4;
397 result.num_ref_frames = pic->num_ref_frames;
398 result.pic_init_qp_minus26 = pic->pic_init_qp_minus26;
399 result.chroma_qp_index_offset = pic->chroma_qp_index_offset;
400 result.second_chroma_qp_index_offset = pic->second_chroma_qp_index_offset;
401
402 result.num_slice_groups_minus1 = 0;
403 result.slice_group_map_type = 0;
404
405 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
406 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
407
408 result.slice_group_change_rate_minus1 = 0;
409
410 memcpy(result.scaling_list_4x4, pic->scaling_lists_4x4, 6*64);
411 memcpy(result.scaling_list_8x8, pic->scaling_lists_8x8, 2*64);
412
413 result.frame_num = pic->frame_num;
414 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
415 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
416 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
417 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
418
419 result.decoded_pic_idx = pic->frame_num;
420
421 return result;
422 }
423
424 /* get vc1 specific message bits */
425 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
426 {
427 struct ruvd_vc1 result;
428
429 memset(&result, 0, sizeof(result));
430 switch(pic->base.profile) {
431 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
432 result.profile = RUVD_VC1_PROFILE_SIMPLE;
433 break;
434
435 case PIPE_VIDEO_PROFILE_VC1_MAIN:
436 result.profile = RUVD_VC1_PROFILE_MAIN;
437 break;
438
439 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
440 result.profile = RUVD_VC1_PROFILE_ADVANCED;
441 break;
442 default:
443 assert(0);
444 }
445
446 if (pic->base.profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) {
447 result.level = 0;
448
449 result.sps_info_flags |= pic->postprocflag << 7;
450 result.sps_info_flags |= pic->pulldown << 6;
451 result.sps_info_flags |= pic->interlace << 5;
452 result.sps_info_flags |= pic->tfcntrflag << 4;
453 result.sps_info_flags |= pic->psf << 1;
454
455 result.pps_info_flags |= pic->panscan_flag << 7;
456 result.pps_info_flags |= pic->refdist_flag << 6;
457 result.pps_info_flags |= pic->extended_dmv << 8;
458 result.pps_info_flags |= pic->range_mapy_flag << 31;
459 result.pps_info_flags |= pic->range_mapy << 28;
460 result.pps_info_flags |= pic->range_mapuv_flag << 27;
461 result.pps_info_flags |= pic->range_mapuv << 24;
462
463 } else {
464 result.level = 0;
465 result.pps_info_flags |= pic->multires << 21;
466 result.pps_info_flags |= pic->syncmarker << 20;
467 result.pps_info_flags |= pic->rangered << 19;
468 result.pps_info_flags |= pic->maxbframes << 16;
469 }
470
471 result.sps_info_flags |= pic->finterpflag << 3;
472 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
473
474 result.pps_info_flags |= pic->loopfilter << 5;
475 result.pps_info_flags |= pic->fastuvmc << 4;
476 result.pps_info_flags |= pic->extended_mv << 3;
477 result.pps_info_flags |= pic->dquant << 1;
478 result.pps_info_flags |= pic->vstransform << 0;
479 result.pps_info_flags |= pic->overlap << 11;
480 result.pps_info_flags |= pic->quantizer << 9;
481
482
483 #if 0
484 uint32_t slice_count
485 uint8_t picture_type
486 uint8_t frame_coding_mode
487 uint8_t deblockEnable
488 uint8_t pquant
489 #endif
490
491 result.chroma_format = 1;
492 return result;
493 }
494
495 /* extract the frame number from a referenced video buffer */
496 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
497 {
498 uint32_t min = dec->frame_number - NUM_MPEG2_REFS;
499 uint32_t max = dec->frame_number - 1;
500 uintptr_t frame;
501
502 /* seems to be the most sane fallback */
503 if (!ref)
504 return max;
505
506 /* get the frame number from the associated data */
507 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
508
509 /* limit the frame number to a valid range */
510 return MAX2(MIN2(frame, max), min);
511 }
512
513 /* get mpeg2 specific msg bits */
514 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
515 struct pipe_mpeg12_picture_desc *pic)
516 {
517 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
518 struct ruvd_mpeg2 result;
519 unsigned i;
520
521 memset(&result, 0, sizeof(result));
522 result.decoded_pic_idx = dec->frame_number;
523 for (i = 0; i < 2; ++i)
524 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
525
526 result.load_intra_quantiser_matrix = 1;
527 result.load_nonintra_quantiser_matrix = 1;
528
529 for (i = 0; i < 64; ++i) {
530 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
531 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
532 }
533
534 result.profile_and_level_indication = 0;
535 result.chroma_format = 0x1;
536
537 result.picture_coding_type = pic->picture_coding_type;
538 result.f_code[0][0] = pic->f_code[0][0] + 1;
539 result.f_code[0][1] = pic->f_code[0][1] + 1;
540 result.f_code[1][0] = pic->f_code[1][0] + 1;
541 result.f_code[1][1] = pic->f_code[1][1] + 1;
542 result.intra_dc_precision = pic->intra_dc_precision;
543 result.pic_structure = pic->picture_structure;
544 result.top_field_first = pic->top_field_first;
545 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
546 result.concealment_motion_vectors = pic->concealment_motion_vectors;
547 result.q_scale_type = pic->q_scale_type;
548 result.intra_vlc_format = pic->intra_vlc_format;
549 result.alternate_scan = pic->alternate_scan;
550
551 return result;
552 }
553
554 /* get mpeg4 specific msg bits */
555 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
556 struct pipe_mpeg4_picture_desc *pic)
557 {
558 struct ruvd_mpeg4 result;
559 unsigned i;
560 memset(&result, 0, sizeof(result));
561 result.decoded_pic_idx = dec->frame_number;
562 for (i = 0; i < 2; ++i)
563 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
564
565 result.video_object_layer_width = dec->base.width;
566 result.video_object_layer_height = dec->base.height;
567
568 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
569 result.quant_type = pic->quant_type;
570
571 result.flags |= pic->short_video_header << 0;
572 //result.flags |= obmc_disable << 1;
573 result.flags |= pic->interlaced << 2;
574 result.flags |= 1 << 3; // load_intra_quant_mat
575 result.flags |= 1 << 4; // load_nonintra_quant_mat
576 result.flags |= pic->quarter_sample << 5;
577 //result.flags |= complexity_estimation_disable << 6
578 result.flags |= pic->resync_marker_disable << 7;
579 //result.flags |= data_partitioned << 8;
580 //result.flags |= reversible_vlc << 9;
581 //result.flags |= newpred_enable << 10;
582 //result.flags |= reduced_resolution_vop_enable << 11;
583 //result.flags |= scalability << 12;
584 //result.flags |= is_object_layer_identifier << 13;
585 //result.flags |= fixed_vop_rate << 14;
586 //result.flags |= newpred_segment_type << 15;
587
588 memcpy(&result.intra_quant_mat, pic->intra_matrix, 64);
589 memcpy(&result.nonintra_quant_mat, pic->non_intra_matrix, 64);
590
591 /*
592 int32_t trd [2]
593 int32_t trb [2]
594 uint8_t vop_coding_type
595 uint8_t vop_fcode_forward
596 uint8_t vop_fcode_backward
597 uint8_t rounding_control
598 uint8_t alternate_vertical_scan_flag
599 uint8_t top_field_first
600 */
601
602 return result;
603 }
604
605 /**
606 * destroy this video decoder
607 */
608 static void ruvd_destroy(struct pipe_video_decoder *decoder)
609 {
610 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
611 struct ruvd_msg msg;
612 unsigned i;
613
614 assert(decoder);
615
616 memset(&msg, 0, sizeof(msg));
617 msg.size = sizeof(msg);
618 msg.msg_type = RUVD_MSG_DESTROY;
619 msg.stream_handle = dec->stream_handle;
620 send_msg(dec, &msg);
621
622 flush(dec);
623
624 dec->ws->cs_destroy(dec->cs);
625
626 for (i = 0; i < NUM_BUFFERS; ++i) {
627 destroy_buffer(&dec->msg_fb_buffers[i]);
628 destroy_buffer(&dec->bs_buffers[i]);
629 }
630
631 destroy_buffer(&dec->dpb);
632
633 FREE(dec);
634 }
635
636 /* free associated data in the video buffer callback */
637 static void ruvd_destroy_associated_data(void *data)
638 {
639 /* NOOP, since we only use an intptr */
640 }
641
642 /**
643 * start decoding of a new frame
644 */
645 static void ruvd_begin_frame(struct pipe_video_decoder *decoder,
646 struct pipe_video_buffer *target,
647 struct pipe_picture_desc *picture)
648 {
649 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
650 uintptr_t frame;
651
652 assert(decoder);
653
654 frame = ++dec->frame_number;
655 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
656 &ruvd_destroy_associated_data);
657
658 dec->bs_size = 0;
659 dec->bs_ptr = dec->ws->buffer_map(
660 dec->bs_buffers[dec->cur_buffer].cs_handle,
661 dec->cs, PIPE_TRANSFER_WRITE);
662 }
663
664 /**
665 * decode a macroblock
666 */
667 static void ruvd_decode_macroblock(struct pipe_video_decoder *decoder,
668 struct pipe_video_buffer *target,
669 struct pipe_picture_desc *picture,
670 const struct pipe_macroblock *macroblocks,
671 unsigned num_macroblocks)
672 {
673 /* not supported (yet) */
674 assert(0);
675 }
676
677 /**
678 * decode a bitstream
679 */
680 static void ruvd_decode_bitstream(struct pipe_video_decoder *decoder,
681 struct pipe_video_buffer *target,
682 struct pipe_picture_desc *picture,
683 unsigned num_buffers,
684 const void * const *buffers,
685 const unsigned *sizes)
686 {
687 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
688 unsigned i;
689
690 assert(decoder);
691
692 if (!dec->bs_ptr)
693 return;
694
695 for (i = 0; i < num_buffers; ++i) {
696 struct ruvd_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
697 unsigned new_size = dec->bs_size + sizes[i];
698
699 if (new_size > buf->buf->size) {
700 dec->ws->buffer_unmap(buf->cs_handle);
701 if (!resize_buffer(dec, buf, new_size)) {
702 RUVD_ERR("Can't resize bitstream buffer!");
703 return;
704 }
705
706 dec->bs_ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs,
707 PIPE_TRANSFER_WRITE);
708 if (!dec->bs_ptr)
709 return;
710
711 dec->bs_ptr += dec->bs_size;
712 }
713
714 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
715 dec->bs_size += sizes[i];
716 dec->bs_ptr += sizes[i];
717 }
718 }
719
720 /**
721 * end decoding of the current frame
722 */
723 static void ruvd_end_frame(struct pipe_video_decoder *decoder,
724 struct pipe_video_buffer *target,
725 struct pipe_picture_desc *picture)
726 {
727 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
728 struct radeon_winsys_cs_handle *dt;
729 struct ruvd_buffer *msg_fb_buf, *bs_buf;
730 struct ruvd_msg msg;
731 unsigned bs_size;
732
733 assert(decoder);
734
735 if (!dec->bs_ptr)
736 return;
737
738 msg_fb_buf = &dec->msg_fb_buffers[dec->cur_buffer];
739 bs_buf = &dec->bs_buffers[dec->cur_buffer];
740
741 bs_size = align(dec->bs_size, 128);
742 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
743 dec->ws->buffer_unmap(bs_buf->cs_handle);
744
745 memset(&msg, 0, sizeof(msg));
746 msg.size = sizeof(msg);
747 msg.msg_type = RUVD_MSG_DECODE;
748 msg.stream_handle = dec->stream_handle;
749 msg.status_report_feedback_number = dec->frame_number;
750
751 msg.body.decode.stream_type = profile2stream_type(dec->base.profile);
752 msg.body.decode.decode_flags = 0x1;
753 msg.body.decode.width_in_samples = dec->base.width;
754 msg.body.decode.height_in_samples = dec->base.height;
755
756 msg.body.decode.dpb_size = dec->dpb.buf->size;
757 msg.body.decode.bsd_size = bs_size;
758
759 dt = dec->set_dtb(&msg, (struct vl_video_buffer *)target);
760
761 switch (u_reduce_video_profile(picture->profile)) {
762 case PIPE_VIDEO_CODEC_MPEG4_AVC:
763 msg.body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
764 break;
765
766 case PIPE_VIDEO_CODEC_VC1:
767 msg.body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
768 break;
769
770 case PIPE_VIDEO_CODEC_MPEG12:
771 msg.body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
772 break;
773
774 case PIPE_VIDEO_CODEC_MPEG4:
775 msg.body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
776 break;
777
778 default:
779 assert(0);
780 return;
781 }
782
783 msg.body.decode.db_surf_tile_config = msg.body.decode.dt_surf_tile_config;
784 msg.body.decode.extension_support = 0x1;
785
786 send_msg(dec, &msg);
787 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.cs_handle, 0,
788 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
789 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->cs_handle,
790 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
791 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
792 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
793 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf->cs_handle,
794 0x1000, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
795 set_reg(dec, RUVD_ENGINE_CNTL, 1);
796
797 flush(dec);
798 next_buffer(dec);
799 }
800
801 /**
802 * flush any outstanding command buffers to the hardware
803 */
804 static void ruvd_flush(struct pipe_video_decoder *decoder)
805 {
806 }
807
808 /**
809 * create and UVD decoder
810 */
811 struct pipe_video_decoder *ruvd_create_decoder(struct pipe_context *context,
812 enum pipe_video_profile profile,
813 enum pipe_video_entrypoint entrypoint,
814 enum pipe_video_chroma_format chroma_format,
815 unsigned width, unsigned height,
816 unsigned max_references, bool expect_chunked_decode,
817 struct radeon_winsys* ws,
818 ruvd_set_dtb set_dtb)
819 {
820 unsigned dpb_size = calc_dpb_size(profile, width, height, max_references);
821 struct ruvd_decoder *dec;
822 struct ruvd_msg msg;
823 int i;
824
825 switch(u_reduce_video_profile(profile)) {
826 case PIPE_VIDEO_CODEC_MPEG12:
827 if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
828 return vl_create_mpeg12_decoder(context, profile, entrypoint,
829 chroma_format, width,
830 height, max_references, expect_chunked_decode);
831
832 /* fall through */
833 case PIPE_VIDEO_CODEC_MPEG4:
834 case PIPE_VIDEO_CODEC_MPEG4_AVC:
835 width = align(width, VL_MACROBLOCK_WIDTH);
836 height = align(height, VL_MACROBLOCK_HEIGHT);
837 break;
838
839 default:
840 break;
841 }
842
843
844 dec = CALLOC_STRUCT(ruvd_decoder);
845
846 if (!dec)
847 return NULL;
848
849 dec->base.context = context;
850 dec->base.profile = profile;
851 dec->base.entrypoint = entrypoint;
852 dec->base.chroma_format = chroma_format;
853 dec->base.width = width;
854 dec->base.height = height;
855
856 dec->base.destroy = ruvd_destroy;
857 dec->base.begin_frame = ruvd_begin_frame;
858 dec->base.decode_macroblock = ruvd_decode_macroblock;
859 dec->base.decode_bitstream = ruvd_decode_bitstream;
860 dec->base.end_frame = ruvd_end_frame;
861 dec->base.flush = ruvd_flush;
862
863 dec->set_dtb = set_dtb;
864 dec->stream_handle = alloc_stream_handle();
865 dec->ws = ws;
866 dec->cs = ws->cs_create(ws, RING_UVD, NULL);
867 if (!dec->cs) {
868 RUVD_ERR("Can't get command submission context.\n");
869 goto error;
870 }
871
872 for (i = 0; i < NUM_BUFFERS; ++i) {
873 unsigned msg_fb_size = align(sizeof(struct ruvd_msg), 0x1000) + 0x1000;
874 if (!create_buffer(dec, &dec->msg_fb_buffers[i], msg_fb_size)) {
875 RUVD_ERR("Can't allocated message buffers.\n");
876 goto error;
877 }
878
879 if (!create_buffer(dec, &dec->bs_buffers[i], 4096)) {
880 RUVD_ERR("Can't allocated bitstream buffers.\n");
881 goto error;
882 }
883
884 clear_buffer(dec, &dec->msg_fb_buffers[i]);
885 clear_buffer(dec, &dec->bs_buffers[i]);
886 }
887
888 if (!create_buffer(dec, &dec->dpb, dpb_size)) {
889 RUVD_ERR("Can't allocated dpb.\n");
890 goto error;
891 }
892
893 clear_buffer(dec, &dec->dpb);
894
895 memset(&msg, 0, sizeof(msg));
896 msg.size = sizeof(msg);
897 msg.msg_type = RUVD_MSG_CREATE;
898 msg.stream_handle = dec->stream_handle;
899 msg.body.create.stream_type = profile2stream_type(dec->base.profile);
900 msg.body.create.width_in_samples = dec->base.width;
901 msg.body.create.height_in_samples = dec->base.height;
902 msg.body.create.dpb_size = dec->dpb.buf->size;
903 send_msg(dec, &msg);
904 flush(dec);
905 next_buffer(dec);
906
907 return &dec->base;
908
909 error:
910 if (dec->cs) dec->ws->cs_destroy(dec->cs);
911
912 for (i = 0; i < NUM_BUFFERS; ++i) {
913 destroy_buffer(&dec->msg_fb_buffers[i]);
914 destroy_buffer(&dec->bs_buffers[i]);
915 }
916
917 destroy_buffer(&dec->dpb);
918
919 FREE(dec);
920
921 return NULL;
922 }
923
924 /**
925 * join surfaces into the same buffer with identical tiling params
926 * sumup their sizes and replace the backend buffers with a single bo
927 */
928 void ruvd_join_surfaces(struct radeon_winsys* ws, unsigned bind,
929 struct pb_buffer** buffers[VL_NUM_COMPONENTS],
930 struct radeon_surface *surfaces[VL_NUM_COMPONENTS])
931 {
932 unsigned best_tiling, best_wh, off;
933 unsigned size, alignment;
934 struct pb_buffer *pb;
935 unsigned i, j;
936
937 for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
938 unsigned wh;
939
940 if (!surfaces[i])
941 continue;
942
943 /* choose the smallest bank w/h for now */
944 wh = surfaces[i]->bankw * surfaces[i]->bankh;
945 if (wh < best_wh) {
946 best_wh = wh;
947 best_tiling = i;
948 }
949 }
950
951 for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
952 if (!surfaces[i])
953 continue;
954
955 /* copy the tiling parameters */
956 surfaces[i]->bankw = surfaces[best_tiling]->bankw;
957 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
958 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
959 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
960
961 /* adjust the texture layer offsets */
962 off = align(off, surfaces[i]->bo_alignment);
963 for (j = 0; j < Elements(surfaces[i]->level); ++j)
964 surfaces[i]->level[j].offset += off;
965 off += surfaces[i]->bo_size;
966 }
967
968 for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
969 if (!buffers[i] || !*buffers[i])
970 continue;
971
972 size = align(size, (*buffers[i])->alignment);
973 size += (*buffers[i])->size;
974 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
975 }
976
977 if (!size)
978 return;
979
980 /* TODO: 2D tiling workaround */
981 alignment *= 2;
982
983 pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM);
984 if (!pb)
985 return;
986
987 for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
988 if (!buffers[i] || !*buffers[i])
989 continue;
990
991 pb_reference(buffers[i], pb);
992 }
993
994 pb_reference(&pb, NULL);
995 }
996
997 /* calculate top/bottom offset */
998 static unsigned texture_offset(struct radeon_surface *surface, unsigned layer)
999 {
1000 return surface->level[0].offset +
1001 layer * surface->level[0].slice_size;
1002 }
1003
1004 /* hw encode the aspect of macro tiles */
1005 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1006 {
1007 switch (macro_tile_aspect) {
1008 default:
1009 case 1: macro_tile_aspect = 0; break;
1010 case 2: macro_tile_aspect = 1; break;
1011 case 4: macro_tile_aspect = 2; break;
1012 case 8: macro_tile_aspect = 3; break;
1013 }
1014 return macro_tile_aspect;
1015 }
1016
1017 /* hw encode the bank width and height */
1018 static unsigned bank_wh(unsigned bankwh)
1019 {
1020 switch (bankwh) {
1021 default:
1022 case 1: bankwh = 0; break;
1023 case 2: bankwh = 1; break;
1024 case 4: bankwh = 2; break;
1025 case 8: bankwh = 3; break;
1026 }
1027 return bankwh;
1028 }
1029
1030 /**
1031 * fill decoding target field from the luma and chroma surfaces
1032 */
1033 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
1034 struct radeon_surface *chroma)
1035 {
1036 msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
1037 switch (luma->level[0].mode) {
1038 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1039 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1040 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1041 break;
1042 case RADEON_SURF_MODE_1D:
1043 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1044 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1045 break;
1046 case RADEON_SURF_MODE_2D:
1047 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1048 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1049 break;
1050 default:
1051 assert(0);
1052 break;
1053 }
1054
1055 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
1056 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
1057 if (msg->body.decode.dt_field_mode) {
1058 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
1059 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
1060 } else {
1061 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1062 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1063 }
1064
1065 assert(luma->bankw == chroma->bankw);
1066 assert(luma->bankh == chroma->bankh);
1067 assert(luma->mtilea == chroma->mtilea);
1068
1069 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
1070 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
1071 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
1072 }
1073
1074 int ruvd_get_video_param(struct pipe_screen *screen,
1075 enum pipe_video_profile profile,
1076 enum pipe_video_cap param)
1077 {
1078 switch (param) {
1079 case PIPE_VIDEO_CAP_SUPPORTED:
1080 switch (u_reduce_video_profile(profile)) {
1081 case PIPE_VIDEO_CODEC_MPEG12:
1082 case PIPE_VIDEO_CODEC_MPEG4:
1083 case PIPE_VIDEO_CODEC_MPEG4_AVC:
1084 case PIPE_VIDEO_CODEC_VC1:
1085 return true;
1086 default:
1087 return false;
1088 }
1089 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
1090 return 1;
1091 case PIPE_VIDEO_CAP_MAX_WIDTH:
1092 return 2048;
1093 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1094 return 1152;
1095 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1096 return PIPE_FORMAT_NV12;
1097 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1098 return false;
1099 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1100 return false; /* TODO: enable this */
1101 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1102 return true;
1103 default:
1104 return 0;
1105 }
1106 }
1107
1108 boolean ruvd_is_format_supported(struct pipe_screen *screen,
1109 enum pipe_format format,
1110 enum pipe_video_profile profile)
1111 {
1112 /* we can only handle this one anyway */
1113 return format == PIPE_FORMAT_NV12;
1114 }