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radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size
[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_codec.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "r600_pipe_common.h"
49 #include "radeon_video.h"
50 #include "radeon_uvd.h"
51
52 #define NUM_BUFFERS 4
53
54 #define NUM_MPEG2_REFS 6
55 #define NUM_H264_REFS 17
56 #define NUM_VC1_REFS 5
57
58 #define FB_BUFFER_OFFSET 0x1000
59 #define FB_BUFFER_SIZE 2048
60 #define IT_SCALING_TABLE_SIZE 224
61
62 /* UVD decoder representation */
63 struct ruvd_decoder {
64 struct pipe_video_codec base;
65
66 ruvd_set_dtb set_dtb;
67
68 unsigned stream_handle;
69 unsigned stream_type;
70 unsigned frame_number;
71
72 struct pipe_screen *screen;
73 struct radeon_winsys* ws;
74 struct radeon_winsys_cs* cs;
75
76 unsigned cur_buffer;
77
78 struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
79 struct ruvd_msg *msg;
80 uint32_t *fb;
81 uint8_t *it;
82
83 struct rvid_buffer bs_buffers[NUM_BUFFERS];
84 void* bs_ptr;
85 unsigned bs_size;
86
87 struct rvid_buffer dpb;
88 bool use_legacy;
89 };
90
91 /* flush IB to the hardware */
92 static void flush(struct ruvd_decoder *dec)
93 {
94 dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL, 0);
95 }
96
97 /* add a new set register command to the IB */
98 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
99 {
100 uint32_t *pm4 = dec->cs->buf;
101 pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0);
102 pm4[dec->cs->cdw++] = val;
103 }
104
105 /* send a command to the VCPU through the GPCOM registers */
106 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
107 struct radeon_winsys_cs_handle* cs_buf, uint32_t off,
108 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
109 {
110 int reloc_idx;
111
112 reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain,
113 RADEON_PRIO_MIN);
114 if (!dec->use_legacy) {
115 uint64_t addr;
116 addr = dec->ws->buffer_get_virtual_address(cs_buf);
117 addr = addr + off;
118 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
119 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
120 } else {
121 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
122 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
123 }
124 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
125 }
126
127 /* map the next available message/feedback/itscaling buffer */
128 static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
129 {
130 struct rvid_buffer* buf;
131 uint8_t *ptr;
132
133 /* grab the current message/feedback buffer */
134 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
135
136 /* and map it for CPU access */
137 ptr = dec->ws->buffer_map(buf->res->cs_buf, dec->cs, PIPE_TRANSFER_WRITE);
138
139 /* calc buffer offsets */
140 dec->msg = (struct ruvd_msg *)ptr;
141 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
142 if (dec->stream_type == RUVD_CODEC_H264_PERF)
143 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
144 }
145
146 /* unmap and send a message command to the VCPU */
147 static void send_msg_buf(struct ruvd_decoder *dec)
148 {
149 struct rvid_buffer* buf;
150
151 /* ignore the request if message/feedback buffer isn't mapped */
152 if (!dec->msg || !dec->fb)
153 return;
154
155 /* grab the current message buffer */
156 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
157
158 /* unmap the buffer */
159 dec->ws->buffer_unmap(buf->res->cs_buf);
160 dec->msg = NULL;
161 dec->fb = NULL;
162 if (dec->stream_type == RUVD_CODEC_H264_PERF)
163 dec->it = NULL;
164
165 /* and send it to the hardware */
166 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->cs_buf, 0,
167 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
168 }
169
170 /* cycle to the next set of buffers */
171 static void next_buffer(struct ruvd_decoder *dec)
172 {
173 ++dec->cur_buffer;
174 dec->cur_buffer %= NUM_BUFFERS;
175 }
176
177 /* convert the profile into something UVD understands */
178 static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
179 {
180 switch (u_reduce_video_profile(dec->base.profile)) {
181 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
182 return (family >= CHIP_TONGA) ?
183 RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
184
185 case PIPE_VIDEO_FORMAT_VC1:
186 return RUVD_CODEC_VC1;
187
188 case PIPE_VIDEO_FORMAT_MPEG12:
189 return RUVD_CODEC_MPEG2;
190
191 case PIPE_VIDEO_FORMAT_MPEG4:
192 return RUVD_CODEC_MPEG4;
193
194 default:
195 assert(0);
196 return 0;
197 }
198 }
199
200 /* calculate size of reference picture buffer */
201 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
202 {
203 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
204
205 // always align them to MB size for dpb calculation
206 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
207 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
208
209 // always one more for currently decoded picture
210 unsigned max_references = dec->base.max_references + 1;
211
212 // aligned size of a single frame
213 image_size = width * height;
214 image_size += image_size / 2;
215 image_size = align(image_size, 1024);
216
217 // picture width & height in 16 pixel units
218 width_in_mb = width / VL_MACROBLOCK_WIDTH;
219 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
220
221 switch (u_reduce_video_profile(dec->base.profile)) {
222 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
223 if (!dec->use_legacy) {
224 unsigned fs_in_mb = width_in_mb * height_in_mb;
225 unsigned alignment = 64, num_dpb_buffer;
226
227 if (dec->stream_type == RUVD_CODEC_H264_PERF)
228 alignment = 256;
229 switch(dec->base.level) {
230 case 30:
231 num_dpb_buffer = 8100 / fs_in_mb;
232 break;
233 case 31:
234 num_dpb_buffer = 18000 / fs_in_mb;
235 break;
236 case 32:
237 num_dpb_buffer = 20480 / fs_in_mb;
238 break;
239 case 41:
240 num_dpb_buffer = 32768 / fs_in_mb;
241 break;
242 case 42:
243 num_dpb_buffer = 34816 / fs_in_mb;
244 break;
245 case 50:
246 num_dpb_buffer = 110400 / fs_in_mb;
247 break;
248 case 51:
249 num_dpb_buffer = 184320 / fs_in_mb;
250 break;
251 default:
252 num_dpb_buffer = 184320 / fs_in_mb;
253 break;
254 }
255 num_dpb_buffer++;
256 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
257 dpb_size = image_size * max_references;
258 dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
259 dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
260 } else {
261 // the firmware seems to allways assume a minimum of ref frames
262 max_references = MAX2(NUM_H264_REFS, max_references);
263 // reference picture buffer
264 dpb_size = image_size * max_references;
265 // macroblock context buffer
266 dpb_size += width_in_mb * height_in_mb * max_references * 192;
267 // IT surface buffer
268 dpb_size += width_in_mb * height_in_mb * 32;
269 }
270 break;
271 }
272
273 case PIPE_VIDEO_FORMAT_VC1:
274 // the firmware seems to allways assume a minimum of ref frames
275 max_references = MAX2(NUM_VC1_REFS, max_references);
276
277 // reference picture buffer
278 dpb_size = image_size * max_references;
279
280 // CONTEXT_BUFFER
281 dpb_size += width_in_mb * height_in_mb * 128;
282
283 // IT surface buffer
284 dpb_size += width_in_mb * 64;
285
286 // DB surface buffer
287 dpb_size += width_in_mb * 128;
288
289 // BP
290 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
291 break;
292
293 case PIPE_VIDEO_FORMAT_MPEG12:
294 // reference picture buffer, must be big enough for all frames
295 dpb_size = image_size * NUM_MPEG2_REFS;
296 break;
297
298 case PIPE_VIDEO_FORMAT_MPEG4:
299 // reference picture buffer
300 dpb_size = image_size * max_references;
301
302 // CM
303 dpb_size += width_in_mb * height_in_mb * 64;
304
305 // IT surface buffer
306 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
307
308 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
309 break;
310
311 default:
312 // something is missing here
313 assert(0);
314
315 // at least use a sane default value
316 dpb_size = 32 * 1024 * 1024;
317 break;
318 }
319 return dpb_size;
320 }
321
322 /* get h264 specific message bits */
323 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
324 {
325 struct ruvd_h264 result;
326
327 memset(&result, 0, sizeof(result));
328 switch (pic->base.profile) {
329 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
330 result.profile = RUVD_H264_PROFILE_BASELINE;
331 break;
332
333 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
334 result.profile = RUVD_H264_PROFILE_MAIN;
335 break;
336
337 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
338 result.profile = RUVD_H264_PROFILE_HIGH;
339 break;
340
341 default:
342 assert(0);
343 break;
344 }
345
346 result.level = dec->base.level;
347
348 result.sps_info_flags = 0;
349 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
350 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
351 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
352 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
353
354 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
355 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
356 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
357 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
358 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
359
360 switch (dec->base.chroma_format) {
361 case PIPE_VIDEO_CHROMA_FORMAT_400:
362 result.chroma_format = 0;
363 break;
364 case PIPE_VIDEO_CHROMA_FORMAT_420:
365 result.chroma_format = 1;
366 break;
367 case PIPE_VIDEO_CHROMA_FORMAT_422:
368 result.chroma_format = 2;
369 break;
370 case PIPE_VIDEO_CHROMA_FORMAT_444:
371 result.chroma_format = 3;
372 break;
373 }
374
375 result.pps_info_flags = 0;
376 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
377 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
378 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
379 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
380 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
381 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
382 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
383 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
384
385 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
386 result.slice_group_map_type = pic->pps->slice_group_map_type;
387 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
388 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
389 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
390 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
391
392 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
393 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
394
395 result.num_ref_frames = pic->num_ref_frames;
396
397 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
398 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
399
400 result.frame_num = pic->frame_num;
401 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
402 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
403 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
404 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
405
406 result.decoded_pic_idx = pic->frame_num;
407
408 return result;
409 }
410
411 /* get vc1 specific message bits */
412 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
413 {
414 struct ruvd_vc1 result;
415
416 memset(&result, 0, sizeof(result));
417
418 switch(pic->base.profile) {
419 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
420 result.profile = RUVD_VC1_PROFILE_SIMPLE;
421 result.level = 1;
422 break;
423
424 case PIPE_VIDEO_PROFILE_VC1_MAIN:
425 result.profile = RUVD_VC1_PROFILE_MAIN;
426 result.level = 2;
427 break;
428
429 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
430 result.profile = RUVD_VC1_PROFILE_ADVANCED;
431 result.level = 4;
432 break;
433
434 default:
435 assert(0);
436 }
437
438 /* fields common for all profiles */
439 result.sps_info_flags |= pic->postprocflag << 7;
440 result.sps_info_flags |= pic->pulldown << 6;
441 result.sps_info_flags |= pic->interlace << 5;
442 result.sps_info_flags |= pic->tfcntrflag << 4;
443 result.sps_info_flags |= pic->finterpflag << 3;
444 result.sps_info_flags |= pic->psf << 1;
445
446 result.pps_info_flags |= pic->range_mapy_flag << 31;
447 result.pps_info_flags |= pic->range_mapy << 28;
448 result.pps_info_flags |= pic->range_mapuv_flag << 27;
449 result.pps_info_flags |= pic->range_mapuv << 24;
450 result.pps_info_flags |= pic->multires << 21;
451 result.pps_info_flags |= pic->maxbframes << 16;
452 result.pps_info_flags |= pic->overlap << 11;
453 result.pps_info_flags |= pic->quantizer << 9;
454 result.pps_info_flags |= pic->panscan_flag << 7;
455 result.pps_info_flags |= pic->refdist_flag << 6;
456 result.pps_info_flags |= pic->vstransform << 0;
457
458 /* some fields only apply to main/advanced profile */
459 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
460 result.pps_info_flags |= pic->syncmarker << 20;
461 result.pps_info_flags |= pic->rangered << 19;
462 result.pps_info_flags |= pic->loopfilter << 5;
463 result.pps_info_flags |= pic->fastuvmc << 4;
464 result.pps_info_flags |= pic->extended_mv << 3;
465 result.pps_info_flags |= pic->extended_dmv << 8;
466 result.pps_info_flags |= pic->dquant << 1;
467 }
468
469 result.chroma_format = 1;
470
471 #if 0
472 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
473 uint32_t slice_count
474 uint8_t picture_type
475 uint8_t frame_coding_mode
476 uint8_t deblockEnable
477 uint8_t pquant
478 #endif
479
480 return result;
481 }
482
483 /* extract the frame number from a referenced video buffer */
484 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
485 {
486 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
487 uint32_t max = MAX2(dec->frame_number, 1) - 1;
488 uintptr_t frame;
489
490 /* seems to be the most sane fallback */
491 if (!ref)
492 return max;
493
494 /* get the frame number from the associated data */
495 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
496
497 /* limit the frame number to a valid range */
498 return MAX2(MIN2(frame, max), min);
499 }
500
501 /* get mpeg2 specific msg bits */
502 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
503 struct pipe_mpeg12_picture_desc *pic)
504 {
505 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
506 struct ruvd_mpeg2 result;
507 unsigned i;
508
509 memset(&result, 0, sizeof(result));
510 result.decoded_pic_idx = dec->frame_number;
511 for (i = 0; i < 2; ++i)
512 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
513
514 result.load_intra_quantiser_matrix = 1;
515 result.load_nonintra_quantiser_matrix = 1;
516
517 for (i = 0; i < 64; ++i) {
518 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
519 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
520 }
521
522 result.profile_and_level_indication = 0;
523 result.chroma_format = 0x1;
524
525 result.picture_coding_type = pic->picture_coding_type;
526 result.f_code[0][0] = pic->f_code[0][0] + 1;
527 result.f_code[0][1] = pic->f_code[0][1] + 1;
528 result.f_code[1][0] = pic->f_code[1][0] + 1;
529 result.f_code[1][1] = pic->f_code[1][1] + 1;
530 result.intra_dc_precision = pic->intra_dc_precision;
531 result.pic_structure = pic->picture_structure;
532 result.top_field_first = pic->top_field_first;
533 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
534 result.concealment_motion_vectors = pic->concealment_motion_vectors;
535 result.q_scale_type = pic->q_scale_type;
536 result.intra_vlc_format = pic->intra_vlc_format;
537 result.alternate_scan = pic->alternate_scan;
538
539 return result;
540 }
541
542 /* get mpeg4 specific msg bits */
543 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
544 struct pipe_mpeg4_picture_desc *pic)
545 {
546 struct ruvd_mpeg4 result;
547 unsigned i;
548
549 memset(&result, 0, sizeof(result));
550 result.decoded_pic_idx = dec->frame_number;
551 for (i = 0; i < 2; ++i)
552 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
553
554 result.variant_type = 0;
555 result.profile_and_level_indication = 0xF0; // ASP Level0
556
557 result.video_object_layer_verid = 0x5; // advanced simple
558 result.video_object_layer_shape = 0x0; // rectangular
559
560 result.video_object_layer_width = dec->base.width;
561 result.video_object_layer_height = dec->base.height;
562
563 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
564
565 result.flags |= pic->short_video_header << 0;
566 //result.flags |= obmc_disable << 1;
567 result.flags |= pic->interlaced << 2;
568 result.flags |= 1 << 3; // load_intra_quant_mat
569 result.flags |= 1 << 4; // load_nonintra_quant_mat
570 result.flags |= pic->quarter_sample << 5;
571 result.flags |= 1 << 6; // complexity_estimation_disable
572 result.flags |= pic->resync_marker_disable << 7;
573 //result.flags |= data_partitioned << 8;
574 //result.flags |= reversible_vlc << 9;
575 result.flags |= 0 << 10; // newpred_enable
576 result.flags |= 0 << 11; // reduced_resolution_vop_enable
577 //result.flags |= scalability << 12;
578 //result.flags |= is_object_layer_identifier << 13;
579 //result.flags |= fixed_vop_rate << 14;
580 //result.flags |= newpred_segment_type << 15;
581
582 result.quant_type = pic->quant_type;
583
584 for (i = 0; i < 64; ++i) {
585 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
586 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
587 }
588
589 /*
590 int32_t trd [2]
591 int32_t trb [2]
592 uint8_t vop_coding_type
593 uint8_t vop_fcode_forward
594 uint8_t vop_fcode_backward
595 uint8_t rounding_control
596 uint8_t alternate_vertical_scan_flag
597 uint8_t top_field_first
598 */
599
600 return result;
601 }
602
603 /**
604 * destroy this video decoder
605 */
606 static void ruvd_destroy(struct pipe_video_codec *decoder)
607 {
608 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
609 unsigned i;
610
611 assert(decoder);
612
613 map_msg_fb_it_buf(dec);
614 memset(dec->msg, 0, sizeof(*dec->msg));
615 dec->msg->size = sizeof(*dec->msg);
616 dec->msg->msg_type = RUVD_MSG_DESTROY;
617 dec->msg->stream_handle = dec->stream_handle;
618 send_msg_buf(dec);
619
620 flush(dec);
621
622 dec->ws->cs_destroy(dec->cs);
623
624 for (i = 0; i < NUM_BUFFERS; ++i) {
625 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
626 rvid_destroy_buffer(&dec->bs_buffers[i]);
627 }
628
629 rvid_destroy_buffer(&dec->dpb);
630
631 FREE(dec);
632 }
633
634 /* free associated data in the video buffer callback */
635 static void ruvd_destroy_associated_data(void *data)
636 {
637 /* NOOP, since we only use an intptr */
638 }
639
640 /**
641 * start decoding of a new frame
642 */
643 static void ruvd_begin_frame(struct pipe_video_codec *decoder,
644 struct pipe_video_buffer *target,
645 struct pipe_picture_desc *picture)
646 {
647 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
648 uintptr_t frame;
649
650 assert(decoder);
651
652 frame = ++dec->frame_number;
653 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
654 &ruvd_destroy_associated_data);
655
656 dec->bs_size = 0;
657 dec->bs_ptr = dec->ws->buffer_map(
658 dec->bs_buffers[dec->cur_buffer].res->cs_buf,
659 dec->cs, PIPE_TRANSFER_WRITE);
660 }
661
662 /**
663 * decode a macroblock
664 */
665 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
666 struct pipe_video_buffer *target,
667 struct pipe_picture_desc *picture,
668 const struct pipe_macroblock *macroblocks,
669 unsigned num_macroblocks)
670 {
671 /* not supported (yet) */
672 assert(0);
673 }
674
675 /**
676 * decode a bitstream
677 */
678 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
679 struct pipe_video_buffer *target,
680 struct pipe_picture_desc *picture,
681 unsigned num_buffers,
682 const void * const *buffers,
683 const unsigned *sizes)
684 {
685 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
686 unsigned i;
687
688 assert(decoder);
689
690 if (!dec->bs_ptr)
691 return;
692
693 for (i = 0; i < num_buffers; ++i) {
694 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
695 unsigned new_size = dec->bs_size + sizes[i];
696
697 if (new_size > buf->res->buf->size) {
698 dec->ws->buffer_unmap(buf->res->cs_buf);
699 if (!rvid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
700 RVID_ERR("Can't resize bitstream buffer!");
701 return;
702 }
703
704 dec->bs_ptr = dec->ws->buffer_map(buf->res->cs_buf, dec->cs,
705 PIPE_TRANSFER_WRITE);
706 if (!dec->bs_ptr)
707 return;
708
709 dec->bs_ptr += dec->bs_size;
710 }
711
712 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
713 dec->bs_size += sizes[i];
714 dec->bs_ptr += sizes[i];
715 }
716 }
717
718 /**
719 * end decoding of the current frame
720 */
721 static void ruvd_end_frame(struct pipe_video_codec *decoder,
722 struct pipe_video_buffer *target,
723 struct pipe_picture_desc *picture)
724 {
725 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
726 struct radeon_winsys_cs_handle *dt;
727 struct rvid_buffer *msg_fb_it_buf, *bs_buf;
728 unsigned bs_size;
729
730 assert(decoder);
731
732 if (!dec->bs_ptr)
733 return;
734
735 msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
736 bs_buf = &dec->bs_buffers[dec->cur_buffer];
737
738 bs_size = align(dec->bs_size, 128);
739 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
740 dec->ws->buffer_unmap(bs_buf->res->cs_buf);
741
742 map_msg_fb_it_buf(dec);
743 dec->msg->size = sizeof(*dec->msg);
744 dec->msg->msg_type = RUVD_MSG_DECODE;
745 dec->msg->stream_handle = dec->stream_handle;
746 dec->msg->status_report_feedback_number = dec->frame_number;
747
748 dec->msg->body.decode.stream_type = dec->stream_type;
749 dec->msg->body.decode.decode_flags = 0x1;
750 dec->msg->body.decode.width_in_samples = dec->base.width;
751 dec->msg->body.decode.height_in_samples = dec->base.height;
752
753 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
754 dec->msg->body.decode.bsd_size = bs_size;
755 dec->msg->body.decode.db_pitch = dec->base.width;
756
757 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
758
759 switch (u_reduce_video_profile(picture->profile)) {
760 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
761 dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
762 if (dec->stream_type == RUVD_CODEC_H264_PERF) {
763 memcpy(dec->it, dec->msg->body.decode.codec.h264.scaling_list_4x4, 6*16);
764 memcpy((dec->it + 96), dec->msg->body.decode.codec.h264.scaling_list_8x8, 2*64);
765 }
766 break;
767
768 case PIPE_VIDEO_FORMAT_VC1:
769 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
770 break;
771
772 case PIPE_VIDEO_FORMAT_MPEG12:
773 dec->msg->body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
774 break;
775
776 case PIPE_VIDEO_FORMAT_MPEG4:
777 dec->msg->body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
778 break;
779
780 default:
781 assert(0);
782 return;
783 }
784
785 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
786 dec->msg->body.decode.extension_support = 0x1;
787
788 /* set at least the feedback buffer size */
789 dec->fb[0] = FB_BUFFER_SIZE;
790
791 send_msg_buf(dec);
792
793 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->cs_buf, 0,
794 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
795 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->cs_buf,
796 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
797 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
798 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
799 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->cs_buf,
800 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
801 if (dec->stream_type == RUVD_CODEC_H264_PERF)
802 send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->cs_buf,
803 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
804 set_reg(dec, RUVD_ENGINE_CNTL, 1);
805
806 flush(dec);
807 next_buffer(dec);
808 }
809
810 /**
811 * flush any outstanding command buffers to the hardware
812 */
813 static void ruvd_flush(struct pipe_video_codec *decoder)
814 {
815 }
816
817 /**
818 * create and UVD decoder
819 */
820 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
821 const struct pipe_video_codec *templ,
822 ruvd_set_dtb set_dtb)
823 {
824 struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
825 struct r600_common_context *rctx = (struct r600_common_context*)context;
826 unsigned dpb_size;
827 unsigned width = templ->width, height = templ->height;
828 unsigned bs_buf_size;
829 struct radeon_info info;
830 struct ruvd_decoder *dec;
831 int i;
832
833 ws->query_info(ws, &info);
834
835 switch(u_reduce_video_profile(templ->profile)) {
836 case PIPE_VIDEO_FORMAT_MPEG12:
837 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
838 return vl_create_mpeg12_decoder(context, templ);
839
840 /* fall through */
841 case PIPE_VIDEO_FORMAT_MPEG4:
842 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
843 width = align(width, VL_MACROBLOCK_WIDTH);
844 height = align(height, VL_MACROBLOCK_HEIGHT);
845 break;
846
847 default:
848 break;
849 }
850
851
852 dec = CALLOC_STRUCT(ruvd_decoder);
853
854 if (!dec)
855 return NULL;
856
857 if (info.drm_major < 3)
858 dec->use_legacy = TRUE;
859
860 dec->base = *templ;
861 dec->base.context = context;
862 dec->base.width = width;
863 dec->base.height = height;
864
865 dec->base.destroy = ruvd_destroy;
866 dec->base.begin_frame = ruvd_begin_frame;
867 dec->base.decode_macroblock = ruvd_decode_macroblock;
868 dec->base.decode_bitstream = ruvd_decode_bitstream;
869 dec->base.end_frame = ruvd_end_frame;
870 dec->base.flush = ruvd_flush;
871
872 dec->stream_type = profile2stream_type(dec, info.family);
873 dec->set_dtb = set_dtb;
874 dec->stream_handle = rvid_alloc_stream_handle();
875 dec->screen = context->screen;
876 dec->ws = ws;
877 dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL, NULL);
878 if (!dec->cs) {
879 RVID_ERR("Can't get command submission context.\n");
880 goto error;
881 }
882
883 bs_buf_size = width * height * 512 / (16 * 16);
884 for (i = 0; i < NUM_BUFFERS; ++i) {
885 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
886 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
887 if (dec->stream_type == RUVD_CODEC_H264_PERF)
888 msg_fb_it_size += IT_SCALING_TABLE_SIZE;
889 if (!rvid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
890 msg_fb_it_size, PIPE_USAGE_STAGING)) {
891 RVID_ERR("Can't allocated message buffers.\n");
892 goto error;
893 }
894
895 if (!rvid_create_buffer(dec->screen, &dec->bs_buffers[i],
896 bs_buf_size, PIPE_USAGE_STAGING)) {
897 RVID_ERR("Can't allocated bitstream buffers.\n");
898 goto error;
899 }
900
901 rvid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
902 rvid_clear_buffer(context, &dec->bs_buffers[i]);
903 }
904
905 dpb_size = calc_dpb_size(dec);
906
907 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
908 RVID_ERR("Can't allocated dpb.\n");
909 goto error;
910 }
911
912 rvid_clear_buffer(context, &dec->dpb);
913
914 map_msg_fb_it_buf(dec);
915 dec->msg->size = sizeof(*dec->msg);
916 dec->msg->msg_type = RUVD_MSG_CREATE;
917 dec->msg->stream_handle = dec->stream_handle;
918 dec->msg->body.create.stream_type = dec->stream_type;
919 dec->msg->body.create.width_in_samples = dec->base.width;
920 dec->msg->body.create.height_in_samples = dec->base.height;
921 dec->msg->body.create.dpb_size = dec->dpb.res->buf->size;
922 send_msg_buf(dec);
923 flush(dec);
924 next_buffer(dec);
925
926 return &dec->base;
927
928 error:
929 if (dec->cs) dec->ws->cs_destroy(dec->cs);
930
931 for (i = 0; i < NUM_BUFFERS; ++i) {
932 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
933 rvid_destroy_buffer(&dec->bs_buffers[i]);
934 }
935
936 rvid_destroy_buffer(&dec->dpb);
937
938 FREE(dec);
939
940 return NULL;
941 }
942
943 /* calculate top/bottom offset */
944 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
945 {
946 return surface->level[0].offset +
947 layer * surface->level[0].slice_size;
948 }
949
950 /* hw encode the aspect of macro tiles */
951 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
952 {
953 switch (macro_tile_aspect) {
954 default:
955 case 1: macro_tile_aspect = 0; break;
956 case 2: macro_tile_aspect = 1; break;
957 case 4: macro_tile_aspect = 2; break;
958 case 8: macro_tile_aspect = 3; break;
959 }
960 return macro_tile_aspect;
961 }
962
963 /* hw encode the bank width and height */
964 static unsigned bank_wh(unsigned bankwh)
965 {
966 switch (bankwh) {
967 default:
968 case 1: bankwh = 0; break;
969 case 2: bankwh = 1; break;
970 case 4: bankwh = 2; break;
971 case 8: bankwh = 3; break;
972 }
973 return bankwh;
974 }
975
976 /**
977 * fill decoding target field from the luma and chroma surfaces
978 */
979 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
980 struct radeon_surf *chroma)
981 {
982 msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
983 switch (luma->level[0].mode) {
984 case RADEON_SURF_MODE_LINEAR_ALIGNED:
985 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
986 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
987 break;
988 case RADEON_SURF_MODE_1D:
989 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
990 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
991 break;
992 case RADEON_SURF_MODE_2D:
993 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
994 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
995 break;
996 default:
997 assert(0);
998 break;
999 }
1000
1001 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
1002 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
1003 if (msg->body.decode.dt_field_mode) {
1004 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
1005 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
1006 } else {
1007 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1008 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1009 }
1010
1011 assert(luma->bankw == chroma->bankw);
1012 assert(luma->bankh == chroma->bankh);
1013 assert(luma->mtilea == chroma->mtilea);
1014
1015 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
1016 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
1017 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
1018 }