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vl: add entrypoint to is_video_format_supported
[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_codec.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "../../winsys/radeon/drm/radeon_winsys.h"
49 #include "radeon_uvd.h"
50
51 #define RUVD_ERR(fmt, args...) \
52 fprintf(stderr, "EE %s:%d %s UVD - "fmt, __FILE__, __LINE__, __func__, ##args)
53
54 #define NUM_BUFFERS 4
55
56 #define NUM_MPEG2_REFS 6
57 #define NUM_H264_REFS 17
58
59 /* UVD buffer representation */
60 struct ruvd_buffer
61 {
62 struct pb_buffer* buf;
63 struct radeon_winsys_cs_handle* cs_handle;
64 };
65
66 /* UVD decoder representation */
67 struct ruvd_decoder {
68 struct pipe_video_codec base;
69
70 ruvd_set_dtb set_dtb;
71
72 unsigned stream_handle;
73 unsigned frame_number;
74
75 struct radeon_winsys* ws;
76 struct radeon_winsys_cs* cs;
77
78 unsigned cur_buffer;
79
80 struct ruvd_buffer msg_fb_buffers[NUM_BUFFERS];
81 struct ruvd_buffer bs_buffers[NUM_BUFFERS];
82 void* bs_ptr;
83 unsigned bs_size;
84
85 struct ruvd_buffer dpb;
86 };
87
88 /* generate an UVD stream handle */
89 static unsigned alloc_stream_handle()
90 {
91 static unsigned counter = 0;
92 unsigned stream_handle = 0;
93 unsigned pid = getpid();
94 int i;
95
96 for (i = 0; i < 32; ++i)
97 stream_handle |= ((pid >> i) & 1) << (31 - i);
98
99 stream_handle ^= ++counter;
100 return stream_handle;
101 }
102
103 /* flush IB to the hardware */
104 static void flush(struct ruvd_decoder *dec)
105 {
106 uint32_t *pm4 = dec->cs->buf;
107
108 // align IB
109 while(dec->cs->cdw % 16)
110 pm4[dec->cs->cdw++] = RUVD_PKT2();
111
112 dec->ws->cs_flush(dec->cs, 0, 0);
113 }
114
115 /* add a new set register command to the IB */
116 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
117 {
118 uint32_t *pm4 = dec->cs->buf;
119 pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0);
120 pm4[dec->cs->cdw++] = val;
121 }
122
123 /* send a command to the VCPU through the GPCOM registers */
124 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
125 struct radeon_winsys_cs_handle* cs_buf, uint32_t off,
126 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
127 {
128 int reloc_idx;
129
130 reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain);
131 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
132 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
133 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
134 }
135
136 /* send a message command to the VCPU */
137 static void send_msg(struct ruvd_decoder *dec, struct ruvd_msg *msg)
138 {
139 struct ruvd_buffer* buf;
140 void *ptr;
141
142 /* grap a message buffer */
143 buf = &dec->msg_fb_buffers[dec->cur_buffer];
144
145 /* copy the message into it */
146 ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE);
147 if (!ptr)
148 return;
149
150 memcpy(ptr, msg, sizeof(*msg));
151 memset(ptr + sizeof(*msg), 0, buf->buf->size - sizeof(*msg));
152 dec->ws->buffer_unmap(buf->cs_handle);
153
154 /* and send it to the hardware */
155 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->cs_handle, 0,
156 RADEON_USAGE_READ, RADEON_DOMAIN_VRAM);
157 }
158
159 /* create a buffer in the winsys */
160 static bool create_buffer(struct ruvd_decoder *dec,
161 struct ruvd_buffer *buffer,
162 unsigned size)
163 {
164 buffer->buf = dec->ws->buffer_create(dec->ws, size, 4096, false,
165 RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM);
166 if (!buffer->buf)
167 return false;
168
169 buffer->cs_handle = dec->ws->buffer_get_cs_handle(buffer->buf);
170 if (!buffer->cs_handle)
171 return false;
172
173 return true;
174 }
175
176 /* destroy a buffer */
177 static void destroy_buffer(struct ruvd_buffer *buffer)
178 {
179 pb_reference(&buffer->buf, NULL);
180 buffer->cs_handle = NULL;
181 }
182
183 /* reallocate a buffer, preserving its content */
184 static bool resize_buffer(struct ruvd_decoder *dec,
185 struct ruvd_buffer *new_buf,
186 unsigned new_size)
187 {
188 unsigned bytes = MIN2(new_buf->buf->size, new_size);
189 struct ruvd_buffer old_buf = *new_buf;
190 void *src = NULL, *dst = NULL;
191
192 if (!create_buffer(dec, new_buf, new_size))
193 goto error;
194
195 src = dec->ws->buffer_map(old_buf.cs_handle, dec->cs, PIPE_TRANSFER_READ);
196 if (!src)
197 goto error;
198
199 dst = dec->ws->buffer_map(new_buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE);
200 if (!dst)
201 goto error;
202
203 memcpy(dst, src, bytes);
204 if (new_size > bytes) {
205 new_size -= bytes;
206 dst += bytes;
207 memset(dst, 0, new_size);
208 }
209 dec->ws->buffer_unmap(new_buf->cs_handle);
210 dec->ws->buffer_unmap(old_buf.cs_handle);
211 destroy_buffer(&old_buf);
212 return true;
213
214 error:
215 if (src) dec->ws->buffer_unmap(old_buf.cs_handle);
216 destroy_buffer(new_buf);
217 *new_buf = old_buf;
218 return false;
219 }
220
221 /* clear the buffer with zeros */
222 static void clear_buffer(struct ruvd_decoder *dec,
223 struct ruvd_buffer* buffer)
224 {
225 //TODO: let the GPU do the job
226 void *ptr = dec->ws->buffer_map(buffer->cs_handle, dec->cs,
227 PIPE_TRANSFER_WRITE);
228 if (!ptr)
229 return;
230
231 memset(ptr, 0, buffer->buf->size);
232 dec->ws->buffer_unmap(buffer->cs_handle);
233 }
234
235 /* cycle to the next set of buffers */
236 static void next_buffer(struct ruvd_decoder *dec)
237 {
238 ++dec->cur_buffer;
239 dec->cur_buffer %= NUM_BUFFERS;
240 }
241
242 /* convert the profile into something UVD understands */
243 static uint32_t profile2stream_type(enum pipe_video_profile profile)
244 {
245 switch (u_reduce_video_profile(profile)) {
246 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
247 return RUVD_CODEC_H264;
248
249 case PIPE_VIDEO_FORMAT_VC1:
250 return RUVD_CODEC_VC1;
251
252 case PIPE_VIDEO_FORMAT_MPEG12:
253 return RUVD_CODEC_MPEG2;
254
255 case PIPE_VIDEO_FORMAT_MPEG4:
256 return RUVD_CODEC_MPEG4;
257
258 default:
259 assert(0);
260 return 0;
261 }
262 }
263
264 /* calculate size of reference picture buffer */
265 static unsigned calc_dpb_size(const struct pipe_video_codec *templ)
266 {
267 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
268
269 // always align them to MB size for dpb calculation
270 unsigned width = align(templ->width, VL_MACROBLOCK_WIDTH);
271 unsigned height = align(templ->height, VL_MACROBLOCK_HEIGHT);
272
273 // always one more for currently decoded picture
274 unsigned max_references = templ->max_references + 1;
275
276 // aligned size of a single frame
277 image_size = width * height;
278 image_size += image_size / 2;
279 image_size = align(image_size, 1024);
280
281 // picture width & height in 16 pixel units
282 width_in_mb = width / VL_MACROBLOCK_WIDTH;
283 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
284
285 switch (u_reduce_video_profile(templ->profile)) {
286 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
287 // the firmware seems to allways assume a minimum of ref frames
288 max_references = MAX2(NUM_H264_REFS, max_references);
289
290 // reference picture buffer
291 dpb_size = image_size * max_references;
292
293 // macroblock context buffer
294 dpb_size += width_in_mb * height_in_mb * max_references * 192;
295
296 // IT surface buffer
297 dpb_size += width_in_mb * height_in_mb * 32;
298 break;
299
300 case PIPE_VIDEO_FORMAT_VC1:
301 // reference picture buffer
302 dpb_size = image_size * max_references;
303
304 // CONTEXT_BUFFER
305 dpb_size += width_in_mb * height_in_mb * 128;
306
307 // IT surface buffer
308 dpb_size += width_in_mb * 64;
309
310 // DB surface buffer
311 dpb_size += width_in_mb * 128;
312
313 // BP
314 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
315 break;
316
317 case PIPE_VIDEO_FORMAT_MPEG12:
318 // reference picture buffer, must be big enough for all frames
319 dpb_size = image_size * NUM_MPEG2_REFS;
320 break;
321
322 case PIPE_VIDEO_FORMAT_MPEG4:
323 // reference picture buffer
324 dpb_size = image_size * max_references;
325
326 // CM
327 dpb_size += width_in_mb * height_in_mb * 64;
328
329 // IT surface buffer
330 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
331 break;
332
333 default:
334 // something is missing here
335 assert(0);
336
337 // at least use a sane default value
338 dpb_size = 32 * 1024 * 1024;
339 break;
340 }
341 return dpb_size;
342 }
343
344 /* get h264 specific message bits */
345 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
346 {
347 struct ruvd_h264 result;
348
349 memset(&result, 0, sizeof(result));
350 switch (pic->base.profile) {
351 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
352 result.profile = RUVD_H264_PROFILE_BASELINE;
353 break;
354
355 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
356 result.profile = RUVD_H264_PROFILE_MAIN;
357 break;
358
359 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
360 result.profile = RUVD_H264_PROFILE_HIGH;
361 break;
362
363 default:
364 assert(0);
365 break;
366 }
367 if (((dec->base.width * dec->base.height) >> 8) <= 1620)
368 result.level = 30;
369 else
370 result.level = 41;
371
372 result.sps_info_flags = 0;
373 result.sps_info_flags |= pic->direct_8x8_inference_flag << 0;
374 result.sps_info_flags |= pic->mb_adaptive_frame_field_flag << 1;
375 result.sps_info_flags |= pic->frame_mbs_only_flag << 2;
376 result.sps_info_flags |= pic->delta_pic_order_always_zero_flag << 3;
377
378 result.pps_info_flags = 0;
379 result.pps_info_flags |= pic->transform_8x8_mode_flag << 0;
380 result.pps_info_flags |= pic->redundant_pic_cnt_present_flag << 1;
381 result.pps_info_flags |= pic->constrained_intra_pred_flag << 2;
382 result.pps_info_flags |= pic->deblocking_filter_control_present_flag << 3;
383 result.pps_info_flags |= pic->weighted_bipred_idc << 4;
384 result.pps_info_flags |= pic->weighted_pred_flag << 6;
385 result.pps_info_flags |= pic->pic_order_present_flag << 7;
386 result.pps_info_flags |= pic->entropy_coding_mode_flag << 8;
387
388 result.chroma_format = 0x1;
389 result.bit_depth_luma_minus8 = 0;
390 result.bit_depth_chroma_minus8 = 0;
391
392 result.log2_max_frame_num_minus4 = pic->log2_max_frame_num_minus4;
393 result.pic_order_cnt_type = pic->pic_order_cnt_type;
394 result.log2_max_pic_order_cnt_lsb_minus4 = pic->log2_max_pic_order_cnt_lsb_minus4;
395 result.num_ref_frames = pic->num_ref_frames;
396 result.pic_init_qp_minus26 = pic->pic_init_qp_minus26;
397 result.chroma_qp_index_offset = pic->chroma_qp_index_offset;
398 result.second_chroma_qp_index_offset = pic->second_chroma_qp_index_offset;
399
400 result.num_slice_groups_minus1 = 0;
401 result.slice_group_map_type = 0;
402
403 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
404 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
405
406 result.slice_group_change_rate_minus1 = 0;
407
408 memcpy(result.scaling_list_4x4, pic->scaling_lists_4x4, 6*64);
409 memcpy(result.scaling_list_8x8, pic->scaling_lists_8x8, 2*64);
410
411 result.frame_num = pic->frame_num;
412 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
413 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
414 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
415 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
416
417 result.decoded_pic_idx = pic->frame_num;
418
419 return result;
420 }
421
422 /* get vc1 specific message bits */
423 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
424 {
425 struct ruvd_vc1 result;
426
427 memset(&result, 0, sizeof(result));
428 switch(pic->base.profile) {
429 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
430 result.profile = RUVD_VC1_PROFILE_SIMPLE;
431 break;
432
433 case PIPE_VIDEO_PROFILE_VC1_MAIN:
434 result.profile = RUVD_VC1_PROFILE_MAIN;
435 break;
436
437 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
438 result.profile = RUVD_VC1_PROFILE_ADVANCED;
439 break;
440 default:
441 assert(0);
442 }
443
444 if (pic->base.profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) {
445 result.level = 0;
446
447 result.sps_info_flags |= pic->postprocflag << 7;
448 result.sps_info_flags |= pic->pulldown << 6;
449 result.sps_info_flags |= pic->interlace << 5;
450 result.sps_info_flags |= pic->tfcntrflag << 4;
451 result.sps_info_flags |= pic->psf << 1;
452
453 result.pps_info_flags |= pic->panscan_flag << 7;
454 result.pps_info_flags |= pic->refdist_flag << 6;
455 result.pps_info_flags |= pic->extended_dmv << 8;
456 result.pps_info_flags |= pic->range_mapy_flag << 31;
457 result.pps_info_flags |= pic->range_mapy << 28;
458 result.pps_info_flags |= pic->range_mapuv_flag << 27;
459 result.pps_info_flags |= pic->range_mapuv << 24;
460
461 } else {
462 result.level = 0;
463 result.pps_info_flags |= pic->multires << 21;
464 result.pps_info_flags |= pic->syncmarker << 20;
465 result.pps_info_flags |= pic->rangered << 19;
466 result.pps_info_flags |= pic->maxbframes << 16;
467 }
468
469 result.sps_info_flags |= pic->finterpflag << 3;
470 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
471
472 result.pps_info_flags |= pic->loopfilter << 5;
473 result.pps_info_flags |= pic->fastuvmc << 4;
474 result.pps_info_flags |= pic->extended_mv << 3;
475 result.pps_info_flags |= pic->dquant << 1;
476 result.pps_info_flags |= pic->vstransform << 0;
477 result.pps_info_flags |= pic->overlap << 11;
478 result.pps_info_flags |= pic->quantizer << 9;
479
480
481 #if 0
482 uint32_t slice_count
483 uint8_t picture_type
484 uint8_t frame_coding_mode
485 uint8_t deblockEnable
486 uint8_t pquant
487 #endif
488
489 result.chroma_format = 1;
490 return result;
491 }
492
493 /* extract the frame number from a referenced video buffer */
494 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
495 {
496 uint32_t min = dec->frame_number - NUM_MPEG2_REFS;
497 uint32_t max = dec->frame_number - 1;
498 uintptr_t frame;
499
500 /* seems to be the most sane fallback */
501 if (!ref)
502 return max;
503
504 /* get the frame number from the associated data */
505 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
506
507 /* limit the frame number to a valid range */
508 return MAX2(MIN2(frame, max), min);
509 }
510
511 /* get mpeg2 specific msg bits */
512 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
513 struct pipe_mpeg12_picture_desc *pic)
514 {
515 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
516 struct ruvd_mpeg2 result;
517 unsigned i;
518
519 memset(&result, 0, sizeof(result));
520 result.decoded_pic_idx = dec->frame_number;
521 for (i = 0; i < 2; ++i)
522 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
523
524 result.load_intra_quantiser_matrix = 1;
525 result.load_nonintra_quantiser_matrix = 1;
526
527 for (i = 0; i < 64; ++i) {
528 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
529 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
530 }
531
532 result.profile_and_level_indication = 0;
533 result.chroma_format = 0x1;
534
535 result.picture_coding_type = pic->picture_coding_type;
536 result.f_code[0][0] = pic->f_code[0][0] + 1;
537 result.f_code[0][1] = pic->f_code[0][1] + 1;
538 result.f_code[1][0] = pic->f_code[1][0] + 1;
539 result.f_code[1][1] = pic->f_code[1][1] + 1;
540 result.intra_dc_precision = pic->intra_dc_precision;
541 result.pic_structure = pic->picture_structure;
542 result.top_field_first = pic->top_field_first;
543 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
544 result.concealment_motion_vectors = pic->concealment_motion_vectors;
545 result.q_scale_type = pic->q_scale_type;
546 result.intra_vlc_format = pic->intra_vlc_format;
547 result.alternate_scan = pic->alternate_scan;
548
549 return result;
550 }
551
552 /* get mpeg4 specific msg bits */
553 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
554 struct pipe_mpeg4_picture_desc *pic)
555 {
556 struct ruvd_mpeg4 result;
557 unsigned i;
558
559 memset(&result, 0, sizeof(result));
560 result.decoded_pic_idx = dec->frame_number;
561 for (i = 0; i < 2; ++i)
562 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
563
564 result.variant_type = 0;
565 result.profile_and_level_indication = 0xF0; // ASP Level0
566
567 result.video_object_layer_verid = 0x5; // advanced simple
568 result.video_object_layer_shape = 0x0; // rectangular
569
570 result.video_object_layer_width = dec->base.width;
571 result.video_object_layer_height = dec->base.height;
572
573 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
574
575 result.flags |= pic->short_video_header << 0;
576 //result.flags |= obmc_disable << 1;
577 result.flags |= pic->interlaced << 2;
578 result.flags |= 1 << 3; // load_intra_quant_mat
579 result.flags |= 1 << 4; // load_nonintra_quant_mat
580 result.flags |= pic->quarter_sample << 5;
581 result.flags |= 1 << 6; // complexity_estimation_disable
582 result.flags |= pic->resync_marker_disable << 7;
583 //result.flags |= data_partitioned << 8;
584 //result.flags |= reversible_vlc << 9;
585 result.flags |= 0 << 10; // newpred_enable
586 result.flags |= 0 << 11; // reduced_resolution_vop_enable
587 //result.flags |= scalability << 12;
588 //result.flags |= is_object_layer_identifier << 13;
589 //result.flags |= fixed_vop_rate << 14;
590 //result.flags |= newpred_segment_type << 15;
591
592 result.quant_type = pic->quant_type;
593
594 for (i = 0; i < 64; ++i) {
595 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
596 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
597 }
598
599 /*
600 int32_t trd [2]
601 int32_t trb [2]
602 uint8_t vop_coding_type
603 uint8_t vop_fcode_forward
604 uint8_t vop_fcode_backward
605 uint8_t rounding_control
606 uint8_t alternate_vertical_scan_flag
607 uint8_t top_field_first
608 */
609
610 return result;
611 }
612
613 /**
614 * destroy this video decoder
615 */
616 static void ruvd_destroy(struct pipe_video_codec *decoder)
617 {
618 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
619 struct ruvd_msg msg;
620 unsigned i;
621
622 assert(decoder);
623
624 memset(&msg, 0, sizeof(msg));
625 msg.size = sizeof(msg);
626 msg.msg_type = RUVD_MSG_DESTROY;
627 msg.stream_handle = dec->stream_handle;
628 send_msg(dec, &msg);
629
630 flush(dec);
631
632 dec->ws->cs_destroy(dec->cs);
633
634 for (i = 0; i < NUM_BUFFERS; ++i) {
635 destroy_buffer(&dec->msg_fb_buffers[i]);
636 destroy_buffer(&dec->bs_buffers[i]);
637 }
638
639 destroy_buffer(&dec->dpb);
640
641 FREE(dec);
642 }
643
644 /* free associated data in the video buffer callback */
645 static void ruvd_destroy_associated_data(void *data)
646 {
647 /* NOOP, since we only use an intptr */
648 }
649
650 /**
651 * start decoding of a new frame
652 */
653 static void ruvd_begin_frame(struct pipe_video_codec *decoder,
654 struct pipe_video_buffer *target,
655 struct pipe_picture_desc *picture)
656 {
657 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
658 uintptr_t frame;
659
660 assert(decoder);
661
662 frame = ++dec->frame_number;
663 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
664 &ruvd_destroy_associated_data);
665
666 dec->bs_size = 0;
667 dec->bs_ptr = dec->ws->buffer_map(
668 dec->bs_buffers[dec->cur_buffer].cs_handle,
669 dec->cs, PIPE_TRANSFER_WRITE);
670 }
671
672 /**
673 * decode a macroblock
674 */
675 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
676 struct pipe_video_buffer *target,
677 struct pipe_picture_desc *picture,
678 const struct pipe_macroblock *macroblocks,
679 unsigned num_macroblocks)
680 {
681 /* not supported (yet) */
682 assert(0);
683 }
684
685 /**
686 * decode a bitstream
687 */
688 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
689 struct pipe_video_buffer *target,
690 struct pipe_picture_desc *picture,
691 unsigned num_buffers,
692 const void * const *buffers,
693 const unsigned *sizes)
694 {
695 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
696 unsigned i;
697
698 assert(decoder);
699
700 if (!dec->bs_ptr)
701 return;
702
703 for (i = 0; i < num_buffers; ++i) {
704 struct ruvd_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
705 unsigned new_size = dec->bs_size + sizes[i];
706
707 if (new_size > buf->buf->size) {
708 dec->ws->buffer_unmap(buf->cs_handle);
709 if (!resize_buffer(dec, buf, new_size)) {
710 RUVD_ERR("Can't resize bitstream buffer!");
711 return;
712 }
713
714 dec->bs_ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs,
715 PIPE_TRANSFER_WRITE);
716 if (!dec->bs_ptr)
717 return;
718
719 dec->bs_ptr += dec->bs_size;
720 }
721
722 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
723 dec->bs_size += sizes[i];
724 dec->bs_ptr += sizes[i];
725 }
726 }
727
728 /**
729 * end decoding of the current frame
730 */
731 static void ruvd_end_frame(struct pipe_video_codec *decoder,
732 struct pipe_video_buffer *target,
733 struct pipe_picture_desc *picture)
734 {
735 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
736 struct radeon_winsys_cs_handle *dt;
737 struct ruvd_buffer *msg_fb_buf, *bs_buf;
738 struct ruvd_msg msg;
739 unsigned bs_size;
740
741 assert(decoder);
742
743 if (!dec->bs_ptr)
744 return;
745
746 msg_fb_buf = &dec->msg_fb_buffers[dec->cur_buffer];
747 bs_buf = &dec->bs_buffers[dec->cur_buffer];
748
749 bs_size = align(dec->bs_size, 128);
750 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
751 dec->ws->buffer_unmap(bs_buf->cs_handle);
752
753 memset(&msg, 0, sizeof(msg));
754 msg.size = sizeof(msg);
755 msg.msg_type = RUVD_MSG_DECODE;
756 msg.stream_handle = dec->stream_handle;
757 msg.status_report_feedback_number = dec->frame_number;
758
759 msg.body.decode.stream_type = profile2stream_type(dec->base.profile);
760 msg.body.decode.decode_flags = 0x1;
761 msg.body.decode.width_in_samples = dec->base.width;
762 msg.body.decode.height_in_samples = dec->base.height;
763
764 msg.body.decode.dpb_size = dec->dpb.buf->size;
765 msg.body.decode.bsd_size = bs_size;
766
767 dt = dec->set_dtb(&msg, (struct vl_video_buffer *)target);
768
769 switch (u_reduce_video_profile(picture->profile)) {
770 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
771 msg.body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
772 break;
773
774 case PIPE_VIDEO_FORMAT_VC1:
775 msg.body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
776 break;
777
778 case PIPE_VIDEO_FORMAT_MPEG12:
779 msg.body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
780 break;
781
782 case PIPE_VIDEO_FORMAT_MPEG4:
783 msg.body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
784 break;
785
786 default:
787 assert(0);
788 return;
789 }
790
791 msg.body.decode.db_surf_tile_config = msg.body.decode.dt_surf_tile_config;
792 msg.body.decode.extension_support = 0x1;
793
794 send_msg(dec, &msg);
795 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.cs_handle, 0,
796 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
797 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->cs_handle,
798 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
799 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
800 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
801 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf->cs_handle,
802 0x1000, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
803 set_reg(dec, RUVD_ENGINE_CNTL, 1);
804
805 flush(dec);
806 next_buffer(dec);
807 }
808
809 /**
810 * flush any outstanding command buffers to the hardware
811 */
812 static void ruvd_flush(struct pipe_video_codec *decoder)
813 {
814 }
815
816 /**
817 * create and UVD decoder
818 */
819 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
820 const struct pipe_video_codec *templ,
821 struct radeon_winsys* ws,
822 ruvd_set_dtb set_dtb)
823 {
824 unsigned dpb_size = calc_dpb_size(templ);
825 unsigned width = templ->width, height = templ->height;
826 struct radeon_info info;
827 struct ruvd_decoder *dec;
828 struct ruvd_msg msg;
829 int i;
830
831 ws->query_info(ws, &info);
832
833 switch(u_reduce_video_profile(templ->profile)) {
834 case PIPE_VIDEO_FORMAT_MPEG12:
835 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
836 return vl_create_mpeg12_decoder(context, templ);
837
838 /* fall through */
839 case PIPE_VIDEO_FORMAT_MPEG4:
840 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
841 width = align(width, VL_MACROBLOCK_WIDTH);
842 height = align(height, VL_MACROBLOCK_HEIGHT);
843 break;
844
845 default:
846 break;
847 }
848
849
850 dec = CALLOC_STRUCT(ruvd_decoder);
851
852 if (!dec)
853 return NULL;
854
855 dec->base = *templ;
856 dec->base.context = context;
857
858 dec->base.destroy = ruvd_destroy;
859 dec->base.begin_frame = ruvd_begin_frame;
860 dec->base.decode_macroblock = ruvd_decode_macroblock;
861 dec->base.decode_bitstream = ruvd_decode_bitstream;
862 dec->base.end_frame = ruvd_end_frame;
863 dec->base.flush = ruvd_flush;
864
865 dec->set_dtb = set_dtb;
866 dec->stream_handle = alloc_stream_handle();
867 dec->ws = ws;
868 dec->cs = ws->cs_create(ws, RING_UVD, NULL);
869 if (!dec->cs) {
870 RUVD_ERR("Can't get command submission context.\n");
871 goto error;
872 }
873
874 for (i = 0; i < NUM_BUFFERS; ++i) {
875 unsigned msg_fb_size = align(sizeof(struct ruvd_msg), 0x1000) + 0x1000;
876 if (!create_buffer(dec, &dec->msg_fb_buffers[i], msg_fb_size)) {
877 RUVD_ERR("Can't allocated message buffers.\n");
878 goto error;
879 }
880
881 if (!create_buffer(dec, &dec->bs_buffers[i], 4096)) {
882 RUVD_ERR("Can't allocated bitstream buffers.\n");
883 goto error;
884 }
885
886 clear_buffer(dec, &dec->msg_fb_buffers[i]);
887 clear_buffer(dec, &dec->bs_buffers[i]);
888 }
889
890 if (!create_buffer(dec, &dec->dpb, dpb_size)) {
891 RUVD_ERR("Can't allocated dpb.\n");
892 goto error;
893 }
894
895 clear_buffer(dec, &dec->dpb);
896
897 memset(&msg, 0, sizeof(msg));
898 msg.size = sizeof(msg);
899 msg.msg_type = RUVD_MSG_CREATE;
900 msg.stream_handle = dec->stream_handle;
901 msg.body.create.stream_type = profile2stream_type(dec->base.profile);
902 msg.body.create.width_in_samples = dec->base.width;
903 msg.body.create.height_in_samples = dec->base.height;
904 msg.body.create.dpb_size = dec->dpb.buf->size;
905 send_msg(dec, &msg);
906 flush(dec);
907 next_buffer(dec);
908
909 return &dec->base;
910
911 error:
912 if (dec->cs) dec->ws->cs_destroy(dec->cs);
913
914 for (i = 0; i < NUM_BUFFERS; ++i) {
915 destroy_buffer(&dec->msg_fb_buffers[i]);
916 destroy_buffer(&dec->bs_buffers[i]);
917 }
918
919 destroy_buffer(&dec->dpb);
920
921 FREE(dec);
922
923 return NULL;
924 }
925
926 /**
927 * join surfaces into the same buffer with identical tiling params
928 * sumup their sizes and replace the backend buffers with a single bo
929 */
930 void ruvd_join_surfaces(struct radeon_winsys* ws, unsigned bind,
931 struct pb_buffer** buffers[VL_NUM_COMPONENTS],
932 struct radeon_surface *surfaces[VL_NUM_COMPONENTS])
933 {
934 unsigned best_tiling, best_wh, off;
935 unsigned size, alignment;
936 struct pb_buffer *pb;
937 unsigned i, j;
938
939 for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
940 unsigned wh;
941
942 if (!surfaces[i])
943 continue;
944
945 /* choose the smallest bank w/h for now */
946 wh = surfaces[i]->bankw * surfaces[i]->bankh;
947 if (wh < best_wh) {
948 best_wh = wh;
949 best_tiling = i;
950 }
951 }
952
953 for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
954 if (!surfaces[i])
955 continue;
956
957 /* copy the tiling parameters */
958 surfaces[i]->bankw = surfaces[best_tiling]->bankw;
959 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
960 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
961 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
962
963 /* adjust the texture layer offsets */
964 off = align(off, surfaces[i]->bo_alignment);
965 for (j = 0; j < Elements(surfaces[i]->level); ++j)
966 surfaces[i]->level[j].offset += off;
967 off += surfaces[i]->bo_size;
968 }
969
970 for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
971 if (!buffers[i] || !*buffers[i])
972 continue;
973
974 size = align(size, (*buffers[i])->alignment);
975 size += (*buffers[i])->size;
976 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
977 }
978
979 if (!size)
980 return;
981
982 /* TODO: 2D tiling workaround */
983 alignment *= 2;
984
985 pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM);
986 if (!pb)
987 return;
988
989 for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
990 if (!buffers[i] || !*buffers[i])
991 continue;
992
993 pb_reference(buffers[i], pb);
994 }
995
996 pb_reference(&pb, NULL);
997 }
998
999 /* calculate top/bottom offset */
1000 static unsigned texture_offset(struct radeon_surface *surface, unsigned layer)
1001 {
1002 return surface->level[0].offset +
1003 layer * surface->level[0].slice_size;
1004 }
1005
1006 /* hw encode the aspect of macro tiles */
1007 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1008 {
1009 switch (macro_tile_aspect) {
1010 default:
1011 case 1: macro_tile_aspect = 0; break;
1012 case 2: macro_tile_aspect = 1; break;
1013 case 4: macro_tile_aspect = 2; break;
1014 case 8: macro_tile_aspect = 3; break;
1015 }
1016 return macro_tile_aspect;
1017 }
1018
1019 /* hw encode the bank width and height */
1020 static unsigned bank_wh(unsigned bankwh)
1021 {
1022 switch (bankwh) {
1023 default:
1024 case 1: bankwh = 0; break;
1025 case 2: bankwh = 1; break;
1026 case 4: bankwh = 2; break;
1027 case 8: bankwh = 3; break;
1028 }
1029 return bankwh;
1030 }
1031
1032 /**
1033 * fill decoding target field from the luma and chroma surfaces
1034 */
1035 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma,
1036 struct radeon_surface *chroma)
1037 {
1038 msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
1039 switch (luma->level[0].mode) {
1040 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1041 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1042 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1043 break;
1044 case RADEON_SURF_MODE_1D:
1045 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1046 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1047 break;
1048 case RADEON_SURF_MODE_2D:
1049 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1050 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1051 break;
1052 default:
1053 assert(0);
1054 break;
1055 }
1056
1057 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
1058 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
1059 if (msg->body.decode.dt_field_mode) {
1060 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
1061 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
1062 } else {
1063 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1064 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1065 }
1066
1067 assert(luma->bankw == chroma->bankw);
1068 assert(luma->bankh == chroma->bankh);
1069 assert(luma->mtilea == chroma->mtilea);
1070
1071 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
1072 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
1073 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
1074 }
1075
1076 int ruvd_get_video_param(struct pipe_screen *screen,
1077 enum pipe_video_profile profile,
1078 enum pipe_video_entrypoint entrypoint,
1079 enum pipe_video_cap param)
1080 {
1081 switch (param) {
1082 case PIPE_VIDEO_CAP_SUPPORTED:
1083 switch (u_reduce_video_profile(profile)) {
1084 case PIPE_VIDEO_FORMAT_MPEG12:
1085 case PIPE_VIDEO_FORMAT_MPEG4:
1086 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1087 case PIPE_VIDEO_FORMAT_VC1:
1088 return true;
1089 default:
1090 return false;
1091 }
1092 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
1093 return 1;
1094 case PIPE_VIDEO_CAP_MAX_WIDTH:
1095 return 2048;
1096 case PIPE_VIDEO_CAP_MAX_HEIGHT:
1097 return 1152;
1098 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
1099 return PIPE_FORMAT_NV12;
1100 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
1101 return true;
1102 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
1103 return true;
1104 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
1105 return true;
1106 case PIPE_VIDEO_CAP_MAX_LEVEL:
1107 switch (profile) {
1108 case PIPE_VIDEO_PROFILE_MPEG1:
1109 return 0;
1110 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
1111 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
1112 return 3;
1113 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
1114 return 3;
1115 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
1116 return 5;
1117 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
1118 return 1;
1119 case PIPE_VIDEO_PROFILE_VC1_MAIN:
1120 return 2;
1121 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
1122 return 4;
1123 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
1124 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
1125 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
1126 return 41;
1127 default:
1128 return 0;
1129 }
1130 default:
1131 return 0;
1132 }
1133 }
1134
1135 boolean ruvd_is_format_supported(struct pipe_screen *screen,
1136 enum pipe_format format,
1137 enum pipe_video_profile profile,
1138 enum pipe_video_entrypoint entrypoint)
1139 {
1140 /* we can only handle this one anyway */
1141 return format == PIPE_FORMAT_NV12;
1142 }