projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
[mesa.git] / src / gallium / drivers / radeon / radeon_uvd.c
1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <sys/types.h>
35 #include <assert.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <stdio.h>
39
40 #include "pipe/p_video_codec.h"
41
42 #include "util/u_memory.h"
43 #include "util/u_video.h"
44
45 #include "vl/vl_defines.h"
46 #include "vl/vl_mpeg12_decoder.h"
47
48 #include "r600_pipe_common.h"
49 #include "radeon_video.h"
50 #include "radeon_uvd.h"
51
52 #define NUM_BUFFERS 4
53
54 #define NUM_MPEG2_REFS 6
55 #define NUM_H264_REFS 17
56 #define NUM_VC1_REFS 5
57
58 #define FB_BUFFER_OFFSET 0x1000
59 #define FB_BUFFER_SIZE 2048
60 #define FB_BUFFER_SIZE_TONGA (2048 * 64)
61 #define IT_SCALING_TABLE_SIZE 992
62 #define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
63
64 /* UVD decoder representation */
65 struct ruvd_decoder {
66 struct pipe_video_codec base;
67
68 ruvd_set_dtb set_dtb;
69
70 unsigned stream_handle;
71 unsigned stream_type;
72 unsigned frame_number;
73
74 struct pipe_screen *screen;
75 struct radeon_winsys* ws;
76 struct radeon_winsys_cs* cs;
77
78 unsigned cur_buffer;
79
80 struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
81 struct ruvd_msg *msg;
82 uint32_t *fb;
83 unsigned fb_size;
84 uint8_t *it;
85
86 struct rvid_buffer bs_buffers[NUM_BUFFERS];
87 void* bs_ptr;
88 unsigned bs_size;
89
90 struct rvid_buffer dpb;
91 bool use_legacy;
92 struct rvid_buffer ctx;
93 struct rvid_buffer sessionctx;
94 };
95
96 /* flush IB to the hardware */
97 static int flush(struct ruvd_decoder *dec, unsigned flags)
98 {
99 return dec->ws->cs_flush(dec->cs, flags, NULL);
100 }
101
102 /* add a new set register command to the IB */
103 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
104 {
105 radeon_emit(dec->cs, RUVD_PKT0(reg >> 2, 0));
106 radeon_emit(dec->cs, val);
107 }
108
109 /* send a command to the VCPU through the GPCOM registers */
110 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
111 struct pb_buffer* buf, uint32_t off,
112 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
113 {
114 int reloc_idx;
115
116 reloc_idx = dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
117 domain,
118 RADEON_PRIO_UVD);
119 if (!dec->use_legacy) {
120 uint64_t addr;
121 addr = dec->ws->buffer_get_virtual_address(buf);
122 addr = addr + off;
123 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
124 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
125 } else {
126 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
127 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
128 }
129 set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
130 }
131
132 /* do the codec needs an IT buffer ?*/
133 static bool have_it(struct ruvd_decoder *dec)
134 {
135 return dec->stream_type == RUVD_CODEC_H264_PERF ||
136 dec->stream_type == RUVD_CODEC_H265;
137 }
138
139 /* map the next available message/feedback/itscaling buffer */
140 static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
141 {
142 struct rvid_buffer* buf;
143 uint8_t *ptr;
144
145 /* grab the current message/feedback buffer */
146 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
147
148 /* and map it for CPU access */
149 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
150
151 /* calc buffer offsets */
152 dec->msg = (struct ruvd_msg *)ptr;
153 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
154 if (have_it(dec))
155 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
156 }
157
158 /* unmap and send a message command to the VCPU */
159 static void send_msg_buf(struct ruvd_decoder *dec)
160 {
161 struct rvid_buffer* buf;
162
163 /* ignore the request if message/feedback buffer isn't mapped */
164 if (!dec->msg || !dec->fb)
165 return;
166
167 /* grab the current message buffer */
168 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
169
170 /* unmap the buffer */
171 dec->ws->buffer_unmap(buf->res->buf);
172 dec->msg = NULL;
173 dec->fb = NULL;
174 dec->it = NULL;
175
176
177 if (dec->sessionctx.res)
178 send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER,
179 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
180 RADEON_DOMAIN_VRAM);
181
182 /* and send it to the hardware */
183 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0,
184 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
185 }
186
187 /* cycle to the next set of buffers */
188 static void next_buffer(struct ruvd_decoder *dec)
189 {
190 ++dec->cur_buffer;
191 dec->cur_buffer %= NUM_BUFFERS;
192 }
193
194 /* convert the profile into something UVD understands */
195 static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
196 {
197 switch (u_reduce_video_profile(dec->base.profile)) {
198 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
199 return (family >= CHIP_TONGA) ?
200 RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
201
202 case PIPE_VIDEO_FORMAT_VC1:
203 return RUVD_CODEC_VC1;
204
205 case PIPE_VIDEO_FORMAT_MPEG12:
206 return RUVD_CODEC_MPEG2;
207
208 case PIPE_VIDEO_FORMAT_MPEG4:
209 return RUVD_CODEC_MPEG4;
210
211 case PIPE_VIDEO_FORMAT_HEVC:
212 return RUVD_CODEC_H265;
213
214 default:
215 assert(0);
216 return 0;
217 }
218 }
219
220 static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
221 {
222 unsigned width_in_mb, height_in_mb, ctx_size;
223 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
224 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
225
226 unsigned max_references = dec->base.max_references + 1;
227
228 // picture width & height in 16 pixel units
229 width_in_mb = width / VL_MACROBLOCK_WIDTH;
230 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
231
232 if (!dec->use_legacy) {
233 unsigned fs_in_mb = width_in_mb * height_in_mb;
234 unsigned num_dpb_buffer;
235 switch(dec->base.level) {
236 case 30:
237 num_dpb_buffer = 8100 / fs_in_mb;
238 break;
239 case 31:
240 num_dpb_buffer = 18000 / fs_in_mb;
241 break;
242 case 32:
243 num_dpb_buffer = 20480 / fs_in_mb;
244 break;
245 case 41:
246 num_dpb_buffer = 32768 / fs_in_mb;
247 break;
248 case 42:
249 num_dpb_buffer = 34816 / fs_in_mb;
250 break;
251 case 50:
252 num_dpb_buffer = 110400 / fs_in_mb;
253 break;
254 case 51:
255 num_dpb_buffer = 184320 / fs_in_mb;
256 break;
257 default:
258 num_dpb_buffer = 184320 / fs_in_mb;
259 break;
260 }
261 num_dpb_buffer++;
262 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
263 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
264 } else {
265 // the firmware seems to always assume a minimum of ref frames
266 max_references = MAX2(NUM_H264_REFS, max_references);
267 // macroblock context buffer
268 ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
269 }
270
271 return ctx_size;
272 }
273
274 static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
275 {
276 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
277 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
278
279 unsigned max_references = dec->base.max_references + 1;
280
281 if (dec->base.width * dec->base.height >= 4096*2000)
282 max_references = MAX2(max_references, 8);
283 else
284 max_references = MAX2(max_references, 17);
285
286 width = align (width, 16);
287 height = align (height, 16);
288 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
289 }
290
291 static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec, struct pipe_h265_picture_desc *pic)
292 {
293 unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
294 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
295 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
296
297 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
298 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
299 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
300
301 unsigned max_references = dec->base.max_references + 1;
302
303 if (dec->base.width * dec->base.height >= 4096*2000)
304 max_references = MAX2(max_references, 8);
305 else
306 max_references = MAX2(max_references, 17);
307
308 block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
309 log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
310
311 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
312 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
313
314 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
315 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
316 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
317
318 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
319 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
320
321 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
322 }
323
324 /* calculate size of reference picture buffer */
325 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
326 {
327 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
328
329 // always align them to MB size for dpb calculation
330 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
331 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
332
333 // always one more for currently decoded picture
334 unsigned max_references = dec->base.max_references + 1;
335
336 // aligned size of a single frame
337 image_size = width * height;
338 image_size += image_size / 2;
339 image_size = align(image_size, 1024);
340
341 // picture width & height in 16 pixel units
342 width_in_mb = width / VL_MACROBLOCK_WIDTH;
343 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
344
345 switch (u_reduce_video_profile(dec->base.profile)) {
346 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
347 if (!dec->use_legacy) {
348 unsigned fs_in_mb = width_in_mb * height_in_mb;
349 unsigned alignment = 64, num_dpb_buffer;
350
351 if (dec->stream_type == RUVD_CODEC_H264_PERF)
352 alignment = 256;
353 switch(dec->base.level) {
354 case 30:
355 num_dpb_buffer = 8100 / fs_in_mb;
356 break;
357 case 31:
358 num_dpb_buffer = 18000 / fs_in_mb;
359 break;
360 case 32:
361 num_dpb_buffer = 20480 / fs_in_mb;
362 break;
363 case 41:
364 num_dpb_buffer = 32768 / fs_in_mb;
365 break;
366 case 42:
367 num_dpb_buffer = 34816 / fs_in_mb;
368 break;
369 case 50:
370 num_dpb_buffer = 110400 / fs_in_mb;
371 break;
372 case 51:
373 num_dpb_buffer = 184320 / fs_in_mb;
374 break;
375 default:
376 num_dpb_buffer = 184320 / fs_in_mb;
377 break;
378 }
379 num_dpb_buffer++;
380 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
381 dpb_size = image_size * max_references;
382 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
383 (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
384 dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
385 dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
386 }
387 } else {
388 // the firmware seems to allways assume a minimum of ref frames
389 max_references = MAX2(NUM_H264_REFS, max_references);
390 // reference picture buffer
391 dpb_size = image_size * max_references;
392 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
393 (((struct r600_common_screen*)dec->screen)->family < CHIP_POLARIS10)) {
394 // macroblock context buffer
395 dpb_size += width_in_mb * height_in_mb * max_references * 192;
396 // IT surface buffer
397 dpb_size += width_in_mb * height_in_mb * 32;
398 }
399 }
400 break;
401 }
402
403 case PIPE_VIDEO_FORMAT_HEVC:
404 if (dec->base.width * dec->base.height >= 4096*2000)
405 max_references = MAX2(max_references, 8);
406 else
407 max_references = MAX2(max_references, 17);
408
409 width = align (width, 16);
410 height = align (height, 16);
411 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
412 dpb_size = align((width * height * 9) / 4, 256) * max_references;
413 else
414 dpb_size = align((width * height * 3) / 2, 256) * max_references;
415 break;
416
417 case PIPE_VIDEO_FORMAT_VC1:
418 // the firmware seems to allways assume a minimum of ref frames
419 max_references = MAX2(NUM_VC1_REFS, max_references);
420
421 // reference picture buffer
422 dpb_size = image_size * max_references;
423
424 // CONTEXT_BUFFER
425 dpb_size += width_in_mb * height_in_mb * 128;
426
427 // IT surface buffer
428 dpb_size += width_in_mb * 64;
429
430 // DB surface buffer
431 dpb_size += width_in_mb * 128;
432
433 // BP
434 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
435 break;
436
437 case PIPE_VIDEO_FORMAT_MPEG12:
438 // reference picture buffer, must be big enough for all frames
439 dpb_size = image_size * NUM_MPEG2_REFS;
440 break;
441
442 case PIPE_VIDEO_FORMAT_MPEG4:
443 // reference picture buffer
444 dpb_size = image_size * max_references;
445
446 // CM
447 dpb_size += width_in_mb * height_in_mb * 64;
448
449 // IT surface buffer
450 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
451
452 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
453 break;
454
455 default:
456 // something is missing here
457 assert(0);
458
459 // at least use a sane default value
460 dpb_size = 32 * 1024 * 1024;
461 break;
462 }
463 return dpb_size;
464 }
465
466 /* free associated data in the video buffer callback */
467 static void ruvd_destroy_associated_data(void *data)
468 {
469 /* NOOP, since we only use an intptr */
470 }
471
472 /* get h264 specific message bits */
473 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
474 {
475 struct ruvd_h264 result;
476
477 memset(&result, 0, sizeof(result));
478 switch (pic->base.profile) {
479 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
480 result.profile = RUVD_H264_PROFILE_BASELINE;
481 break;
482
483 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
484 result.profile = RUVD_H264_PROFILE_MAIN;
485 break;
486
487 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
488 result.profile = RUVD_H264_PROFILE_HIGH;
489 break;
490
491 default:
492 assert(0);
493 break;
494 }
495
496 result.level = dec->base.level;
497
498 result.sps_info_flags = 0;
499 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
500 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
501 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
502 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
503
504 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
505 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
506 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
507 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
508 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
509
510 switch (dec->base.chroma_format) {
511 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
512 /* TODO: assert? */
513 break;
514 case PIPE_VIDEO_CHROMA_FORMAT_400:
515 result.chroma_format = 0;
516 break;
517 case PIPE_VIDEO_CHROMA_FORMAT_420:
518 result.chroma_format = 1;
519 break;
520 case PIPE_VIDEO_CHROMA_FORMAT_422:
521 result.chroma_format = 2;
522 break;
523 case PIPE_VIDEO_CHROMA_FORMAT_444:
524 result.chroma_format = 3;
525 break;
526 }
527
528 result.pps_info_flags = 0;
529 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
530 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
531 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
532 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
533 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
534 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
535 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
536 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
537
538 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
539 result.slice_group_map_type = pic->pps->slice_group_map_type;
540 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
541 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
542 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
543 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
544
545 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
546 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
547
548 if (dec->stream_type == RUVD_CODEC_H264_PERF) {
549 memcpy(dec->it, result.scaling_list_4x4, 6*16);
550 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
551 }
552
553 result.num_ref_frames = pic->num_ref_frames;
554
555 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
556 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
557
558 result.frame_num = pic->frame_num;
559 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
560 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
561 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
562 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
563
564 result.decoded_pic_idx = pic->frame_num;
565
566 return result;
567 }
568
569 /* get h265 specific message bits */
570 static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video_buffer *target,
571 struct pipe_h265_picture_desc *pic)
572 {
573 struct ruvd_h265 result;
574 unsigned i;
575
576 memset(&result, 0, sizeof(result));
577
578 result.sps_info_flags = 0;
579 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
580 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
581 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
582 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
583 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
584 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
585 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
586 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
587 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
588 if (((struct r600_common_screen*)dec->screen)->family == CHIP_CARRIZO)
589 result.sps_info_flags |= 1 << 9;
590 if (pic->UseRefPicList == true)
591 result.sps_info_flags |= 1 << 10;
592
593 result.chroma_format = pic->pps->sps->chroma_format_idc;
594 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
595 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
596 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
597 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
598 result.log2_min_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_luma_coding_block_size_minus3;
599 result.log2_diff_max_min_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
600 result.log2_min_transform_block_size_minus2 = pic->pps->sps->log2_min_transform_block_size_minus2;
601 result.log2_diff_max_min_transform_block_size = pic->pps->sps->log2_diff_max_min_transform_block_size;
602 result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
603 result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
604 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
605 result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
606 result.log2_min_pcm_luma_coding_block_size_minus3 = pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
607 result.log2_diff_max_min_pcm_luma_coding_block_size = pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
608 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
609
610 result.pps_info_flags = 0;
611 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
612 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
613 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
614 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
615 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
616 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
617 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
618 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
619 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
620 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
621 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
622 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
623 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
624 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
625 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
626 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
627 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
628 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
629 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
630 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
631 //result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag; ???
632
633 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
634 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
635 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
636 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
637 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
638 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
639 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
640 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
641 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
642 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
643 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
644 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
645 result.init_qp_minus26 = pic->pps->init_qp_minus26;
646
647 for (i = 0; i < 19; ++i)
648 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
649
650 for (i = 0; i < 21; ++i)
651 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
652
653 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
654 result.curr_idx = pic->CurrPicOrderCntVal;
655 result.curr_poc = pic->CurrPicOrderCntVal;
656
657 vl_video_buffer_set_associated_data(target, &dec->base,
658 (void *)(uintptr_t)pic->CurrPicOrderCntVal,
659 &ruvd_destroy_associated_data);
660
661 for (i = 0; i < 16; ++i) {
662 struct pipe_video_buffer *ref = pic->ref[i];
663 uintptr_t ref_pic = 0;
664
665 result.poc_list[i] = pic->PicOrderCntVal[i];
666
667 if (ref)
668 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
669 else
670 ref_pic = 0x7F;
671 result.ref_pic_list[i] = ref_pic;
672 }
673
674 for (i = 0; i < 8; ++i) {
675 result.ref_pic_set_st_curr_before[i] = 0xFF;
676 result.ref_pic_set_st_curr_after[i] = 0xFF;
677 result.ref_pic_set_lt_curr[i] = 0xFF;
678 }
679
680 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
681 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
682
683 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
684 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
685
686 for (i = 0; i < pic->NumPocLtCurr; ++i)
687 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
688
689 for (i = 0; i < 6; ++i)
690 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
691
692 for (i = 0; i < 2; ++i)
693 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
694
695 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
696 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
697 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
698 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
699
700 for (i = 0 ; i < 2 ; i++) {
701 for (int j = 0 ; j < 15 ; j++)
702 result.direct_reflist[i][j] = pic->RefPicList[i][j];
703 }
704
705 if ((pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) &&
706 (target->buffer_format == PIPE_FORMAT_NV12)) {
707 result.p010_mode = 0;
708 result.luma_10to8 = 5;
709 result.chroma_10to8 = 5;
710 result.sclr_luma10to8 = 4;
711 result.sclr_chroma10to8 = 4;
712 }
713
714 /* TODO
715 result.highestTid;
716 result.isNonRef;
717
718 IDRPicFlag;
719 RAPPicFlag;
720 NumPocTotalCurr;
721 NumShortTermPictureSliceHeaderBits;
722 NumLongTermPictureSliceHeaderBits;
723
724 IsLongTerm[16];
725 */
726
727 return result;
728 }
729
730 /* get vc1 specific message bits */
731 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
732 {
733 struct ruvd_vc1 result;
734
735 memset(&result, 0, sizeof(result));
736
737 switch(pic->base.profile) {
738 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
739 result.profile = RUVD_VC1_PROFILE_SIMPLE;
740 result.level = 1;
741 break;
742
743 case PIPE_VIDEO_PROFILE_VC1_MAIN:
744 result.profile = RUVD_VC1_PROFILE_MAIN;
745 result.level = 2;
746 break;
747
748 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
749 result.profile = RUVD_VC1_PROFILE_ADVANCED;
750 result.level = 4;
751 break;
752
753 default:
754 assert(0);
755 }
756
757 /* fields common for all profiles */
758 result.sps_info_flags |= pic->postprocflag << 7;
759 result.sps_info_flags |= pic->pulldown << 6;
760 result.sps_info_flags |= pic->interlace << 5;
761 result.sps_info_flags |= pic->tfcntrflag << 4;
762 result.sps_info_flags |= pic->finterpflag << 3;
763 result.sps_info_flags |= pic->psf << 1;
764
765 result.pps_info_flags |= pic->range_mapy_flag << 31;
766 result.pps_info_flags |= pic->range_mapy << 28;
767 result.pps_info_flags |= pic->range_mapuv_flag << 27;
768 result.pps_info_flags |= pic->range_mapuv << 24;
769 result.pps_info_flags |= pic->multires << 21;
770 result.pps_info_flags |= pic->maxbframes << 16;
771 result.pps_info_flags |= pic->overlap << 11;
772 result.pps_info_flags |= pic->quantizer << 9;
773 result.pps_info_flags |= pic->panscan_flag << 7;
774 result.pps_info_flags |= pic->refdist_flag << 6;
775 result.pps_info_flags |= pic->vstransform << 0;
776
777 /* some fields only apply to main/advanced profile */
778 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
779 result.pps_info_flags |= pic->syncmarker << 20;
780 result.pps_info_flags |= pic->rangered << 19;
781 result.pps_info_flags |= pic->loopfilter << 5;
782 result.pps_info_flags |= pic->fastuvmc << 4;
783 result.pps_info_flags |= pic->extended_mv << 3;
784 result.pps_info_flags |= pic->extended_dmv << 8;
785 result.pps_info_flags |= pic->dquant << 1;
786 }
787
788 result.chroma_format = 1;
789
790 #if 0
791 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
792 uint32_t slice_count
793 uint8_t picture_type
794 uint8_t frame_coding_mode
795 uint8_t deblockEnable
796 uint8_t pquant
797 #endif
798
799 return result;
800 }
801
802 /* extract the frame number from a referenced video buffer */
803 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
804 {
805 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
806 uint32_t max = MAX2(dec->frame_number, 1) - 1;
807 uintptr_t frame;
808
809 /* seems to be the most sane fallback */
810 if (!ref)
811 return max;
812
813 /* get the frame number from the associated data */
814 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
815
816 /* limit the frame number to a valid range */
817 return MAX2(MIN2(frame, max), min);
818 }
819
820 /* get mpeg2 specific msg bits */
821 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
822 struct pipe_mpeg12_picture_desc *pic)
823 {
824 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
825 struct ruvd_mpeg2 result;
826 unsigned i;
827
828 memset(&result, 0, sizeof(result));
829 result.decoded_pic_idx = dec->frame_number;
830 for (i = 0; i < 2; ++i)
831 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
832
833 result.load_intra_quantiser_matrix = 1;
834 result.load_nonintra_quantiser_matrix = 1;
835
836 for (i = 0; i < 64; ++i) {
837 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
838 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
839 }
840
841 result.profile_and_level_indication = 0;
842 result.chroma_format = 0x1;
843
844 result.picture_coding_type = pic->picture_coding_type;
845 result.f_code[0][0] = pic->f_code[0][0] + 1;
846 result.f_code[0][1] = pic->f_code[0][1] + 1;
847 result.f_code[1][0] = pic->f_code[1][0] + 1;
848 result.f_code[1][1] = pic->f_code[1][1] + 1;
849 result.intra_dc_precision = pic->intra_dc_precision;
850 result.pic_structure = pic->picture_structure;
851 result.top_field_first = pic->top_field_first;
852 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
853 result.concealment_motion_vectors = pic->concealment_motion_vectors;
854 result.q_scale_type = pic->q_scale_type;
855 result.intra_vlc_format = pic->intra_vlc_format;
856 result.alternate_scan = pic->alternate_scan;
857
858 return result;
859 }
860
861 /* get mpeg4 specific msg bits */
862 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
863 struct pipe_mpeg4_picture_desc *pic)
864 {
865 struct ruvd_mpeg4 result;
866 unsigned i;
867
868 memset(&result, 0, sizeof(result));
869 result.decoded_pic_idx = dec->frame_number;
870 for (i = 0; i < 2; ++i)
871 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
872
873 result.variant_type = 0;
874 result.profile_and_level_indication = 0xF0; // ASP Level0
875
876 result.video_object_layer_verid = 0x5; // advanced simple
877 result.video_object_layer_shape = 0x0; // rectangular
878
879 result.video_object_layer_width = dec->base.width;
880 result.video_object_layer_height = dec->base.height;
881
882 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
883
884 result.flags |= pic->short_video_header << 0;
885 //result.flags |= obmc_disable << 1;
886 result.flags |= pic->interlaced << 2;
887 result.flags |= 1 << 3; // load_intra_quant_mat
888 result.flags |= 1 << 4; // load_nonintra_quant_mat
889 result.flags |= pic->quarter_sample << 5;
890 result.flags |= 1 << 6; // complexity_estimation_disable
891 result.flags |= pic->resync_marker_disable << 7;
892 //result.flags |= data_partitioned << 8;
893 //result.flags |= reversible_vlc << 9;
894 result.flags |= 0 << 10; // newpred_enable
895 result.flags |= 0 << 11; // reduced_resolution_vop_enable
896 //result.flags |= scalability << 12;
897 //result.flags |= is_object_layer_identifier << 13;
898 //result.flags |= fixed_vop_rate << 14;
899 //result.flags |= newpred_segment_type << 15;
900
901 result.quant_type = pic->quant_type;
902
903 for (i = 0; i < 64; ++i) {
904 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
905 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
906 }
907
908 /*
909 int32_t trd [2]
910 int32_t trb [2]
911 uint8_t vop_coding_type
912 uint8_t vop_fcode_forward
913 uint8_t vop_fcode_backward
914 uint8_t rounding_control
915 uint8_t alternate_vertical_scan_flag
916 uint8_t top_field_first
917 */
918
919 return result;
920 }
921
922 /**
923 * destroy this video decoder
924 */
925 static void ruvd_destroy(struct pipe_video_codec *decoder)
926 {
927 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
928 unsigned i;
929
930 assert(decoder);
931
932 map_msg_fb_it_buf(dec);
933 memset(dec->msg, 0, sizeof(*dec->msg));
934 dec->msg->size = sizeof(*dec->msg);
935 dec->msg->msg_type = RUVD_MSG_DESTROY;
936 dec->msg->stream_handle = dec->stream_handle;
937 send_msg_buf(dec);
938
939 flush(dec, 0);
940
941 dec->ws->cs_destroy(dec->cs);
942
943 for (i = 0; i < NUM_BUFFERS; ++i) {
944 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
945 rvid_destroy_buffer(&dec->bs_buffers[i]);
946 }
947
948 rvid_destroy_buffer(&dec->dpb);
949 rvid_destroy_buffer(&dec->ctx);
950 rvid_destroy_buffer(&dec->sessionctx);
951
952 FREE(dec);
953 }
954
955 /**
956 * start decoding of a new frame
957 */
958 static void ruvd_begin_frame(struct pipe_video_codec *decoder,
959 struct pipe_video_buffer *target,
960 struct pipe_picture_desc *picture)
961 {
962 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
963 uintptr_t frame;
964
965 assert(decoder);
966
967 frame = ++dec->frame_number;
968 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
969 &ruvd_destroy_associated_data);
970
971 dec->bs_size = 0;
972 dec->bs_ptr = dec->ws->buffer_map(
973 dec->bs_buffers[dec->cur_buffer].res->buf,
974 dec->cs, PIPE_TRANSFER_WRITE);
975 }
976
977 /**
978 * decode a macroblock
979 */
980 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
981 struct pipe_video_buffer *target,
982 struct pipe_picture_desc *picture,
983 const struct pipe_macroblock *macroblocks,
984 unsigned num_macroblocks)
985 {
986 /* not supported (yet) */
987 assert(0);
988 }
989
990 /**
991 * decode a bitstream
992 */
993 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
994 struct pipe_video_buffer *target,
995 struct pipe_picture_desc *picture,
996 unsigned num_buffers,
997 const void * const *buffers,
998 const unsigned *sizes)
999 {
1000 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
1001 unsigned i;
1002
1003 assert(decoder);
1004
1005 if (!dec->bs_ptr)
1006 return;
1007
1008 for (i = 0; i < num_buffers; ++i) {
1009 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1010 unsigned new_size = dec->bs_size + sizes[i];
1011
1012 if (new_size > buf->res->buf->size) {
1013 dec->ws->buffer_unmap(buf->res->buf);
1014 if (!rvid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1015 RVID_ERR("Can't resize bitstream buffer!");
1016 return;
1017 }
1018
1019 dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1020 PIPE_TRANSFER_WRITE);
1021 if (!dec->bs_ptr)
1022 return;
1023
1024 dec->bs_ptr += dec->bs_size;
1025 }
1026
1027 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1028 dec->bs_size += sizes[i];
1029 dec->bs_ptr += sizes[i];
1030 }
1031 }
1032
1033 /**
1034 * end decoding of the current frame
1035 */
1036 static void ruvd_end_frame(struct pipe_video_codec *decoder,
1037 struct pipe_video_buffer *target,
1038 struct pipe_picture_desc *picture)
1039 {
1040 struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
1041 struct pb_buffer *dt;
1042 struct rvid_buffer *msg_fb_it_buf, *bs_buf;
1043 unsigned bs_size;
1044
1045 assert(decoder);
1046
1047 if (!dec->bs_ptr)
1048 return;
1049
1050 msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
1051 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1052
1053 bs_size = align(dec->bs_size, 128);
1054 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
1055 dec->ws->buffer_unmap(bs_buf->res->buf);
1056
1057 map_msg_fb_it_buf(dec);
1058 dec->msg->size = sizeof(*dec->msg);
1059 dec->msg->msg_type = RUVD_MSG_DECODE;
1060 dec->msg->stream_handle = dec->stream_handle;
1061 dec->msg->status_report_feedback_number = dec->frame_number;
1062
1063 dec->msg->body.decode.stream_type = dec->stream_type;
1064 dec->msg->body.decode.decode_flags = 0x1;
1065 dec->msg->body.decode.width_in_samples = dec->base.width;
1066 dec->msg->body.decode.height_in_samples = dec->base.height;
1067
1068 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
1069 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
1070 dec->msg->body.decode.width_in_samples = align(dec->msg->body.decode.width_in_samples, 16) / 16;
1071 dec->msg->body.decode.height_in_samples = align(dec->msg->body.decode.height_in_samples, 16) / 16;
1072 }
1073
1074 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1075 dec->msg->body.decode.bsd_size = bs_size;
1076 dec->msg->body.decode.db_pitch = align(dec->base.width, 16);
1077
1078 if (dec->stream_type == RUVD_CODEC_H264_PERF &&
1079 ((struct r600_common_screen*)dec->screen)->family >= CHIP_POLARIS10)
1080 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1081
1082 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
1083 if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
1084 dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
1085
1086 switch (u_reduce_video_profile(picture->profile)) {
1087 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1088 dec->msg->body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
1089 break;
1090
1091 case PIPE_VIDEO_FORMAT_HEVC:
1092 dec->msg->body.decode.codec.h265 = get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
1093 if (dec->ctx.res == NULL) {
1094 unsigned ctx_size;
1095 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1096 ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc*)picture);
1097 else
1098 ctx_size = calc_ctx_size_h265_main(dec);
1099 if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1100 RVID_ERR("Can't allocated context buffer.\n");
1101 }
1102 rvid_clear_buffer(decoder->context, &dec->ctx);
1103 }
1104
1105 if (dec->ctx.res)
1106 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1107 break;
1108
1109 case PIPE_VIDEO_FORMAT_VC1:
1110 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
1111 break;
1112
1113 case PIPE_VIDEO_FORMAT_MPEG12:
1114 dec->msg->body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
1115 break;
1116
1117 case PIPE_VIDEO_FORMAT_MPEG4:
1118 dec->msg->body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
1119 break;
1120
1121 default:
1122 assert(0);
1123 return;
1124 }
1125
1126 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
1127 dec->msg->body.decode.extension_support = 0x1;
1128
1129 /* set at least the feedback buffer size */
1130 dec->fb[0] = dec->fb_size;
1131
1132 send_msg_buf(dec);
1133
1134 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1135 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1136 if (dec->ctx.res)
1137 send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1138 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1139 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1140 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1141 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0,
1142 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1143 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf,
1144 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1145 if (have_it(dec))
1146 send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
1147 FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1148 set_reg(dec, RUVD_ENGINE_CNTL, 1);
1149
1150 flush(dec, RADEON_FLUSH_ASYNC);
1151 next_buffer(dec);
1152 }
1153
1154 /**
1155 * flush any outstanding command buffers to the hardware
1156 */
1157 static void ruvd_flush(struct pipe_video_codec *decoder)
1158 {
1159 }
1160
1161 /**
1162 * create and UVD decoder
1163 */
1164 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
1165 const struct pipe_video_codec *templ,
1166 ruvd_set_dtb set_dtb)
1167 {
1168 struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
1169 struct r600_common_context *rctx = (struct r600_common_context*)context;
1170 unsigned dpb_size;
1171 unsigned width = templ->width, height = templ->height;
1172 unsigned bs_buf_size;
1173 struct radeon_info info;
1174 struct ruvd_decoder *dec;
1175 int r, i;
1176
1177 ws->query_info(ws, &info);
1178
1179 switch(u_reduce_video_profile(templ->profile)) {
1180 case PIPE_VIDEO_FORMAT_MPEG12:
1181 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM)
1182 return vl_create_mpeg12_decoder(context, templ);
1183
1184 /* fall through */
1185 case PIPE_VIDEO_FORMAT_MPEG4:
1186 width = align(width, VL_MACROBLOCK_WIDTH);
1187 height = align(height, VL_MACROBLOCK_HEIGHT);
1188 break;
1189 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1190 width = align(width, VL_MACROBLOCK_WIDTH);
1191 height = align(height, VL_MACROBLOCK_HEIGHT);
1192 break;
1193
1194 default:
1195 break;
1196 }
1197
1198
1199 dec = CALLOC_STRUCT(ruvd_decoder);
1200
1201 if (!dec)
1202 return NULL;
1203
1204 if (info.drm_major < 3)
1205 dec->use_legacy = true;
1206
1207 dec->base = *templ;
1208 dec->base.context = context;
1209 dec->base.width = width;
1210 dec->base.height = height;
1211
1212 dec->base.destroy = ruvd_destroy;
1213 dec->base.begin_frame = ruvd_begin_frame;
1214 dec->base.decode_macroblock = ruvd_decode_macroblock;
1215 dec->base.decode_bitstream = ruvd_decode_bitstream;
1216 dec->base.end_frame = ruvd_end_frame;
1217 dec->base.flush = ruvd_flush;
1218
1219 dec->stream_type = profile2stream_type(dec, info.family);
1220 dec->set_dtb = set_dtb;
1221 dec->stream_handle = rvid_alloc_stream_handle();
1222 dec->screen = context->screen;
1223 dec->ws = ws;
1224 dec->cs = ws->cs_create(rctx->ctx, RING_UVD, NULL, NULL);
1225 if (!dec->cs) {
1226 RVID_ERR("Can't get command submission context.\n");
1227 goto error;
1228 }
1229
1230 dec->fb_size = (info.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
1231 FB_BUFFER_SIZE;
1232 bs_buf_size = width * height * (512 / (16 * 16));
1233 for (i = 0; i < NUM_BUFFERS; ++i) {
1234 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
1235 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
1236 if (have_it(dec))
1237 msg_fb_it_size += IT_SCALING_TABLE_SIZE;
1238 if (!rvid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
1239 msg_fb_it_size, PIPE_USAGE_STAGING)) {
1240 RVID_ERR("Can't allocated message buffers.\n");
1241 goto error;
1242 }
1243
1244 if (!rvid_create_buffer(dec->screen, &dec->bs_buffers[i],
1245 bs_buf_size, PIPE_USAGE_STAGING)) {
1246 RVID_ERR("Can't allocated bitstream buffers.\n");
1247 goto error;
1248 }
1249
1250 rvid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
1251 rvid_clear_buffer(context, &dec->bs_buffers[i]);
1252 }
1253
1254 dpb_size = calc_dpb_size(dec);
1255
1256 if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1257 RVID_ERR("Can't allocated dpb.\n");
1258 goto error;
1259 }
1260
1261 rvid_clear_buffer(context, &dec->dpb);
1262
1263 if (dec->stream_type == RUVD_CODEC_H264_PERF && info.family >= CHIP_POLARIS10) {
1264 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1265 if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1266 RVID_ERR("Can't allocated context buffer.\n");
1267 goto error;
1268 }
1269 rvid_clear_buffer(context, &dec->ctx);
1270 }
1271
1272 if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
1273 if (!rvid_create_buffer(dec->screen, &dec->sessionctx,
1274 UVD_SESSION_CONTEXT_SIZE,
1275 PIPE_USAGE_DEFAULT)) {
1276 RVID_ERR("Can't allocated session ctx.\n");
1277 goto error;
1278 }
1279 rvid_clear_buffer(context, &dec->sessionctx);
1280 }
1281
1282 map_msg_fb_it_buf(dec);
1283 dec->msg->size = sizeof(*dec->msg);
1284 dec->msg->msg_type = RUVD_MSG_CREATE;
1285 dec->msg->stream_handle = dec->stream_handle;
1286 dec->msg->body.create.stream_type = dec->stream_type;
1287 dec->msg->body.create.width_in_samples = dec->base.width;
1288 dec->msg->body.create.height_in_samples = dec->base.height;
1289 dec->msg->body.create.dpb_size = dpb_size;
1290 send_msg_buf(dec);
1291 r = flush(dec, 0);
1292 if (r)
1293 goto error;
1294
1295 next_buffer(dec);
1296
1297 return &dec->base;
1298
1299 error:
1300 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1301
1302 for (i = 0; i < NUM_BUFFERS; ++i) {
1303 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
1304 rvid_destroy_buffer(&dec->bs_buffers[i]);
1305 }
1306
1307 rvid_destroy_buffer(&dec->dpb);
1308 rvid_destroy_buffer(&dec->ctx);
1309 rvid_destroy_buffer(&dec->sessionctx);
1310
1311 FREE(dec);
1312
1313 return NULL;
1314 }
1315
1316 /* calculate top/bottom offset */
1317 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
1318 {
1319 return surface->level[0].offset +
1320 layer * surface->level[0].slice_size;
1321 }
1322
1323 /* hw encode the aspect of macro tiles */
1324 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1325 {
1326 switch (macro_tile_aspect) {
1327 default:
1328 case 1: macro_tile_aspect = 0; break;
1329 case 2: macro_tile_aspect = 1; break;
1330 case 4: macro_tile_aspect = 2; break;
1331 case 8: macro_tile_aspect = 3; break;
1332 }
1333 return macro_tile_aspect;
1334 }
1335
1336 /* hw encode the bank width and height */
1337 static unsigned bank_wh(unsigned bankwh)
1338 {
1339 switch (bankwh) {
1340 default:
1341 case 1: bankwh = 0; break;
1342 case 2: bankwh = 1; break;
1343 case 4: bankwh = 2; break;
1344 case 8: bankwh = 3; break;
1345 }
1346 return bankwh;
1347 }
1348
1349 /**
1350 * fill decoding target field from the luma and chroma surfaces
1351 */
1352 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
1353 struct radeon_surf *chroma)
1354 {
1355 msg->body.decode.dt_pitch = luma->level[0].pitch_bytes;
1356 switch (luma->level[0].mode) {
1357 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1358 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1359 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1360 break;
1361 case RADEON_SURF_MODE_1D:
1362 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1363 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1364 break;
1365 case RADEON_SURF_MODE_2D:
1366 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1367 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1368 break;
1369 default:
1370 assert(0);
1371 break;
1372 }
1373
1374 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0);
1375 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0);
1376 if (msg->body.decode.dt_field_mode) {
1377 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1);
1378 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1);
1379 } else {
1380 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1381 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1382 }
1383
1384 assert(luma->bankw == chroma->bankw);
1385 assert(luma->bankh == chroma->bankh);
1386 assert(luma->mtilea == chroma->mtilea);
1387
1388 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
1389 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
1390 msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
1391 }