1 /**************************************************************************
3 * Copyright 2011 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
37 /* UVD uses PM4 packet type 0 and 2 */
38 #define RUVD_PKT_TYPE_S(x) (((x) & 0x3) << 30)
39 #define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3)
40 #define RUVD_PKT_TYPE_C 0x3FFFFFFF
41 #define RUVD_PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
42 #define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
43 #define RUVD_PKT_COUNT_C 0xC000FFFF
44 #define RUVD_PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0)
45 #define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
46 #define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000
47 #define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
48 #define RUVD_PKT2() (RUVD_PKT_TYPE_S(2))
50 /* registers involved with UVD */
51 #define RUVD_GPCOM_VCPU_CMD 0xEF0C
52 #define RUVD_GPCOM_VCPU_DATA0 0xEF10
53 #define RUVD_GPCOM_VCPU_DATA1 0xEF14
54 #define RUVD_ENGINE_CNTL 0xEF18
56 /* UVD commands to VCPU */
57 #define RUVD_CMD_MSG_BUFFER 0x00000000
58 #define RUVD_CMD_DPB_BUFFER 0x00000001
59 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
60 #define RUVD_CMD_FEEDBACK_BUFFER 0x00000003
61 #define RUVD_CMD_BITSTREAM_BUFFER 0x00000100
63 /* UVD message types */
64 #define RUVD_MSG_CREATE 0
65 #define RUVD_MSG_DECODE 1
66 #define RUVD_MSG_DESTROY 2
68 /* UVD stream types */
69 #define RUVD_CODEC_H264 0x00000000
70 #define RUVD_CODEC_VC1 0x00000001
71 #define RUVD_CODEC_MPEG2 0x00000003
72 #define RUVD_CODEC_MPEG4 0x00000004
74 /* UVD decode target buffer tiling mode */
75 #define RUVD_TILE_LINEAR 0x00000000
76 #define RUVD_TILE_8X4 0x00000001
77 #define RUVD_TILE_8X8 0x00000002
78 #define RUVD_TILE_32AS8 0x00000003
80 /* UVD decode target buffer array mode */
81 #define RUVD_ARRAY_MODE_LINEAR 0x00000000
82 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001
83 #define RUVD_ARRAY_MODE_1D_THIN 0x00000002
84 #define RUVD_ARRAY_MODE_2D_THIN 0x00000004
85 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
86 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005
89 #define RUVD_BANK_WIDTH(x) ((x) << 0)
90 #define RUVD_BANK_HEIGHT(x) ((x) << 3)
91 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
92 #define RUVD_NUM_BANKS(x) ((x) << 9)
94 /* H.264 profile definitions */
95 #define RUVD_H264_PROFILE_BASELINE 0x00000000
96 #define RUVD_H264_PROFILE_MAIN 0x00000001
97 #define RUVD_H264_PROFILE_HIGH 0x00000002
98 #define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003
99 #define RUVD_H264_PROFILE_MVC 0x00000004
101 /* VC-1 profile definitions */
102 #define RUVD_VC1_PROFILE_SIMPLE 0x00000000
103 #define RUVD_VC1_PROFILE_MAIN 0x00000001
104 #define RUVD_VC1_PROFILE_ADVANCED 0x00000002
106 struct ruvd_mvc_element
{
107 uint16_t viewOrderIndex
;
109 uint16_t numOfAnchorRefsInL0
;
110 uint16_t viewIdOfAnchorRefsInL0
[15];
111 uint16_t numOfAnchorRefsInL1
;
112 uint16_t viewIdOfAnchorRefsInL1
[15];
113 uint16_t numOfNonAnchorRefsInL0
;
114 uint16_t viewIdOfNonAnchorRefsInL0
[15];
115 uint16_t numOfNonAnchorRefsInL1
;
116 uint16_t viewIdOfNonAnchorRefsInL1
[15];
123 uint32_t sps_info_flags
;
124 uint32_t pps_info_flags
;
125 uint8_t chroma_format
;
126 uint8_t bit_depth_luma_minus8
;
127 uint8_t bit_depth_chroma_minus8
;
128 uint8_t log2_max_frame_num_minus4
;
130 uint8_t pic_order_cnt_type
;
131 uint8_t log2_max_pic_order_cnt_lsb_minus4
;
132 uint8_t num_ref_frames
;
133 uint8_t reserved_8bit
;
135 int8_t pic_init_qp_minus26
;
136 int8_t pic_init_qs_minus26
;
137 int8_t chroma_qp_index_offset
;
138 int8_t second_chroma_qp_index_offset
;
140 uint8_t num_slice_groups_minus1
;
141 uint8_t slice_group_map_type
;
142 uint8_t num_ref_idx_l0_active_minus1
;
143 uint8_t num_ref_idx_l1_active_minus1
;
145 uint16_t slice_group_change_rate_minus1
;
146 uint16_t reserved_16bit_1
;
148 uint8_t scaling_list_4x4
[6][16];
149 uint8_t scaling_list_8x8
[2][64];
152 uint32_t frame_num_list
[16];
153 int32_t curr_field_order_cnt_list
[2];
154 int32_t field_order_cnt_list
[16][2];
156 uint32_t decoded_pic_idx
;
158 uint32_t curr_pic_ref_frame_num
;
160 uint8_t ref_frame_list
[16];
162 uint32_t reserved
[122];
167 struct ruvd_mvc_element mvcElements
[1];
174 uint32_t sps_info_flags
;
175 uint32_t pps_info_flags
;
176 uint32_t pic_structure
;
177 uint32_t chroma_format
;
181 uint32_t decoded_pic_idx
;
182 uint32_t ref_pic_idx
[2];
184 uint8_t load_intra_quantiser_matrix
;
185 uint8_t load_nonintra_quantiser_matrix
;
186 uint8_t reserved_quantiser_alignement
[2];
187 uint8_t intra_quantiser_matrix
[64];
188 uint8_t nonintra_quantiser_matrix
[64];
190 uint8_t profile_and_level_indication
;
191 uint8_t chroma_format
;
193 uint8_t picture_coding_type
;
197 uint8_t f_code
[2][2];
198 uint8_t intra_dc_precision
;
199 uint8_t pic_structure
;
200 uint8_t top_field_first
;
201 uint8_t frame_pred_frame_dct
;
202 uint8_t concealment_motion_vectors
;
203 uint8_t q_scale_type
;
204 uint8_t intra_vlc_format
;
205 uint8_t alternate_scan
;
210 uint32_t decoded_pic_idx
;
211 uint32_t ref_pic_idx
[2];
213 uint32_t variant_type
;
214 uint8_t profile_and_level_indication
;
216 uint8_t video_object_layer_verid
;
217 uint8_t video_object_layer_shape
;
221 uint16_t video_object_layer_width
;
222 uint16_t video_object_layer_height
;
224 uint16_t vop_time_increment_resolution
;
232 uint8_t reserved_3
[3];
234 uint8_t intra_quant_mat
[64];
235 uint8_t nonintra_quant_mat
[64];
238 uint8_t sprite_enable
;
240 uint8_t reserved_4
[3];
242 uint16_t sprite_width
;
243 uint16_t sprite_height
;
244 int16_t sprite_left_coordinate
;
245 int16_t sprite_top_coordinate
;
247 uint8_t no_of_sprite_warping_points
;
248 uint8_t sprite_warping_accuracy
;
249 uint8_t sprite_brightness_change
;
250 uint8_t low_latency_sprite_enable
;
256 uint8_t reserved_5
[3];
260 /* message between driver and hardware */
265 uint32_t stream_handle
;
266 uint32_t status_report_feedback_number
;
270 uint32_t stream_type
;
271 uint32_t session_flags
;
273 uint32_t width_in_samples
;
274 uint32_t height_in_samples
;
278 uint32_t version_info
;
282 uint32_t stream_type
;
283 uint32_t decode_flags
;
284 uint32_t width_in_samples
;
285 uint32_t height_in_samples
;
290 uint32_t dpb_reserved
;
292 uint32_t db_offset_alignment
;
294 uint32_t db_tiling_mode
;
295 uint32_t db_array_mode
;
296 uint32_t db_field_mode
;
297 uint32_t db_surf_tile_config
;
298 uint32_t db_aligned_height
;
299 uint32_t db_reserved
;
301 uint32_t use_addr_macro
;
306 uint32_t pic_param_buffer
;
307 uint32_t pic_param_size
;
308 uint32_t mb_cntl_buffer
;
309 uint32_t mb_cntl_size
;
313 uint32_t dt_tiling_mode
;
314 uint32_t dt_array_mode
;
315 uint32_t dt_field_mode
;
316 uint32_t dt_luma_top_offset
;
317 uint32_t dt_luma_bottom_offset
;
318 uint32_t dt_chroma_top_offset
;
319 uint32_t dt_chroma_bottom_offset
;
320 uint32_t dt_surf_tile_config
;
321 uint32_t dt_reserved
[3];
323 uint32_t reserved
[16];
326 struct ruvd_h264 h264
;
328 struct ruvd_mpeg2 mpeg2
;
329 struct ruvd_mpeg4 mpeg4
;
334 uint8_t extension_support
;
335 uint8_t reserved_8bit_1
;
336 uint8_t reserved_8bit_2
;
337 uint8_t reserved_8bit_3
;
338 uint32_t extension_reserved
[64];
343 /* driver dependent callback */
344 typedef struct radeon_winsys_cs_handle
* (*ruvd_set_dtb
)
345 (struct ruvd_msg
* msg
, struct vl_video_buffer
*vb
);
347 /* create an UVD decode */
348 struct pipe_video_decoder
*ruvd_create_decoder(struct pipe_context
*context
,
349 enum pipe_video_profile profile
,
350 enum pipe_video_entrypoint entrypoint
,
351 enum pipe_video_chroma_format chroma_format
,
352 unsigned width
, unsigned height
,
353 unsigned max_references
, bool expect_chunked_decode
,
354 struct radeon_winsys
* ws
,
355 ruvd_set_dtb set_dtb
);
357 /* join surfaces into the same buffer with identical tiling params
358 sumup their sizes and replace the backend buffers with a single bo */
359 void ruvd_join_surfaces(struct radeon_winsys
* ws
, unsigned bind
,
360 struct pb_buffer
** buffers
[VL_NUM_COMPONENTS
],
361 struct radeon_surface
*surfaces
[VL_NUM_COMPONENTS
]);
363 /* fill decoding target field from the luma and chroma surfaces */
364 void ruvd_set_dt_surfaces(struct ruvd_msg
*msg
, struct radeon_surface
*luma
,
365 struct radeon_surface
*chroma
);
367 /* returns supported codecs and other parameters */
368 int ruvd_get_video_param(struct pipe_screen
*screen
,
369 enum pipe_video_profile profile
,
370 enum pipe_video_cap param
);
372 /* the hardware only supports NV12 */
373 boolean
ruvd_is_format_supported(struct pipe_screen
*screen
,
374 enum pipe_format format
,
375 enum pipe_video_profile profile
);