1 /**************************************************************************
3 * Copyright 2011 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
37 #include "radeon/radeon_winsys.h"
38 #include "vl/vl_video_buffer.h"
40 /* UVD uses PM4 packet type 0 and 2 */
41 #define RUVD_PKT_TYPE_S(x) (((x) & 0x3) << 30)
42 #define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3)
43 #define RUVD_PKT_TYPE_C 0x3FFFFFFF
44 #define RUVD_PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
45 #define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
46 #define RUVD_PKT_COUNT_C 0xC000FFFF
47 #define RUVD_PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0)
48 #define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
49 #define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000
50 #define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
51 #define RUVD_PKT2() (RUVD_PKT_TYPE_S(2))
53 /* registers involved with UVD */
54 #define RUVD_GPCOM_VCPU_CMD 0xEF0C
55 #define RUVD_GPCOM_VCPU_DATA0 0xEF10
56 #define RUVD_GPCOM_VCPU_DATA1 0xEF14
57 #define RUVD_ENGINE_CNTL 0xEF18
59 /* UVD commands to VCPU */
60 #define RUVD_CMD_MSG_BUFFER 0x00000000
61 #define RUVD_CMD_DPB_BUFFER 0x00000001
62 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
63 #define RUVD_CMD_FEEDBACK_BUFFER 0x00000003
64 #define RUVD_CMD_BITSTREAM_BUFFER 0x00000100
65 #define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204
66 #define RUVD_CMD_CONTEXT_BUFFER 0x00000206
68 /* UVD message types */
69 #define RUVD_MSG_CREATE 0
70 #define RUVD_MSG_DECODE 1
71 #define RUVD_MSG_DESTROY 2
73 /* UVD stream types */
74 #define RUVD_CODEC_H264 0x00000000
75 #define RUVD_CODEC_VC1 0x00000001
76 #define RUVD_CODEC_MPEG2 0x00000003
77 #define RUVD_CODEC_MPEG4 0x00000004
78 #define RUVD_CODEC_H264_PERF 0x00000007
79 #define RUVD_CODEC_H265 0x00000010
81 /* UVD decode target buffer tiling mode */
82 #define RUVD_TILE_LINEAR 0x00000000
83 #define RUVD_TILE_8X4 0x00000001
84 #define RUVD_TILE_8X8 0x00000002
85 #define RUVD_TILE_32AS8 0x00000003
87 /* UVD decode target buffer array mode */
88 #define RUVD_ARRAY_MODE_LINEAR 0x00000000
89 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001
90 #define RUVD_ARRAY_MODE_1D_THIN 0x00000002
91 #define RUVD_ARRAY_MODE_2D_THIN 0x00000004
92 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
93 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005
96 #define RUVD_BANK_WIDTH(x) ((x) << 0)
97 #define RUVD_BANK_HEIGHT(x) ((x) << 3)
98 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
99 #define RUVD_NUM_BANKS(x) ((x) << 9)
101 /* H.264 profile definitions */
102 #define RUVD_H264_PROFILE_BASELINE 0x00000000
103 #define RUVD_H264_PROFILE_MAIN 0x00000001
104 #define RUVD_H264_PROFILE_HIGH 0x00000002
105 #define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003
106 #define RUVD_H264_PROFILE_MVC 0x00000004
108 /* VC-1 profile definitions */
109 #define RUVD_VC1_PROFILE_SIMPLE 0x00000000
110 #define RUVD_VC1_PROFILE_MAIN 0x00000001
111 #define RUVD_VC1_PROFILE_ADVANCED 0x00000002
113 struct ruvd_mvc_element
{
114 uint16_t viewOrderIndex
;
116 uint16_t numOfAnchorRefsInL0
;
117 uint16_t viewIdOfAnchorRefsInL0
[15];
118 uint16_t numOfAnchorRefsInL1
;
119 uint16_t viewIdOfAnchorRefsInL1
[15];
120 uint16_t numOfNonAnchorRefsInL0
;
121 uint16_t viewIdOfNonAnchorRefsInL0
[15];
122 uint16_t numOfNonAnchorRefsInL1
;
123 uint16_t viewIdOfNonAnchorRefsInL1
[15];
130 uint32_t sps_info_flags
;
131 uint32_t pps_info_flags
;
132 uint8_t chroma_format
;
133 uint8_t bit_depth_luma_minus8
;
134 uint8_t bit_depth_chroma_minus8
;
135 uint8_t log2_max_frame_num_minus4
;
137 uint8_t pic_order_cnt_type
;
138 uint8_t log2_max_pic_order_cnt_lsb_minus4
;
139 uint8_t num_ref_frames
;
140 uint8_t reserved_8bit
;
142 int8_t pic_init_qp_minus26
;
143 int8_t pic_init_qs_minus26
;
144 int8_t chroma_qp_index_offset
;
145 int8_t second_chroma_qp_index_offset
;
147 uint8_t num_slice_groups_minus1
;
148 uint8_t slice_group_map_type
;
149 uint8_t num_ref_idx_l0_active_minus1
;
150 uint8_t num_ref_idx_l1_active_minus1
;
152 uint16_t slice_group_change_rate_minus1
;
153 uint16_t reserved_16bit_1
;
155 uint8_t scaling_list_4x4
[6][16];
156 uint8_t scaling_list_8x8
[2][64];
159 uint32_t frame_num_list
[16];
160 int32_t curr_field_order_cnt_list
[2];
161 int32_t field_order_cnt_list
[16][2];
163 uint32_t decoded_pic_idx
;
165 uint32_t curr_pic_ref_frame_num
;
167 uint8_t ref_frame_list
[16];
169 uint32_t reserved
[122];
174 struct ruvd_mvc_element mvcElements
[1];
179 uint32_t sps_info_flags
;
180 uint32_t pps_info_flags
;
182 uint8_t chroma_format
;
183 uint8_t bit_depth_luma_minus8
;
184 uint8_t bit_depth_chroma_minus8
;
185 uint8_t log2_max_pic_order_cnt_lsb_minus4
;
187 uint8_t sps_max_dec_pic_buffering_minus1
;
188 uint8_t log2_min_luma_coding_block_size_minus3
;
189 uint8_t log2_diff_max_min_luma_coding_block_size
;
190 uint8_t log2_min_transform_block_size_minus2
;
192 uint8_t log2_diff_max_min_transform_block_size
;
193 uint8_t max_transform_hierarchy_depth_inter
;
194 uint8_t max_transform_hierarchy_depth_intra
;
195 uint8_t pcm_sample_bit_depth_luma_minus1
;
197 uint8_t pcm_sample_bit_depth_chroma_minus1
;
198 uint8_t log2_min_pcm_luma_coding_block_size_minus3
;
199 uint8_t log2_diff_max_min_pcm_luma_coding_block_size
;
200 uint8_t num_extra_slice_header_bits
;
202 uint8_t num_short_term_ref_pic_sets
;
203 uint8_t num_long_term_ref_pic_sps
;
204 uint8_t num_ref_idx_l0_default_active_minus1
;
205 uint8_t num_ref_idx_l1_default_active_minus1
;
207 int8_t pps_cb_qp_offset
;
208 int8_t pps_cr_qp_offset
;
209 int8_t pps_beta_offset_div2
;
210 int8_t pps_tc_offset_div2
;
212 uint8_t diff_cu_qp_delta_depth
;
213 uint8_t num_tile_columns_minus1
;
214 uint8_t num_tile_rows_minus1
;
215 uint8_t log2_parallel_merge_level_minus2
;
217 uint16_t column_width_minus1
[19];
218 uint16_t row_height_minus1
[21];
220 int8_t init_qp_minus26
;
221 uint8_t num_delta_pocs_ref_rps_idx
;
225 uint8_t ref_pic_list
[16];
226 int32_t poc_list
[16];
227 uint8_t ref_pic_set_st_curr_before
[8];
228 uint8_t ref_pic_set_st_curr_after
[8];
229 uint8_t ref_pic_set_lt_curr
[8];
231 uint8_t ucScalingListDCCoefSizeID2
[6];
232 uint8_t ucScalingListDCCoefSizeID3
[2];
241 uint32_t sps_info_flags
;
242 uint32_t pps_info_flags
;
243 uint32_t pic_structure
;
244 uint32_t chroma_format
;
248 uint32_t decoded_pic_idx
;
249 uint32_t ref_pic_idx
[2];
251 uint8_t load_intra_quantiser_matrix
;
252 uint8_t load_nonintra_quantiser_matrix
;
253 uint8_t reserved_quantiser_alignement
[2];
254 uint8_t intra_quantiser_matrix
[64];
255 uint8_t nonintra_quantiser_matrix
[64];
257 uint8_t profile_and_level_indication
;
258 uint8_t chroma_format
;
260 uint8_t picture_coding_type
;
264 uint8_t f_code
[2][2];
265 uint8_t intra_dc_precision
;
266 uint8_t pic_structure
;
267 uint8_t top_field_first
;
268 uint8_t frame_pred_frame_dct
;
269 uint8_t concealment_motion_vectors
;
270 uint8_t q_scale_type
;
271 uint8_t intra_vlc_format
;
272 uint8_t alternate_scan
;
277 uint32_t decoded_pic_idx
;
278 uint32_t ref_pic_idx
[2];
280 uint32_t variant_type
;
281 uint8_t profile_and_level_indication
;
283 uint8_t video_object_layer_verid
;
284 uint8_t video_object_layer_shape
;
288 uint16_t video_object_layer_width
;
289 uint16_t video_object_layer_height
;
291 uint16_t vop_time_increment_resolution
;
299 uint8_t reserved_3
[3];
301 uint8_t intra_quant_mat
[64];
302 uint8_t nonintra_quant_mat
[64];
305 uint8_t sprite_enable
;
307 uint8_t reserved_4
[3];
309 uint16_t sprite_width
;
310 uint16_t sprite_height
;
311 int16_t sprite_left_coordinate
;
312 int16_t sprite_top_coordinate
;
314 uint8_t no_of_sprite_warping_points
;
315 uint8_t sprite_warping_accuracy
;
316 uint8_t sprite_brightness_change
;
317 uint8_t low_latency_sprite_enable
;
323 uint8_t reserved_5
[3];
327 /* message between driver and hardware */
332 uint32_t stream_handle
;
333 uint32_t status_report_feedback_number
;
337 uint32_t stream_type
;
338 uint32_t session_flags
;
340 uint32_t width_in_samples
;
341 uint32_t height_in_samples
;
345 uint32_t version_info
;
349 uint32_t stream_type
;
350 uint32_t decode_flags
;
351 uint32_t width_in_samples
;
352 uint32_t height_in_samples
;
357 uint32_t dpb_reserved
;
359 uint32_t db_offset_alignment
;
361 uint32_t db_tiling_mode
;
362 uint32_t db_array_mode
;
363 uint32_t db_field_mode
;
364 uint32_t db_surf_tile_config
;
365 uint32_t db_aligned_height
;
366 uint32_t db_reserved
;
368 uint32_t use_addr_macro
;
373 uint32_t pic_param_buffer
;
374 uint32_t pic_param_size
;
375 uint32_t mb_cntl_buffer
;
376 uint32_t mb_cntl_size
;
380 uint32_t dt_tiling_mode
;
381 uint32_t dt_array_mode
;
382 uint32_t dt_field_mode
;
383 uint32_t dt_luma_top_offset
;
384 uint32_t dt_luma_bottom_offset
;
385 uint32_t dt_chroma_top_offset
;
386 uint32_t dt_chroma_bottom_offset
;
387 uint32_t dt_surf_tile_config
;
388 uint32_t dt_reserved
[3];
390 uint32_t reserved
[16];
393 struct ruvd_h264 h264
;
394 struct ruvd_h265 h265
;
396 struct ruvd_mpeg2 mpeg2
;
397 struct ruvd_mpeg4 mpeg4
;
402 uint8_t extension_support
;
403 uint8_t reserved_8bit_1
;
404 uint8_t reserved_8bit_2
;
405 uint8_t reserved_8bit_3
;
406 uint32_t extension_reserved
[64];
411 /* driver dependent callback */
412 typedef struct radeon_winsys_cs_handle
* (*ruvd_set_dtb
)
413 (struct ruvd_msg
* msg
, struct vl_video_buffer
*vb
);
415 /* create an UVD decode */
416 struct pipe_video_codec
*ruvd_create_decoder(struct pipe_context
*context
,
417 const struct pipe_video_codec
*templat
,
418 ruvd_set_dtb set_dtb
);
420 /* fill decoding target field from the luma and chroma surfaces */
421 void ruvd_set_dt_surfaces(struct ruvd_msg
*msg
, struct radeon_surf
*luma
,
422 struct radeon_surf
*chroma
);