src/gallium/drivers/radeon/radeon_uvd.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2011 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #ifndef RADEON_UVD_H
  35 #define RADEON_UVD_H
  36
  37 #include "radeon/radeon_winsys.h"
  38 #include "vl/vl_video_buffer.h"
  39
  40 /* UVD uses PM4 packet type 0 and 2 */
  41 #define RUVD_PKT_TYPE_S(x)              (((x) & 0x3) << 30)
  42 #define RUVD_PKT_TYPE_G(x)              (((x) >> 30) & 0x3)
  43 #define RUVD_PKT_TYPE_C                 0x3FFFFFFF
  44 #define RUVD_PKT_COUNT_S(x)             (((x) & 0x3FFF) << 16)
  45 #define RUVD_PKT_COUNT_G(x)             (((x) >> 16) & 0x3FFF)
  46 #define RUVD_PKT_COUNT_C                0xC000FFFF
  47 #define RUVD_PKT0_BASE_INDEX_S(x)       (((x) & 0xFFFF) << 0)
  48 #define RUVD_PKT0_BASE_INDEX_G(x)       (((x) >> 0) & 0xFFFF)
  49 #define RUVD_PKT0_BASE_INDEX_C          0xFFFF0000
  50 #define RUVD_PKT0(index, count)         (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
  51 #define RUVD_PKT2()                     (RUVD_PKT_TYPE_S(2))
  52
  53 /* registers involved with UVD */
  54 #define RUVD_GPCOM_VCPU_CMD             0xEF0C
  55 #define RUVD_GPCOM_VCPU_DATA0           0xEF10
  56 #define RUVD_GPCOM_VCPU_DATA1           0xEF14
  57 #define RUVD_ENGINE_CNTL                0xEF18
  58
  59 /* UVD commands to VCPU */
  60 #define RUVD_CMD_MSG_BUFFER             0x00000000
  61 #define RUVD_CMD_DPB_BUFFER             0x00000001
  62 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
  63 #define RUVD_CMD_FEEDBACK_BUFFER        0x00000003
  64 #define RUVD_CMD_BITSTREAM_BUFFER       0x00000100
  65
  66 /* UVD message types */
  67 #define RUVD_MSG_CREATE         0
  68 #define RUVD_MSG_DECODE         1
  69 #define RUVD_MSG_DESTROY        2
  70
  71 /* UVD stream types */
  72 #define RUVD_CODEC_H264         0x00000000
  73 #define RUVD_CODEC_VC1          0x00000001
  74 #define RUVD_CODEC_MPEG2        0x00000003
  75 #define RUVD_CODEC_MPEG4        0x00000004
  76
  77 /* UVD decode target buffer tiling mode */
  78 #define RUVD_TILE_LINEAR        0x00000000
  79 #define RUVD_TILE_8X4           0x00000001
  80 #define RUVD_TILE_8X8           0x00000002
  81 #define RUVD_TILE_32AS8         0x00000003
  82
  83 /* UVD decode target buffer array mode */
  84 #define RUVD_ARRAY_MODE_LINEAR                          0x00000000
  85 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED        0x00000001
  86 #define RUVD_ARRAY_MODE_1D_THIN                         0x00000002
  87 #define RUVD_ARRAY_MODE_2D_THIN                         0x00000004
  88 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR        0x00000004
  89 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED         0x00000005
  90
  91 /* UVD tile config */
  92 #define RUVD_BANK_WIDTH(x)              ((x) << 0)
  93 #define RUVD_BANK_HEIGHT(x)             ((x) << 3)
  94 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
  95 #define RUVD_NUM_BANKS(x)               ((x) << 9)
  96
  97 /* H.264 profile definitions */
  98 #define RUVD_H264_PROFILE_BASELINE      0x00000000
  99 #define RUVD_H264_PROFILE_MAIN          0x00000001
 100 #define RUVD_H264_PROFILE_HIGH          0x00000002
 101 #define RUVD_H264_PROFILE_STEREO_HIGH   0x00000003
 102 #define RUVD_H264_PROFILE_MVC           0x00000004
 103
 104 /* VC-1 profile definitions */
 105 #define RUVD_VC1_PROFILE_SIMPLE         0x00000000
 106 #define RUVD_VC1_PROFILE_MAIN           0x00000001
 107 #define RUVD_VC1_PROFILE_ADVANCED       0x00000002
 108
 109 struct ruvd_mvc_element {
 110         uint16_t        viewOrderIndex;
 111         uint16_t        viewId;
 112         uint16_t        numOfAnchorRefsInL0;
 113         uint16_t        viewIdOfAnchorRefsInL0[15];
 114         uint16_t        numOfAnchorRefsInL1;
 115         uint16_t        viewIdOfAnchorRefsInL1[15];
 116         uint16_t        numOfNonAnchorRefsInL0;
 117         uint16_t        viewIdOfNonAnchorRefsInL0[15];
 118         uint16_t        numOfNonAnchorRefsInL1;
 119         uint16_t        viewIdOfNonAnchorRefsInL1[15];
 120 };
 121
 122 struct ruvd_h264 {
 123         uint32_t        profile;
 124         uint32_t        level;
 125
 126         uint32_t        sps_info_flags;
 127         uint32_t        pps_info_flags;
 128         uint8_t         chroma_format;
 129         uint8_t         bit_depth_luma_minus8;
 130         uint8_t         bit_depth_chroma_minus8;
 131         uint8_t         log2_max_frame_num_minus4;
 132
 133         uint8_t         pic_order_cnt_type;
 134         uint8_t         log2_max_pic_order_cnt_lsb_minus4;
 135         uint8_t         num_ref_frames;
 136         uint8_t         reserved_8bit;
 137
 138         int8_t          pic_init_qp_minus26;
 139         int8_t          pic_init_qs_minus26;
 140         int8_t          chroma_qp_index_offset;
 141         int8_t          second_chroma_qp_index_offset;
 142
 143         uint8_t         num_slice_groups_minus1;
 144         uint8_t         slice_group_map_type;
 145         uint8_t         num_ref_idx_l0_active_minus1;
 146         uint8_t         num_ref_idx_l1_active_minus1;
 147
 148         uint16_t        slice_group_change_rate_minus1;
 149         uint16_t        reserved_16bit_1;
 150
 151         uint8_t         scaling_list_4x4[6][16];
 152         uint8_t         scaling_list_8x8[2][64];
 153
 154         uint32_t        frame_num;
 155         uint32_t        frame_num_list[16];
 156         int32_t         curr_field_order_cnt_list[2];
 157         int32_t         field_order_cnt_list[16][2];
 158
 159         uint32_t        decoded_pic_idx;
 160
 161         uint32_t        curr_pic_ref_frame_num;
 162
 163         uint8_t         ref_frame_list[16];
 164
 165         uint32_t        reserved[122];
 166
 167         struct {
 168                 uint32_t                        numViews;
 169                 uint32_t                        viewId0;
 170                 struct ruvd_mvc_element mvcElements[1];
 171         } mvc;
 172 };
 173
 174 struct ruvd_vc1 {
 175         uint32_t        profile;
 176         uint32_t        level;
 177         uint32_t        sps_info_flags;
 178         uint32_t        pps_info_flags;
 179         uint32_t        pic_structure;
 180         uint32_t        chroma_format;
 181 };
 182
 183 struct ruvd_mpeg2 {
 184         uint32_t        decoded_pic_idx;
 185         uint32_t        ref_pic_idx[2];
 186
 187         uint8_t         load_intra_quantiser_matrix;
 188         uint8_t         load_nonintra_quantiser_matrix;
 189         uint8_t         reserved_quantiser_alignement[2];
 190         uint8_t         intra_quantiser_matrix[64];
 191         uint8_t         nonintra_quantiser_matrix[64];
 192
 193         uint8_t         profile_and_level_indication;
 194         uint8_t         chroma_format;
 195
 196         uint8_t         picture_coding_type;
 197
 198         uint8_t         reserved_1;
 199
 200         uint8_t         f_code[2][2];
 201         uint8_t         intra_dc_precision;
 202         uint8_t         pic_structure;
 203         uint8_t         top_field_first;
 204         uint8_t         frame_pred_frame_dct;
 205         uint8_t         concealment_motion_vectors;
 206         uint8_t         q_scale_type;
 207         uint8_t         intra_vlc_format;
 208         uint8_t         alternate_scan;
 209 };
 210
 211 struct ruvd_mpeg4
 212 {
 213         uint32_t        decoded_pic_idx;
 214         uint32_t        ref_pic_idx[2];
 215
 216         uint32_t        variant_type;
 217         uint8_t         profile_and_level_indication;
 218
 219         uint8_t         video_object_layer_verid;
 220         uint8_t         video_object_layer_shape;
 221
 222         uint8_t         reserved_1;
 223
 224         uint16_t        video_object_layer_width;
 225         uint16_t        video_object_layer_height;
 226
 227         uint16_t        vop_time_increment_resolution;
 228
 229         uint16_t        reserved_2;
 230
 231         uint32_t        flags;
 232
 233         uint8_t         quant_type;
 234
 235         uint8_t         reserved_3[3];
 236
 237         uint8_t         intra_quant_mat[64];
 238         uint8_t         nonintra_quant_mat[64];
 239
 240         struct {
 241                 uint8_t         sprite_enable;
 242
 243                 uint8_t         reserved_4[3];
 244
 245                 uint16_t        sprite_width;
 246                 uint16_t        sprite_height;
 247                 int16_t         sprite_left_coordinate;
 248                 int16_t         sprite_top_coordinate;
 249
 250                 uint8_t         no_of_sprite_warping_points;
 251                 uint8_t         sprite_warping_accuracy;
 252                 uint8_t         sprite_brightness_change;
 253                 uint8_t         low_latency_sprite_enable;
 254         } sprite_config;
 255
 256         struct {
 257                 uint32_t        flags;
 258                 uint8_t         vol_mode;
 259                 uint8_t         reserved_5[3];
 260         } divx_311_config;
 261 };
 262
 263 /* message between driver and hardware */
 264 struct ruvd_msg {
 265
 266         uint32_t        size;
 267         uint32_t        msg_type;
 268         uint32_t        stream_handle;
 269         uint32_t        status_report_feedback_number;
 270
 271         union {
 272                 struct {
 273                         uint32_t        stream_type;
 274                         uint32_t        session_flags;
 275                         uint32_t        asic_id;
 276                         uint32_t        width_in_samples;
 277                         uint32_t        height_in_samples;
 278                         uint32_t        dpb_buffer;
 279                         uint32_t        dpb_size;
 280                         uint32_t        dpb_model;
 281                         uint32_t        version_info;
 282                 } create;
 283
 284                 struct {
 285                         uint32_t        stream_type;
 286                         uint32_t        decode_flags;
 287                         uint32_t        width_in_samples;
 288                         uint32_t        height_in_samples;
 289
 290                         uint32_t        dpb_buffer;
 291                         uint32_t        dpb_size;
 292                         uint32_t        dpb_model;
 293                         uint32_t        dpb_reserved;
 294
 295                         uint32_t        db_offset_alignment;
 296                         uint32_t        db_pitch;
 297                         uint32_t        db_tiling_mode;
 298                         uint32_t        db_array_mode;
 299                         uint32_t        db_field_mode;
 300                         uint32_t        db_surf_tile_config;
 301                         uint32_t        db_aligned_height;
 302                         uint32_t        db_reserved;
 303
 304                         uint32_t        use_addr_macro;
 305
 306                         uint32_t        bsd_buffer;
 307                         uint32_t        bsd_size;
 308
 309                         uint32_t        pic_param_buffer;
 310                         uint32_t        pic_param_size;
 311                         uint32_t        mb_cntl_buffer;
 312                         uint32_t        mb_cntl_size;
 313
 314                         uint32_t        dt_buffer;
 315                         uint32_t        dt_pitch;
 316                         uint32_t        dt_tiling_mode;
 317                         uint32_t        dt_array_mode;
 318                         uint32_t        dt_field_mode;
 319                         uint32_t        dt_luma_top_offset;
 320                         uint32_t        dt_luma_bottom_offset;
 321                         uint32_t        dt_chroma_top_offset;
 322                         uint32_t        dt_chroma_bottom_offset;
 323                         uint32_t        dt_surf_tile_config;
 324                         uint32_t        dt_reserved[3];
 325
 326                         uint32_t        reserved[16];
 327
 328                         union {
 329                                 struct ruvd_h264        h264;
 330                                 struct ruvd_vc1         vc1;
 331                                 struct ruvd_mpeg2       mpeg2;
 332                                 struct ruvd_mpeg4       mpeg4;
 333
 334                                 uint32_t info[768];
 335                         } codec;
 336
 337                         uint8_t         extension_support;
 338                         uint8_t         reserved_8bit_1;
 339                         uint8_t         reserved_8bit_2;
 340                         uint8_t         reserved_8bit_3;
 341                         uint32_t        extension_reserved[64];
 342                 } decode;
 343         } body;
 344 };
 345
 346 /* driver dependent callback */
 347 typedef struct radeon_winsys_cs_handle* (*ruvd_set_dtb)
 348 (struct ruvd_msg* msg, struct vl_video_buffer *vb);
 349
 350 /* create an UVD decode */
 351 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
 352                                              const struct pipe_video_codec *templat,
 353                                              ruvd_set_dtb set_dtb);
 354
 355 /* fill decoding target field from the luma and chroma surfaces */
 356 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
 357                           struct radeon_surf *chroma);
 358 #endif