src/gallium/drivers/radeon/radeon_uvd_enc.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef _RADEON_UVD_ENC_H
  29 #define _RADEON_UVD_ENC_H
  30
  31 #define RENC_UVD_FW_INTERFACE_MAJOR_VERSION     1
  32 #define RENC_UVD_FW_INTERFACE_MINOR_VERSION     1
  33
  34 #define RENC_UVD_IB_PARAM_SESSION_INFO                  0x00000001
  35 #define RENC_UVD_IB_PARAM_TASK_INFO                     0x00000002
  36 #define RENC_UVD_IB_PARAM_SESSION_INIT                  0x00000003
  37 #define RENC_UVD_IB_PARAM_LAYER_CONTROL                 0x00000004
  38 #define RENC_UVD_IB_PARAM_LAYER_SELECT                  0x00000005
  39 #define RENC_UVD_IB_PARAM_SLICE_CONTROL                 0x00000006
  40 #define RENC_UVD_IB_PARAM_SPEC_MISC                     0x00000007
  41 #define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT     0x00000008
  42 #define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT       0x00000009
  43 #define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE      0x0000000a
  44 #define RENC_UVD_IB_PARAM_SLICE_HEADER                  0x0000000b
  45 #define RENC_UVD_IB_PARAM_ENCODE_PARAMS                 0x0000000c
  46 #define RENC_UVD_IB_PARAM_QUALITY_PARAMS                0x0000000d
  47 #define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER             0x0000000e
  48 #define RENC_UVD_IB_PARAM_INTRA_REFRESH                 0x0000000f
  49 #define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER         0x00000010
  50 #define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER        0x00000011
  51 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER               0x00000012
  52 #define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER            0x00000013
  53 #define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL    0x00000014
  54
  55 #define RENC_UVD_IB_OP_INITIALIZE                       0x08000001
  56 #define RENC_UVD_IB_OP_CLOSE_SESSION                    0x08000002
  57 #define RENC_UVD_IB_OP_ENCODE                           0x08000003
  58 #define RENC_UVD_IB_OP_INIT_RC                          0x08000004
  59 #define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL         0x08000005
  60 #define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE          0x08000006
  61 #define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE        0x08000007
  62 #define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE        0x08000008
  63
  64 #define RENC_UVD_IF_MAJOR_VERSION_MASK                  0xFFFF0000
  65 #define RENC_UVD_IF_MAJOR_VERSION_SHIFT                 16
  66 #define RENC_UVD_IF_MINOR_VERSION_MASK                  0x0000FFFF
  67 #define RENC_UVD_IF_MINOR_VERSION_SHIFT                 0
  68
  69 #define RENC_UVD_PREENCODE_MODE_NONE                    0x00000000
  70 #define RENC_UVD_PREENCODE_MODE_1X                      0x00000001
  71 #define RENC_UVD_PREENCODE_MODE_2X                      0x00000002
  72 #define RENC_UVD_PREENCODE_MODE_4X                      0x00000004
  73
  74 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS          0x00000000
  75 #define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS          0x00000001
  76
  77 #define RENC_UVD_RATE_CONTROL_METHOD_NONE                       0x00000000
  78 #define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR    0x00000001
  79 #define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR       0x00000002
  80 #define RENC_UVD_RATE_CONTROL_METHOD_CBR                        0x00000003
  81
  82 #define RENC_UVD_NALU_TYPE_AUD              0x00000001
  83 #define RENC_UVD_NALU_TYPE_VPS              0x00000002
  84 #define RENC_UVD_NALU_TYPE_SPS              0x00000003
  85 #define RENC_UVD_NALU_TYPE_PPS              0x00000004
  86 #define RENC_UVD_NALU_TYPE_END_OF_SEQUENCE  0x00000005
  87
  88 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS      16
  89 #define RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS             16
  90
  91 #define RENC_UVD_HEADER_INSTRUCTION_END                                 0
  92 #define RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END                 1
  93 #define RENC_UVD_HEADER_INSTRUCTION_COPY                                2
  94 #define RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE                         3
  95 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT                       4
  96 #define RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA                      5
  97
  98 #define RENC_UVD_PICTURE_TYPE_B                 0
  99 #define RENC_UVD_PICTURE_TYPE_P                 1
 100 #define RENC_UVD_PICTURE_TYPE_I                 2
 101 #define RENC_UVD_PICTURE_TYPE_P_SKIP            3
 102
 103 #define RENC_UVD_SWIZZLE_MODE_LINEAR                    0
 104 #define RENC_UVD_SWIZZLE_MODE_256B_D                    2
 105 #define RENC_UVD_SWIZZLE_MODE_4kB_D                     6
 106 #define RENC_UVD_SWIZZLE_MODE_64kB_D                    10
 107 #define RENC_UVD_INTRA_REFRESH_MODE_NONE                0
 108 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_ROWS         1
 109 #define RENC_UVD_INTRA_REFRESH_MODE_CTB_MB_COLUMNS      2
 110
 111 #define RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES         34
 112 #define RENC_UVD_ADDR_MODE_LINEAR                       0
 113 #define RENC_UVD_ADDR_MODE_PELE_8X8_1D                  1
 114 #define RENC_UVD_ADDR_MODE_32AS8_88                     2
 115
 116 #define RENC_UVD_ARRAY_MODE_LINEAR                      0
 117 #define RENC_UVD_ARRAY_MODE_PELE_8X8_1D                 2
 118 #define RENC_UVD_ARRAY_MODE_2D_TILED_THIN1              4
 119
 120 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR     0
 121 #define RENC_UVD_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR   1
 122
 123 #define RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR            0
 124 #define RENC_UVD_FEEDBACK_BUFFER_MODE_CIRCULAR          1
 125
 126 #define RENC_UVD_FEEDBACK_STATUS_OK                     0x00000000
 127 #define RENC_UVD_FEEDBACK_STATUS_NOT_ENCODED            0x10000001
 128
 129 typedef struct radeon_uvd_enc_feedback_s
 130 {
 131    uint32_t task_id;
 132    uint32_t first_in_task;
 133    uint32_t last_in_task;
 134    uint32_t status;
 135    uint32_t has_bitstream;
 136    uint32_t bitstream_offset;
 137    uint32_t bitstream_size;
 138    uint32_t enabled_filler_data;
 139    uint32_t filler_data_size;
 140    uint32_t extra_bytes;
 141 } radeon_uvd_enc_feedback_t;
 142
 143 typedef struct ruvd_enc_session_info_s
 144 {
 145    uint32_t reserved;
 146    uint32_t interface_version;
 147    uint32_t sw_context_address_hi;
 148    uint32_t sw_context_address_lo;
 149 } ruvd_enc_session_info_t;
 150
 151 typedef struct ruvd_enc_task_info_s
 152 {
 153    uint32_t total_size_of_all_packages;
 154    uint32_t task_id;
 155    uint32_t allowed_max_num_feedbacks;
 156 } ruvd_enc_task_info_t;
 157
 158 typedef struct ruvd_enc_session_init_s
 159 {
 160    uint32_t aligned_picture_width;
 161    uint32_t aligned_picture_height;
 162    uint32_t padding_width;
 163    uint32_t padding_height;
 164    uint32_t pre_encode_mode;
 165    uint32_t pre_encode_chroma_enabled;
 166 } ruvd_enc_session_init_t;
 167
 168 typedef struct ruvd_enc_layer_control_s
 169 {
 170    uint32_t max_num_temporal_layers;
 171    uint32_t num_temporal_layers;
 172 } ruvd_enc_layer_control_t;
 173
 174 typedef struct ruvd_enc_layer_select_s
 175 {
 176    uint32_t temporal_layer_index;
 177 } ruvd_enc_layer_select_t;
 178
 179 typedef struct ruvd_enc_hevc_slice_control_s
 180 {
 181    uint32_t slice_control_mode;
 182    union
 183    {
 184       struct
 185       {
 186          uint32_t num_ctbs_per_slice;
 187          uint32_t num_ctbs_per_slice_segment;
 188       } fixed_ctbs_per_slice;
 189
 190       struct
 191       {
 192          uint32_t num_bits_per_slice;
 193          uint32_t num_bits_per_slice_segment;
 194       } fixed_bits_per_slice;
 195    };
 196 } ruvd_enc_hevc_slice_control_t;
 197
 198 typedef struct ruvd_enc_hevc_spec_misc_s
 199 {
 200    uint32_t log2_min_luma_coding_block_size_minus3;
 201    uint32_t amp_disabled;
 202    uint32_t strong_intra_smoothing_enabled;
 203    uint32_t constrained_intra_pred_flag;
 204    uint32_t cabac_init_flag;
 205    uint32_t half_pel_enabled;
 206    uint32_t quarter_pel_enabled;
 207 } ruvd_enc_hevc_spec_misc_t;
 208
 209 typedef struct ruvd_enc_rate_ctl_session_init_s
 210 {
 211    uint32_t rate_control_method;
 212    uint32_t vbv_buffer_level;
 213 } ruvd_enc_rate_ctl_session_init_t;
 214
 215 typedef struct ruvd_enc_rate_ctl_layer_init_s
 216 {
 217    uint32_t target_bit_rate;
 218    uint32_t peak_bit_rate;
 219    uint32_t frame_rate_num;
 220    uint32_t frame_rate_den;
 221    uint32_t vbv_buffer_size;
 222    uint32_t avg_target_bits_per_picture;
 223    uint32_t peak_bits_per_picture_integer;
 224    uint32_t peak_bits_per_picture_fractional;
 225 } ruvd_enc_rate_ctl_layer_init_t;
 226
 227 typedef struct ruvd_enc_rate_ctl_per_picture_s
 228 {
 229    uint32_t qp;
 230    uint32_t min_qp_app;
 231    uint32_t max_qp_app;
 232    uint32_t max_au_size;
 233    uint32_t enabled_filler_data;
 234    uint32_t skip_frame_enable;
 235    uint32_t enforce_hrd;
 236 } ruvd_enc_rate_ctl_per_picture_t;
 237
 238 typedef struct ruvd_enc_quality_params_s
 239 {
 240    uint32_t vbaq_mode;
 241    uint32_t scene_change_sensitivity;
 242    uint32_t scene_change_min_idr_interval;
 243 } ruvd_enc_quality_params_t;
 244
 245 typedef struct ruvd_enc_direct_output_nalu_s
 246 {
 247    uint32_t type;
 248    uint32_t size;
 249    uint32_t data[1];
 250 } ruvd_enc_direct_output_nalu_t;
 251
 252 typedef struct ruvd_enc_slice_header_s
 253 {
 254    uint32_t
 255       bitstream_template
 256       [RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
 257    struct
 258    {
 259       uint32_t instruction;
 260       uint32_t num_bits;
 261    } instructions[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
 262 } ruvd_enc_slice_header_t;
 263
 264 typedef struct ruvd_enc_encode_params_s
 265 {
 266    uint32_t pic_type;
 267    uint32_t allowed_max_bitstream_size;
 268    uint32_t input_picture_luma_address_hi;
 269    uint32_t input_picture_luma_address_lo;
 270    uint32_t input_picture_chroma_address_hi;
 271    uint32_t input_picture_chroma_address_lo;
 272    uint32_t input_pic_luma_pitch;
 273    uint32_t input_pic_chroma_pitch;
 274    union
 275    {
 276       uint32_t input_pic_addr_mode;
 277       uint32_t reserved;
 278    };
 279    union
 280    {
 281       uint32_t input_pic_array_mode;
 282       uint32_t input_pic_swizzle_mode;
 283    };
 284    uint32_t reference_picture_index;
 285    uint32_t reconstructed_picture_index;
 286 } ruvd_enc_encode_params_t;
 287
 288 typedef struct ruvd_enc_hevc_deblocking_filter_s
 289 {
 290    uint32_t loop_filter_across_slices_enabled;
 291    int32_t deblocking_filter_disabled;
 292    int32_t beta_offset_div2;
 293    int32_t tc_offset_div2;
 294    int32_t cb_qp_offset;
 295    int32_t cr_qp_offset;
 296 } ruvd_enc_hevc_deblocking_filter_t;
 297
 298 typedef struct ruvd_enc_intra_refresh_s
 299 {
 300    uint32_t intra_refresh_mode;
 301    uint32_t offset;
 302    uint32_t region_size;
 303 } ruvd_enc_intra_refresh_t;
 304
 305 typedef struct ruvd_enc_reconstructed_picture_s
 306 {
 307    uint32_t luma_offset;
 308    uint32_t chroma_offset;
 309 } ruvd_enc_reconstructed_picture_t;
 310
 311 typedef struct ruvd_enc_encode_context_buffer_s
 312 {
 313    uint32_t encode_context_address_hi;
 314    uint32_t encode_context_address_lo;
 315    union
 316    {
 317       uint32_t addr_mode;
 318       uint32_t reserved;
 319    };
 320    union
 321    {
 322       uint32_t array_mode;
 323       uint32_t swizzle_mode;
 324    };
 325    uint32_t rec_luma_pitch;
 326    uint32_t rec_chroma_pitch;
 327    uint32_t num_reconstructed_pictures;
 328    ruvd_enc_reconstructed_picture_t
 329       reconstructed_pictures[RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
 330    uint32_t pre_encode_picture_luma_pitch;
 331    uint32_t pre_encode_picture_chroma_pitch;
 332    ruvd_enc_reconstructed_picture_t
 333       pre_encode_reconstructed_pictures
 334       [RENC_UVD_MAX_NUM_RECONSTRUCTED_PICTURES];
 335    ruvd_enc_reconstructed_picture_t pre_encode_input_picture;
 336 } ruvd_enc_encode_context_buffer_t;
 337
 338 typedef struct ruvd_enc_video_bitstream_buffer_s
 339 {
 340    uint32_t mode;
 341    uint32_t video_bitstream_buffer_address_hi;
 342    uint32_t video_bitstream_buffer_address_lo;
 343    uint32_t video_bitstream_buffer_size;
 344    uint32_t video_bitstream_data_offset;
 345 } ruvd_enc_video_bitstream_buffer_t;
 346
 347 typedef struct ruvd_enc_feedback_buffer_s
 348 {
 349    uint32_t mode;
 350    uint32_t feedback_buffer_address_hi;
 351    uint32_t feedback_buffer_address_lo;
 352    uint32_t feedback_buffer_size;
 353    uint32_t feedback_data_size;
 354 } ruvd_enc_feedback_buffer_t;
 355
 356 typedef void (*radeon_uvd_enc_get_buffer) (struct pipe_resource * resource,
 357                                            struct pb_buffer ** handle,
 358                                            struct radeon_surf ** surface);
 359
 360 struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context
 361                                                    *context,
 362                                                    const struct
 363                                                    pipe_video_codec *templat,
 364                                                    struct radeon_winsys *ws,
 365                                                    radeon_uvd_enc_get_buffer
 366                                                    get_buffer);
 367
 368 struct radeon_uvd_enc_pic
 369 {
 370    enum pipe_h265_enc_picture_type picture_type;
 371
 372    unsigned frame_num;
 373    unsigned pic_order_cnt;
 374    unsigned pic_order_cnt_type;
 375    unsigned crop_left;
 376    unsigned crop_right;
 377    unsigned crop_top;
 378    unsigned crop_bottom;
 379    unsigned general_tier_flag;
 380    unsigned general_profile_idc;
 381    unsigned general_level_idc;
 382    unsigned max_poc;
 383    unsigned log2_max_poc;
 384    unsigned chroma_format_idc;
 385    unsigned pic_width_in_luma_samples;
 386    unsigned pic_height_in_luma_samples;
 387    unsigned log2_diff_max_min_luma_coding_block_size;
 388    unsigned log2_min_transform_block_size_minus2;
 389    unsigned log2_diff_max_min_transform_block_size;
 390    unsigned max_transform_hierarchy_depth_inter;
 391    unsigned max_transform_hierarchy_depth_intra;
 392    unsigned log2_parallel_merge_level_minus2;
 393    unsigned bit_depth_luma_minus8;
 394    unsigned bit_depth_chroma_minus8;
 395    unsigned nal_unit_type;
 396    unsigned max_num_merge_cand;
 397
 398    bool not_referenced;
 399    bool is_iframe;
 400    bool is_even_frame;
 401    bool sample_adaptive_offset_enabled_flag;
 402    bool pcm_enabled_flag;
 403    bool sps_temporal_mvp_enabled_flag;
 404
 405    ruvd_enc_task_info_t task_info;
 406    ruvd_enc_session_init_t session_init;
 407    ruvd_enc_layer_control_t layer_ctrl;
 408    ruvd_enc_layer_select_t layer_sel;
 409    ruvd_enc_hevc_slice_control_t hevc_slice_ctrl;
 410    ruvd_enc_hevc_spec_misc_t hevc_spec_misc;
 411    ruvd_enc_rate_ctl_session_init_t rc_session_init;
 412    ruvd_enc_rate_ctl_layer_init_t rc_layer_init;
 413    ruvd_enc_hevc_deblocking_filter_t hevc_deblock;
 414    ruvd_enc_rate_ctl_per_picture_t rc_per_pic;
 415    ruvd_enc_quality_params_t quality_params;
 416    ruvd_enc_encode_context_buffer_t ctx_buf;
 417    ruvd_enc_video_bitstream_buffer_t bit_buf;
 418    ruvd_enc_feedback_buffer_t fb_buf;
 419    ruvd_enc_intra_refresh_t intra_ref;
 420    ruvd_enc_encode_params_t enc_params;
 421 };
 422
 423 struct radeon_uvd_encoder
 424 {
 425    struct pipe_video_codec base;
 426
 427    void (*begin) (struct radeon_uvd_encoder * enc,
 428                   struct pipe_picture_desc * pic);
 429    void (*encode) (struct radeon_uvd_encoder * enc);
 430    void (*destroy) (struct radeon_uvd_encoder * enc);
 431
 432    unsigned stream_handle;
 433
 434    struct pipe_screen *screen;
 435    struct radeon_winsys *ws;
 436    struct radeon_cmdbuf *cs;
 437
 438    radeon_uvd_enc_get_buffer get_buffer;
 439
 440    struct pb_buffer *handle;
 441    struct radeon_surf *luma;
 442    struct radeon_surf *chroma;
 443
 444    struct pb_buffer *bs_handle;
 445    unsigned bs_size;
 446
 447    unsigned cpb_num;
 448
 449    struct rvid_buffer *si;
 450    struct rvid_buffer *fb;
 451    struct rvid_buffer cpb;
 452    struct radeon_uvd_enc_pic enc_pic;
 453
 454    unsigned shifter;
 455    unsigned bits_in_shifter;
 456    unsigned num_zeros;
 457    unsigned byte_index;
 458    unsigned bits_output;
 459    uint32_t total_task_size;
 460    uint32_t *p_task_size;
 461
 462    bool emulation_prevention;
 463    bool need_feedback;
 464 };
 465
 466 void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc);
 467 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen);
 468
 469 #endif // _RADEON_UVD_ENC_H