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[mesa.git] / src / gallium / drivers / radeon / radeon_vce.c
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdio.h>
29
30 #include "pipe/p_video_codec.h"
31
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
34
35 #include "vl/vl_video_buffer.h"
36
37 #include "radeonsi/si_pipe.h"
38 #include "radeon_video.h"
39 #include "radeon_vce.h"
40
41 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
42 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
43 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
44 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
45 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
46 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
47 #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
48 #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
49 #define FW_53 (53 << 24)
50
51 /**
52 * flush commands to the hardware
53 */
54 static void flush(struct rvce_encoder *enc)
55 {
56 enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
57 enc->task_info_idx = 0;
58 enc->bs_idx = 0;
59 }
60
61 #if 0
62 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
63 {
64 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
65 unsigned i = 0;
66 fprintf(stderr, "\n");
67 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
68 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
69 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
70 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
71 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
72 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
73 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
74 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
75 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
76 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
77 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
78 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
79 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
80 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
81 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
82 fprintf(stderr, "\n");
83 enc->ws->buffer_unmap(fb->res->buf);
84 }
85 #endif
86
87 /**
88 * reset the CPB handling
89 */
90 static void reset_cpb(struct rvce_encoder *enc)
91 {
92 unsigned i;
93
94 list_inithead(&enc->cpb_slots);
95 for (i = 0; i < enc->cpb_num; ++i) {
96 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
97 slot->index = i;
98 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
99 slot->frame_num = 0;
100 slot->pic_order_cnt = 0;
101 list_addtail(&slot->list, &enc->cpb_slots);
102 }
103 }
104
105 /**
106 * sort l0 and l1 to the top of the list
107 */
108 static void sort_cpb(struct rvce_encoder *enc)
109 {
110 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
111
112 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
113 if (i->frame_num == enc->pic.ref_idx_l0)
114 l0 = i;
115
116 if (i->frame_num == enc->pic.ref_idx_l1)
117 l1 = i;
118
119 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
120 break;
121
122 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
123 l0 && l1)
124 break;
125 }
126
127 if (l1) {
128 list_del(&l1->list);
129 list_add(&l1->list, &enc->cpb_slots);
130 }
131
132 if (l0) {
133 list_del(&l0->list);
134 list_add(&l0->list, &enc->cpb_slots);
135 }
136 }
137
138 /**
139 * get number of cpbs based on dpb
140 */
141 static unsigned get_cpb_num(struct rvce_encoder *enc)
142 {
143 unsigned w = align(enc->base.width, 16) / 16;
144 unsigned h = align(enc->base.height, 16) / 16;
145 unsigned dpb;
146
147 switch (enc->base.level) {
148 case 10:
149 dpb = 396;
150 break;
151 case 11:
152 dpb = 900;
153 break;
154 case 12:
155 case 13:
156 case 20:
157 dpb = 2376;
158 break;
159 case 21:
160 dpb = 4752;
161 break;
162 case 22:
163 case 30:
164 dpb = 8100;
165 break;
166 case 31:
167 dpb = 18000;
168 break;
169 case 32:
170 dpb = 20480;
171 break;
172 case 40:
173 case 41:
174 dpb = 32768;
175 break;
176 case 42:
177 dpb = 34816;
178 break;
179 case 50:
180 dpb = 110400;
181 break;
182 default:
183 case 51:
184 case 52:
185 dpb = 184320;
186 break;
187 }
188
189 return MIN2(dpb / (w * h), 16);
190 }
191
192 /**
193 * Get the slot for the currently encoded frame
194 */
195 struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc)
196 {
197 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
198 }
199
200 /**
201 * Get the slot for L0
202 */
203 struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc)
204 {
205 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
206 }
207
208 /**
209 * Get the slot for L1
210 */
211 struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc)
212 {
213 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
214 }
215
216 /**
217 * Calculate the offsets into the CPB
218 */
219 void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
220 signed *luma_offset, signed *chroma_offset)
221 {
222 struct si_screen *sscreen = (struct si_screen *)enc->screen;
223 unsigned pitch, vpitch, fsize;
224
225 if (sscreen->info.chip_class < GFX9) {
226 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
227 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
228 } else {
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
230 vpitch = align(enc->luma->u.gfx9.surf_height, 16);
231 }
232 fsize = pitch * (vpitch + vpitch / 2);
233
234 *luma_offset = slot->index * fsize;
235 *chroma_offset = *luma_offset + pitch * vpitch;
236 }
237
238 /**
239 * destroy this video encoder
240 */
241 static void rvce_destroy(struct pipe_video_codec *encoder)
242 {
243 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
244 if (enc->stream_handle) {
245 struct rvid_buffer fb;
246 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
247 enc->fb = &fb;
248 enc->session(enc);
249 enc->destroy(enc);
250 flush(enc);
251 si_vid_destroy_buffer(&fb);
252 }
253 si_vid_destroy_buffer(&enc->cpb);
254 enc->ws->cs_destroy(enc->cs);
255 FREE(enc->cpb_array);
256 FREE(enc);
257 }
258
259 static void rvce_begin_frame(struct pipe_video_codec *encoder,
260 struct pipe_video_buffer *source,
261 struct pipe_picture_desc *picture)
262 {
263 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
264 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
265 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
266
267 bool need_rate_control =
268 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
269 enc->pic.quant_i_frames != pic->quant_i_frames ||
270 enc->pic.quant_p_frames != pic->quant_p_frames ||
271 enc->pic.quant_b_frames != pic->quant_b_frames ||
272 enc->pic.rate_ctrl.target_bitrate != pic->rate_ctrl.target_bitrate;
273
274 enc->pic = *pic;
275 enc->si_get_pic_param(enc, pic);
276
277 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
278 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
279
280 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
281 reset_cpb(enc);
282 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
283 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
284 sort_cpb(enc);
285
286 if (!enc->stream_handle) {
287 struct rvid_buffer fb;
288 enc->stream_handle = si_vid_alloc_stream_handle();
289 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
290 enc->fb = &fb;
291 enc->session(enc);
292 enc->create(enc);
293 enc->config(enc);
294 enc->feedback(enc);
295 flush(enc);
296 //dump_feedback(enc, &fb);
297 si_vid_destroy_buffer(&fb);
298 need_rate_control = false;
299 }
300
301 if (need_rate_control) {
302 enc->session(enc);
303 enc->config(enc);
304 flush(enc);
305 }
306 }
307
308 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
309 struct pipe_video_buffer *source,
310 struct pipe_resource *destination,
311 void **fb)
312 {
313 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
314 enc->get_buffer(destination, &enc->bs_handle, NULL);
315 enc->bs_size = destination->width0;
316
317 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
318 if (!si_vid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
319 RVID_ERR("Can't create feedback buffer.\n");
320 return;
321 }
322 if (!radeon_emitted(enc->cs, 0))
323 enc->session(enc);
324 enc->encode(enc);
325 enc->feedback(enc);
326 }
327
328 static void rvce_end_frame(struct pipe_video_codec *encoder,
329 struct pipe_video_buffer *source,
330 struct pipe_picture_desc *picture)
331 {
332 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
333 struct rvce_cpb_slot *slot = LIST_ENTRY(
334 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
335
336 if (!enc->dual_inst || enc->bs_idx > 1)
337 flush(enc);
338
339 /* update the CPB backtrack with the just encoded frame */
340 slot->picture_type = enc->pic.picture_type;
341 slot->frame_num = enc->pic.frame_num;
342 slot->pic_order_cnt = enc->pic.pic_order_cnt;
343 if (!enc->pic.not_referenced) {
344 list_del(&slot->list);
345 list_add(&slot->list, &enc->cpb_slots);
346 }
347 }
348
349 static void rvce_get_feedback(struct pipe_video_codec *encoder,
350 void *feedback, unsigned *size)
351 {
352 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
353 struct rvid_buffer *fb = feedback;
354
355 if (size) {
356 uint32_t *ptr = enc->ws->buffer_map(
357 fb->res->buf, enc->cs,
358 PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
359
360 if (ptr[1]) {
361 *size = ptr[4] - ptr[9];
362 } else {
363 *size = 0;
364 }
365
366 enc->ws->buffer_unmap(fb->res->buf);
367 }
368 //dump_feedback(enc, fb);
369 si_vid_destroy_buffer(fb);
370 FREE(fb);
371 }
372
373 /**
374 * flush any outstanding command buffers to the hardware
375 */
376 static void rvce_flush(struct pipe_video_codec *encoder)
377 {
378 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
379
380 flush(enc);
381 }
382
383 static void rvce_cs_flush(void *ctx, unsigned flags,
384 struct pipe_fence_handle **fence)
385 {
386 // just ignored
387 }
388
389 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
390 const struct pipe_video_codec *templ,
391 struct radeon_winsys* ws,
392 rvce_get_buffer get_buffer)
393 {
394 struct si_screen *sscreen = (struct si_screen *)context->screen;
395 struct si_context *sctx = (struct si_context*)context;
396 struct rvce_encoder *enc;
397 struct pipe_video_buffer *tmp_buf, templat = {};
398 struct radeon_surf *tmp_surf;
399 unsigned cpb_size;
400
401 if (!sscreen->info.vce_fw_version) {
402 RVID_ERR("Kernel doesn't supports VCE!\n");
403 return NULL;
404
405 } else if (!si_vce_is_fw_version_supported(sscreen)) {
406 RVID_ERR("Unsupported VCE fw version loaded!\n");
407 return NULL;
408 }
409
410 enc = CALLOC_STRUCT(rvce_encoder);
411 if (!enc)
412 return NULL;
413
414 if (sscreen->info.is_amdgpu)
415 enc->use_vm = true;
416 if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
417 sscreen->info.is_amdgpu)
418 enc->use_vui = true;
419 if (sscreen->info.family >= CHIP_TONGA &&
420 sscreen->info.family != CHIP_STONEY &&
421 sscreen->info.family != CHIP_POLARIS11 &&
422 sscreen->info.family != CHIP_POLARIS12 &&
423 sscreen->info.family != CHIP_VEGAM)
424 enc->dual_pipe = true;
425 /* TODO enable B frame with dual instance */
426 if ((sscreen->info.family >= CHIP_TONGA) &&
427 (templ->max_references == 1) &&
428 (sscreen->info.vce_harvest_config == 0))
429 enc->dual_inst = true;
430
431 enc->base = *templ;
432 enc->base.context = context;
433
434 enc->base.destroy = rvce_destroy;
435 enc->base.begin_frame = rvce_begin_frame;
436 enc->base.encode_bitstream = rvce_encode_bitstream;
437 enc->base.end_frame = rvce_end_frame;
438 enc->base.flush = rvce_flush;
439 enc->base.get_feedback = rvce_get_feedback;
440 enc->get_buffer = get_buffer;
441
442 enc->screen = context->screen;
443 enc->ws = ws;
444 enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
445 if (!enc->cs) {
446 RVID_ERR("Can't get command submission context.\n");
447 goto error;
448 }
449
450 templat.buffer_format = PIPE_FORMAT_NV12;
451 templat.width = enc->base.width;
452 templat.height = enc->base.height;
453 templat.interlaced = false;
454 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
455 RVID_ERR("Can't create video buffer.\n");
456 goto error;
457 }
458
459 enc->cpb_num = get_cpb_num(enc);
460 if (!enc->cpb_num)
461 goto error;
462
463 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
464
465 cpb_size = (sscreen->info.chip_class < GFX9) ?
466 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
467 align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
468
469 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
470 align(tmp_surf->u.gfx9.surf_height, 32);
471
472 cpb_size = cpb_size * 3 / 2;
473 cpb_size = cpb_size * enc->cpb_num;
474 if (enc->dual_pipe)
475 cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
476 RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
477 tmp_buf->destroy(tmp_buf);
478 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
479 RVID_ERR("Can't create CPB buffer.\n");
480 goto error;
481 }
482
483 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
484 if (!enc->cpb_array)
485 goto error;
486
487 reset_cpb(enc);
488
489 switch (sscreen->info.vce_fw_version) {
490 case FW_40_2_2:
491 si_vce_40_2_2_init(enc);
492 break;
493
494 case FW_50_0_1:
495 case FW_50_1_2:
496 case FW_50_10_2:
497 case FW_50_17_3:
498 si_vce_50_init(enc);
499 break;
500
501 case FW_52_0_3:
502 case FW_52_4_3:
503 case FW_52_8_3:
504 si_vce_52_init(enc);
505 break;
506
507 default:
508 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) {
509 si_vce_52_init(enc);
510 } else
511 goto error;
512 }
513
514 return &enc->base;
515
516 error:
517 if (enc->cs)
518 enc->ws->cs_destroy(enc->cs);
519
520 si_vid_destroy_buffer(&enc->cpb);
521
522 FREE(enc->cpb_array);
523 FREE(enc);
524 return NULL;
525 }
526
527 /**
528 * check if kernel has the right fw version loaded
529 */
530 bool si_vce_is_fw_version_supported(struct si_screen *sscreen)
531 {
532 switch (sscreen->info.vce_fw_version) {
533 case FW_40_2_2:
534 case FW_50_0_1:
535 case FW_50_1_2:
536 case FW_50_10_2:
537 case FW_50_17_3:
538 case FW_52_0_3:
539 case FW_52_4_3:
540 case FW_52_8_3:
541 return true;
542 default:
543 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53)
544 return true;
545 else
546 return false;
547 }
548 }
549
550 /**
551 * Add the buffer as relocation to the current command submission
552 */
553 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
554 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
555 signed offset)
556 {
557 int reloc_idx;
558
559 reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
560 domain, 0);
561 if (enc->use_vm) {
562 uint64_t addr;
563 addr = enc->ws->buffer_get_virtual_address(buf);
564 addr = addr + offset;
565 RVCE_CS(addr >> 32);
566 RVCE_CS(addr);
567 } else {
568 offset += enc->ws->buffer_get_reloc_offset(buf);
569 RVCE_CS(reloc_idx * 4);
570 RVCE_CS(offset);
571 }
572 }