Merge branch 'wip/nir-vtn' into vulkan
[mesa.git] / src / gallium / drivers / radeon / radeon_vce.c
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <stdio.h>
35
36 #include "pipe/p_video_codec.h"
37
38 #include "util/u_video.h"
39 #include "util/u_memory.h"
40
41 #include "vl/vl_video_buffer.h"
42
43 #include "r600_pipe_common.h"
44 #include "radeon_video.h"
45 #include "radeon_vce.h"
46
47 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
48 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
49 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
50
51 /**
52 * flush commands to the hardware
53 */
54 static void flush(struct rvce_encoder *enc)
55 {
56 enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL, 0);
57 }
58
59 #if 0
60 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
61 {
62 uint32_t *ptr = enc->ws->buffer_map(fb->res->cs_buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
63 unsigned i = 0;
64 fprintf(stderr, "\n");
65 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
66 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
67 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
68 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
69 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
70 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
71 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
72 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
73 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
74 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
75 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
76 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
77 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
78 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
79 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
80 fprintf(stderr, "\n");
81 enc->ws->buffer_unmap(fb->res->cs_buf);
82 }
83 #endif
84
85 /**
86 * reset the CPB handling
87 */
88 static void reset_cpb(struct rvce_encoder *enc)
89 {
90 unsigned i;
91
92 LIST_INITHEAD(&enc->cpb_slots);
93 for (i = 0; i < enc->cpb_num; ++i) {
94 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
95 slot->index = i;
96 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
97 slot->frame_num = 0;
98 slot->pic_order_cnt = 0;
99 LIST_ADDTAIL(&slot->list, &enc->cpb_slots);
100 }
101 }
102
103 /**
104 * sort l0 and l1 to the top of the list
105 */
106 static void sort_cpb(struct rvce_encoder *enc)
107 {
108 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
109
110 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
111 if (i->frame_num == enc->pic.ref_idx_l0)
112 l0 = i;
113
114 if (i->frame_num == enc->pic.ref_idx_l1)
115 l1 = i;
116
117 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
118 break;
119
120 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
121 l0 && l1)
122 break;
123 }
124
125 if (l1) {
126 LIST_DEL(&l1->list);
127 LIST_ADD(&l1->list, &enc->cpb_slots);
128 }
129
130 if (l0) {
131 LIST_DEL(&l0->list);
132 LIST_ADD(&l0->list, &enc->cpb_slots);
133 }
134 }
135
136 /**
137 * get number of cpbs based on dpb
138 */
139 static unsigned get_cpb_num(struct rvce_encoder *enc)
140 {
141 unsigned w = align(enc->base.width, 16) / 16;
142 unsigned h = align(enc->base.height, 16) / 16;
143 unsigned dpb;
144
145 switch (enc->base.level) {
146 case 10:
147 dpb = 396;
148 break;
149 case 11:
150 dpb = 900;
151 break;
152 case 12:
153 case 13:
154 case 20:
155 dpb = 2376;
156 break;
157 case 21:
158 dpb = 4752;
159 break;
160 case 22:
161 case 30:
162 dpb = 8100;
163 break;
164 case 31:
165 dpb = 18000;
166 break;
167 case 32:
168 dpb = 20480;
169 break;
170 case 40:
171 case 41:
172 dpb = 32768;
173 break;
174 default:
175 case 42:
176 dpb = 34816;
177 break;
178 case 50:
179 dpb = 110400;
180 break;
181 case 51:
182 dpb = 184320;
183 break;
184 }
185
186 return MIN2(dpb / (w * h), 16);
187 }
188
189 /**
190 * Get the slot for the currently encoded frame
191 */
192 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
193 {
194 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
195 }
196
197 /**
198 * Get the slot for L0
199 */
200 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
201 {
202 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
203 }
204
205 /**
206 * Get the slot for L1
207 */
208 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
209 {
210 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
211 }
212
213 /**
214 * Calculate the offsets into the CPB
215 */
216 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
217 unsigned *luma_offset, unsigned *chroma_offset)
218 {
219 unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
220 unsigned vpitch = align(enc->luma->npix_y, 16);
221 unsigned fsize = pitch * (vpitch + vpitch / 2);
222
223 *luma_offset = slot->index * fsize;
224 *chroma_offset = *luma_offset + pitch * vpitch;
225 }
226
227 /**
228 * destroy this video encoder
229 */
230 static void rvce_destroy(struct pipe_video_codec *encoder)
231 {
232 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
233 if (enc->stream_handle) {
234 struct rvid_buffer fb;
235 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
236 enc->fb = &fb;
237 enc->session(enc);
238 enc->feedback(enc);
239 enc->destroy(enc);
240 flush(enc);
241 rvid_destroy_buffer(&fb);
242 }
243 rvid_destroy_buffer(&enc->cpb);
244 enc->ws->cs_destroy(enc->cs);
245 FREE(enc->cpb_array);
246 FREE(enc);
247 }
248
249 static void rvce_begin_frame(struct pipe_video_codec *encoder,
250 struct pipe_video_buffer *source,
251 struct pipe_picture_desc *picture)
252 {
253 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
254 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
255 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
256
257 bool need_rate_control =
258 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
259 enc->pic.quant_i_frames != pic->quant_i_frames ||
260 enc->pic.quant_p_frames != pic->quant_p_frames ||
261 enc->pic.quant_b_frames != pic->quant_b_frames;
262
263 enc->pic = *pic;
264
265 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
266 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
267
268 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
269 reset_cpb(enc);
270 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
271 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
272 sort_cpb(enc);
273
274 if (!enc->stream_handle) {
275 struct rvid_buffer fb;
276 enc->stream_handle = rvid_alloc_stream_handle();
277 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
278 enc->fb = &fb;
279 enc->session(enc);
280 enc->create(enc);
281 enc->rate_control(enc);
282 need_rate_control = false;
283 enc->config_extension(enc);
284 enc->motion_estimation(enc);
285 enc->rdo(enc);
286 if (enc->use_vui)
287 enc->vui(enc);
288 enc->pic_control(enc);
289 enc->feedback(enc);
290 flush(enc);
291 //dump_feedback(enc, &fb);
292 rvid_destroy_buffer(&fb);
293 }
294
295 enc->session(enc);
296
297 if (need_rate_control)
298 enc->rate_control(enc);
299 }
300
301 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
302 struct pipe_video_buffer *source,
303 struct pipe_resource *destination,
304 void **fb)
305 {
306 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
307 enc->get_buffer(destination, &enc->bs_handle, NULL);
308 enc->bs_size = destination->width0;
309
310 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
311 if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
312 RVID_ERR("Can't create feedback buffer.\n");
313 return;
314 }
315 enc->encode(enc);
316 enc->feedback(enc);
317 }
318
319 static void rvce_end_frame(struct pipe_video_codec *encoder,
320 struct pipe_video_buffer *source,
321 struct pipe_picture_desc *picture)
322 {
323 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
324 struct rvce_cpb_slot *slot = LIST_ENTRY(
325 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
326
327 flush(enc);
328
329 /* update the CPB backtrack with the just encoded frame */
330 slot->picture_type = enc->pic.picture_type;
331 slot->frame_num = enc->pic.frame_num;
332 slot->pic_order_cnt = enc->pic.pic_order_cnt;
333 if (!enc->pic.not_referenced) {
334 LIST_DEL(&slot->list);
335 LIST_ADD(&slot->list, &enc->cpb_slots);
336 }
337 }
338
339 static void rvce_get_feedback(struct pipe_video_codec *encoder,
340 void *feedback, unsigned *size)
341 {
342 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
343 struct rvid_buffer *fb = feedback;
344
345 if (size) {
346 uint32_t *ptr = enc->ws->buffer_map(fb->res->cs_buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
347
348 if (ptr[1]) {
349 *size = ptr[4] - ptr[9];
350 } else {
351 *size = 0;
352 }
353
354 enc->ws->buffer_unmap(fb->res->cs_buf);
355 }
356 //dump_feedback(enc, fb);
357 rvid_destroy_buffer(fb);
358 FREE(fb);
359 }
360
361 /**
362 * flush any outstanding command buffers to the hardware
363 */
364 static void rvce_flush(struct pipe_video_codec *encoder)
365 {
366 }
367
368 static void rvce_cs_flush(void *ctx, unsigned flags,
369 struct pipe_fence_handle **fence)
370 {
371 // just ignored
372 }
373
374 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
375 const struct pipe_video_codec *templ,
376 struct radeon_winsys* ws,
377 rvce_get_buffer get_buffer)
378 {
379 struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
380 struct rvce_encoder *enc;
381 struct pipe_video_buffer *tmp_buf, templat = {};
382 struct radeon_surf *tmp_surf;
383 unsigned cpb_size;
384
385 if (!rscreen->info.vce_fw_version) {
386 RVID_ERR("Kernel doesn't supports VCE!\n");
387 return NULL;
388
389 } else if (!rvce_is_fw_version_supported(rscreen)) {
390 RVID_ERR("Unsupported VCE fw version loaded!\n");
391 return NULL;
392 }
393
394 enc = CALLOC_STRUCT(rvce_encoder);
395 if (!enc)
396 return NULL;
397
398 if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
399 enc->use_vui = true;
400
401 enc->base = *templ;
402 enc->base.context = context;
403
404 enc->base.destroy = rvce_destroy;
405 enc->base.begin_frame = rvce_begin_frame;
406 enc->base.encode_bitstream = rvce_encode_bitstream;
407 enc->base.end_frame = rvce_end_frame;
408 enc->base.flush = rvce_flush;
409 enc->base.get_feedback = rvce_get_feedback;
410 enc->get_buffer = get_buffer;
411
412 enc->screen = context->screen;
413 enc->ws = ws;
414 enc->cs = ws->cs_create(ws, RING_VCE, rvce_cs_flush, enc, NULL);
415 if (!enc->cs) {
416 RVID_ERR("Can't get command submission context.\n");
417 goto error;
418 }
419
420 templat.buffer_format = PIPE_FORMAT_NV12;
421 templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
422 templat.width = enc->base.width;
423 templat.height = enc->base.height;
424 templat.interlaced = false;
425 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
426 RVID_ERR("Can't create video buffer.\n");
427 goto error;
428 }
429
430 enc->cpb_num = get_cpb_num(enc);
431 if (!enc->cpb_num)
432 goto error;
433
434 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
435 cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
436 cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
437 cpb_size = cpb_size * 3 / 2;
438 cpb_size = cpb_size * enc->cpb_num;
439 tmp_buf->destroy(tmp_buf);
440 if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
441 RVID_ERR("Can't create CPB buffer.\n");
442 goto error;
443 }
444
445 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
446 if (!enc->cpb_array)
447 goto error;
448
449 reset_cpb(enc);
450
451 switch (rscreen->info.vce_fw_version) {
452 case FW_40_2_2:
453 radeon_vce_40_2_2_init(enc);
454 break;
455
456 case FW_50_0_1:
457 case FW_50_1_2:
458 radeon_vce_50_init(enc);
459 break;
460
461 default:
462 goto error;
463 }
464
465 return &enc->base;
466
467 error:
468 if (enc->cs)
469 enc->ws->cs_destroy(enc->cs);
470
471 rvid_destroy_buffer(&enc->cpb);
472
473 FREE(enc->cpb_array);
474 FREE(enc);
475 return NULL;
476 }
477
478 /**
479 * check if kernel has the right fw version loaded
480 */
481 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
482 {
483 return rscreen->info.vce_fw_version == FW_40_2_2 ||
484 rscreen->info.vce_fw_version == FW_50_0_1 ||
485 rscreen->info.vce_fw_version == FW_50_1_2;
486 }