1 /**************************************************************************
3 * Copyright 2013 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
31 #include "util/list.h"
33 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
34 #define RVCE_BEGIN(cmd) { \
35 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
37 #define RVCE_READ(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
38 #define RVCE_WRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
39 #define RVCE_READWRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
40 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
42 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
43 #define RVCE_MAX_AUX_BUFFER_NUM 4
47 /* driver dependent callback */
48 typedef void (*rvce_get_buffer
)(struct pipe_resource
*resource
,
49 struct pb_buffer
**handle
,
50 struct radeon_surf
**surface
);
52 /* Coded picture buffer slot */
53 struct rvce_cpb_slot
{
54 struct list_head list
;
57 enum pipe_h264_enc_picture_type picture_type
;
59 unsigned pic_order_cnt
;
62 struct rvce_rate_control
{
64 uint32_t target_bitrate
;
65 uint32_t peak_bitrate
;
66 uint32_t frame_rate_num
;
68 uint32_t quant_i_frames
;
69 uint32_t quant_p_frames
;
70 uint32_t quant_b_frames
;
71 uint32_t vbv_buffer_size
;
72 uint32_t frame_rate_den
;
75 uint32_t qp_initial_mode
;
76 uint32_t target_bits_picture
;
77 uint32_t peak_bits_picture_integer
;
78 uint32_t peak_bits_picture_fraction
;
81 uint32_t skip_frame_enable
;
82 uint32_t fill_data_enable
;
84 uint32_t b_pics_delta_qp
;
85 uint32_t ref_b_pics_delta_qp
;
86 uint32_t rc_reinit_disable
;
87 uint32_t enc_lcvbr_init_qp_flag
;
88 uint32_t lcvbrsatd_based_nonlinear_bit_budget_flag
;
91 struct rvce_motion_estimation
{
92 uint32_t enc_ime_decimation_search
;
93 uint32_t motion_est_half_pixel
;
94 uint32_t motion_est_quarter_pixel
;
95 uint32_t disable_favor_pmv_point
;
96 uint32_t force_zero_point_center
;
98 uint32_t enc_search_range_x
;
99 uint32_t enc_search_range_y
;
100 uint32_t enc_search1_range_x
;
101 uint32_t enc_search1_range_y
;
102 uint32_t disable_16x16_frame1
;
103 uint32_t disable_satd
;
105 uint32_t enc_disable_sub_mode
;
106 uint32_t enc_ime_skip_x
;
107 uint32_t enc_ime_skip_y
;
108 uint32_t enc_en_ime_overw_dis_subm
;
109 uint32_t enc_ime_overw_dis_subm_no
;
110 uint32_t enc_ime2_search_range_x
;
111 uint32_t enc_ime2_search_range_y
;
112 uint32_t parallel_mode_speedup_enable
;
113 uint32_t fme0_enc_disable_sub_mode
;
114 uint32_t fme1_enc_disable_sub_mode
;
115 uint32_t ime_sw_speedup_enable
;
118 struct rvce_pic_control
{
119 uint32_t enc_use_constrained_intra_pred
;
120 uint32_t enc_cabac_enable
;
121 uint32_t enc_cabac_idc
;
122 uint32_t enc_loop_filter_disable
;
123 int32_t enc_lf_beta_offset
;
124 int32_t enc_lf_alpha_c0_offset
;
125 uint32_t enc_crop_left_offset
;
126 uint32_t enc_crop_right_offset
;
127 uint32_t enc_crop_top_offset
;
128 uint32_t enc_crop_bottom_offset
;
129 uint32_t enc_num_mbs_per_slice
;
130 uint32_t enc_intra_refresh_num_mbs_per_slot
;
131 uint32_t enc_force_intra_refresh
;
132 uint32_t enc_force_imb_period
;
133 uint32_t enc_pic_order_cnt_type
;
134 uint32_t log2_max_pic_order_cnt_lsb_minus4
;
137 uint32_t enc_constraint_set_flags
;
138 uint32_t enc_b_pic_pattern
;
139 uint32_t weight_pred_mode_b_picture
;
140 uint32_t enc_number_of_reference_frames
;
141 uint32_t enc_max_num_ref_frames
;
142 uint32_t enc_num_default_active_ref_l0
;
143 uint32_t enc_num_default_active_ref_l1
;
144 uint32_t enc_slice_mode
;
145 uint32_t enc_max_slice_size
;
148 struct rvce_task_info
{
149 uint32_t offset_of_next_task_info
;
150 uint32_t task_operation
;
151 uint32_t reference_picture_dependency
;
152 uint32_t collocate_flag_dependency
;
153 uint32_t feedback_index
;
154 uint32_t video_bitstream_ring_index
;
157 struct rvce_feedback_buf_pkg
{
158 uint32_t feedback_ring_address_hi
;
159 uint32_t feedback_ring_address_lo
;
160 uint32_t feedback_ring_size
;
164 uint32_t enc_disable_tbe_pred_i_frame
;
165 uint32_t enc_disable_tbe_pred_p_frame
;
166 uint32_t use_fme_interpol_y
;
167 uint32_t use_fme_interpol_uv
;
168 uint32_t use_fme_intrapol_y
;
169 uint32_t use_fme_intrapol_uv
;
170 uint32_t use_fme_interpol_y_1
;
171 uint32_t use_fme_interpol_uv_1
;
172 uint32_t use_fme_intrapol_y_1
;
173 uint32_t use_fme_intrapol_uv_1
;
174 uint32_t enc_16x16_cost_adj
;
175 uint32_t enc_skip_cost_adj
;
176 uint32_t enc_force_16x16_skip
;
177 uint32_t enc_disable_threshold_calc_a
;
178 uint32_t enc_luma_coeff_cost
;
179 uint32_t enc_luma_mb_coeff_cost
;
180 uint32_t enc_chroma_coeff_cost
;
184 uint32_t aspect_ratio_info_present_flag
;
185 uint32_t aspect_ratio_idc
;
188 uint32_t overscan_info_present_flag
;
189 uint32_t overscan_Approp_flag
;
190 uint32_t video_signal_type_present_flag
;
191 uint32_t video_format
;
192 uint32_t video_full_range_flag
;
193 uint32_t color_description_present_flag
;
195 uint32_t transfer_char
;
196 uint32_t matrix_coef
;
197 uint32_t chroma_loc_info_present_flag
;
198 uint32_t chroma_loc_top
;
199 uint32_t chroma_loc_bottom
;
200 uint32_t timing_info_present_flag
;
201 uint32_t num_units_in_tick
;
203 uint32_t fixed_frame_rate_flag
;
204 uint32_t nal_hrd_parameters_present_flag
;
205 uint32_t cpb_cnt_minus1
;
206 uint32_t bit_rate_scale
;
207 uint32_t cpb_size_scale
;
208 uint32_t bit_rate_value_minus
;
209 uint32_t cpb_size_value_minus
;
211 uint32_t initial_cpb_removal_delay_length_minus1
;
212 uint32_t cpb_removal_delay_length_minus1
;
213 uint32_t dpb_output_delay_length_minus1
;
214 uint32_t time_offset_length
;
215 uint32_t low_delay_hrd_flag
;
216 uint32_t pic_struct_present_flag
;
217 uint32_t bitstream_restriction_present_flag
;
218 uint32_t motion_vectors_over_pic_boundaries_flag
;
219 uint32_t max_bytes_per_pic_denom
;
220 uint32_t max_bits_per_mb_denom
;
221 uint32_t log2_max_mv_length_hori
;
222 uint32_t log2_max_mv_length_vert
;
223 uint32_t num_reorder_frames
;
224 uint32_t max_dec_frame_buffering
;
227 struct rvce_enc_operation
{
228 uint32_t insert_headers
;
229 uint32_t picture_structure
;
230 uint32_t allowed_max_bitstream_size
;
231 uint32_t force_refresh_map
;
233 uint32_t end_of_sequence
;
234 uint32_t end_of_stream
;
235 uint32_t input_picture_luma_address_hi
;
236 uint32_t input_picture_luma_address_lo
;
237 uint32_t input_picture_chroma_address_hi
;
238 uint32_t input_picture_chroma_address_lo
;
239 uint32_t enc_input_frame_y_pitch
;
240 uint32_t enc_input_pic_luma_pitch
;
241 uint32_t enc_input_pic_chroma_pitch
;;
242 uint32_t enc_input_pic_addr_array
;
243 uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload
;
244 uint32_t enc_input_pic_tile_config
;
245 uint32_t enc_pic_type
;
246 uint32_t enc_idr_flag
;
247 uint32_t enc_idr_pic_id
;
248 uint32_t enc_mgs_key_pic
;
249 uint32_t enc_reference_flag
;
250 uint32_t enc_temporal_layer_index
;
251 uint32_t num_ref_idx_active_override_flag
;
252 uint32_t num_ref_idx_l0_active_minus1
;
253 uint32_t num_ref_idx_l1_active_minus1
;
254 uint32_t enc_ref_list_modification_op
;
255 uint32_t enc_ref_list_modification_num
;
256 uint32_t enc_decoded_picture_marking_op
;
257 uint32_t enc_decoded_picture_marking_num
;
258 uint32_t enc_decoded_picture_marking_idx
;
259 uint32_t enc_decoded_ref_base_picture_marking_op
;
260 uint32_t enc_decoded_ref_base_picture_marking_num
;
261 uint32_t l0_picture_structure
;
262 uint32_t l0_enc_pic_type
;
263 uint32_t l0_frame_number
;
264 uint32_t l0_picture_order_count
;
265 uint32_t l0_luma_offset
;
266 uint32_t l0_chroma_offset
;
267 uint32_t l1_picture_structure
;
268 uint32_t l1_enc_pic_type
;
269 uint32_t l1_frame_number
;
270 uint32_t l1_picture_order_count
;
271 uint32_t l1_luma_offset
;
272 uint32_t l1_chroma_offset
;
273 uint32_t enc_reconstructed_luma_offset
;
274 uint32_t enc_reconstructed_chroma_offset
;;
275 uint32_t enc_coloc_buffer_offset
;
276 uint32_t enc_reconstructed_ref_base_picture_luma_offset
;
277 uint32_t enc_reconstructed_ref_base_picture_chroma_offset
;
278 uint32_t enc_reference_ref_base_picture_luma_offset
;
279 uint32_t enc_reference_ref_base_picture_chroma_offset
;
280 uint32_t picture_count
;
281 uint32_t frame_number
;
282 uint32_t picture_order_count
;
283 uint32_t num_i_pic_remain_in_rcgop
;
284 uint32_t num_p_pic_remain_in_rcgop
;
285 uint32_t num_b_pic_remain_in_rcgop
;
286 uint32_t num_ir_pic_remain_in_rcgop
;
287 uint32_t enable_intra_refresh
;
288 uint32_t aq_variance_en
;
289 uint32_t aq_block_size
;
290 uint32_t aq_mb_variance_sel
;
291 uint32_t aq_frame_variance_sel
;
297 uint32_t context_in_sfb
;
300 struct rvce_enc_create
{
301 uint32_t enc_use_circular_buffer
;
302 uint32_t enc_profile
;
304 uint32_t enc_pic_struct_restriction
;
305 uint32_t enc_image_width
;
306 uint32_t enc_image_height
;
307 uint32_t enc_ref_pic_luma_pitch
;
308 uint32_t enc_ref_pic_chroma_pitch
;
309 uint32_t enc_ref_y_height_in_qw
;
310 uint32_t enc_ref_pic_addr_array_enc_pic_struct_restriction_disable_rdo
;
311 uint32_t enc_pre_encode_context_buffer_offset
;
312 uint32_t enc_pre_encode_input_luma_buffer_offset
;
313 uint32_t enc_pre_encode_input_chroma_buffer_offset
;
314 uint32_t enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity
;
317 struct rvce_config_ext
{
318 uint32_t enc_enable_perf_logging
;
321 struct rvce_h264_enc_pic
{
322 struct rvce_rate_control rc
;
323 struct rvce_motion_estimation me
;
324 struct rvce_pic_control pc
;
325 struct rvce_task_info ti
;
326 struct rvce_feedback_buf_pkg fb
;
329 struct rvce_enc_operation eo
;
330 struct rvce_enc_create ec
;
331 struct rvce_config_ext ce
;
333 unsigned quant_i_frames
;
334 unsigned quant_p_frames
;
335 unsigned quant_b_frames
;
337 enum pipe_h264_enc_picture_type picture_type
;
339 unsigned frame_num_cnt
;
345 unsigned pic_order_cnt
;
348 unsigned addrmode_arraymode_disrdo_distwoinstants
;
352 bool has_ref_pic_list
;
354 unsigned int ref_pic_list_0
[32];
355 unsigned int ref_pic_list_1
[32];
356 unsigned int frame_idx
[32];
359 /* VCE encoder representation */
360 struct rvce_encoder
{
361 struct pipe_video_codec base
;
363 /* version specific packets */
364 void (*session
)(struct rvce_encoder
*enc
);
365 void (*create
)(struct rvce_encoder
*enc
);
366 void (*feedback
)(struct rvce_encoder
*enc
);
367 void (*rate_control
)(struct rvce_encoder
*enc
);
368 void (*config_extension
)(struct rvce_encoder
*enc
);
369 void (*pic_control
)(struct rvce_encoder
*enc
);
370 void (*motion_estimation
)(struct rvce_encoder
*enc
);
371 void (*rdo
)(struct rvce_encoder
*enc
);
372 void (*vui
)(struct rvce_encoder
*enc
);
373 void (*config
)(struct rvce_encoder
*enc
);
374 void (*encode
)(struct rvce_encoder
*enc
);
375 void (*destroy
)(struct rvce_encoder
*enc
);
376 void (*task_info
)(struct rvce_encoder
*enc
, uint32_t op
,
377 uint32_t dep
, uint32_t fb_idx
,
380 unsigned stream_handle
;
382 struct pipe_screen
*screen
;
383 struct radeon_winsys
* ws
;
384 struct radeon_cmdbuf
* cs
;
386 rvce_get_buffer get_buffer
;
388 struct pb_buffer
* handle
;
389 struct radeon_surf
* luma
;
390 struct radeon_surf
* chroma
;
392 struct pb_buffer
* bs_handle
;
395 struct rvce_cpb_slot
*cpb_array
;
396 struct list_head cpb_slots
;
399 struct rvid_buffer
*fb
;
400 struct rvid_buffer cpb
;
401 struct pipe_h264_enc_picture_desc pic
;
402 struct rvce_h264_enc_pic enc_pic
;
404 unsigned task_info_idx
;
413 /* CPB handling functions */
414 struct rvce_cpb_slot
*si_current_slot(struct rvce_encoder
*enc
);
415 struct rvce_cpb_slot
*si_l0_slot(struct rvce_encoder
*enc
);
416 struct rvce_cpb_slot
*si_l1_slot(struct rvce_encoder
*enc
);
417 void si_vce_frame_offset(struct rvce_encoder
*enc
, struct rvce_cpb_slot
*slot
,
418 signed *luma_offset
, signed *chroma_offset
);
420 struct pipe_video_codec
*si_vce_create_encoder(struct pipe_context
*context
,
421 const struct pipe_video_codec
*templat
,
422 struct radeon_winsys
* ws
,
423 rvce_get_buffer get_buffer
);
425 bool si_vce_is_fw_version_supported(struct si_screen
*sscreen
);
427 void si_vce_add_buffer(struct rvce_encoder
*enc
, struct pb_buffer
*buf
,
428 enum radeon_bo_usage usage
, enum radeon_bo_domain domain
,
431 /* init vce fw 40.2.2 specific callbacks */
432 void si_vce_40_2_2_init(struct rvce_encoder
*enc
);
434 /* init vce fw 50 specific callbacks */
435 void si_vce_50_init(struct rvce_encoder
*enc
);
437 /* init vce fw 52 specific callbacks */
438 void si_vce_52_init(struct rvce_encoder
*enc
);
440 /* version specific function for getting parameters */
441 void (*si_get_pic_param
)(struct rvce_encoder
*enc
,
442 struct pipe_h264_enc_picture_desc
*pic
);
444 /* get parameters for vce 40.2.2 */
445 void si_vce_40_2_2_get_param(struct rvce_encoder
*enc
,
446 struct pipe_h264_enc_picture_desc
*pic
);
448 /* get parameters for vce 50 */
449 void si_vce_50_get_param(struct rvce_encoder
*enc
,
450 struct pipe_h264_enc_picture_desc
*pic
);
452 /* get parameters for vce 52 */
453 void si_vce_52_get_param(struct rvce_encoder
*enc
,
454 struct pipe_h264_enc_picture_desc
*pic
);