1 /**************************************************************************
3 * Copyright 2013 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
36 #include "pipe/p_video_codec.h"
38 #include "util/u_video.h"
39 #include "util/u_memory.h"
41 #include "vl/vl_video_buffer.h"
43 #include "r600_pipe_common.h"
44 #include "radeon_video.h"
45 #include "radeon_vce.h"
47 static void rate_control(struct rvce_encoder
*enc
)
49 RVCE_BEGIN(0x04000005); // rate control
50 RVCE_CS(enc
->pic
.rate_ctrl
.rate_ctrl_method
); // encRateControlMethod
51 RVCE_CS(enc
->pic
.rate_ctrl
.target_bitrate
); // encRateControlTargetBitRate
52 RVCE_CS(enc
->pic
.rate_ctrl
.peak_bitrate
); // encRateControlPeakBitRate
53 RVCE_CS(enc
->pic
.rate_ctrl
.frame_rate_num
); // encRateControlFrameRateNum
54 RVCE_CS(0x00000000); // encGOPSize
55 RVCE_CS(enc
->pic
.quant_i_frames
); // encQP_I
56 RVCE_CS(enc
->pic
.quant_p_frames
); // encQP_P
57 RVCE_CS(enc
->pic
.quant_b_frames
); // encQP_B
58 RVCE_CS(enc
->pic
.rate_ctrl
.vbv_buffer_size
); // encVBVBufferSize
59 RVCE_CS(enc
->pic
.rate_ctrl
.frame_rate_den
); // encRateControlFrameRateDen
60 RVCE_CS(0x00000000); // encVBVBufferLevel
61 RVCE_CS(0x00000000); // encMaxAUSize
62 RVCE_CS(0x00000000); // encQPInitialMode
63 RVCE_CS(enc
->pic
.rate_ctrl
.target_bits_picture
); // encTargetBitsPerPicture
64 RVCE_CS(enc
->pic
.rate_ctrl
.peak_bits_picture_integer
); // encPeakBitsPerPictureInteger
65 RVCE_CS(enc
->pic
.rate_ctrl
.peak_bits_picture_fraction
); // encPeakBitsPerPictureFractional
66 RVCE_CS(0x00000000); // encMinQP
67 RVCE_CS(0x00000033); // encMaxQP
68 RVCE_CS(0x00000000); // encSkipFrameEnable
69 RVCE_CS(0x00000000); // encFillerDataEnable
70 RVCE_CS(0x00000000); // encEnforceHRD
71 RVCE_CS(0x00000000); // encBPicsDeltaQP
72 RVCE_CS(0x00000000); // encReferenceBPicsDeltaQP
73 RVCE_CS(0x00000000); // encRateControlReInitDisable
74 RVCE_CS(0x00000000); // encLCVBRInitQPFlag
75 RVCE_CS(0x00000000); // encLCVBRSATDBasedNonlinearBitBudgetFlag
79 static void encode(struct rvce_encoder
*enc
)
82 unsigned luma_offset
, chroma_offset
;
84 enc
->task_info(enc
, 0x00000003, 0, 0, 0);
86 RVCE_BEGIN(0x05000001); // context buffer
87 RVCE_READWRITE(enc
->cpb
.res
->cs_buf
, enc
->cpb
.res
->domains
, 0); // encodeContextAddressHi/Lo
90 RVCE_BEGIN(0x05000004); // video bitstream buffer
91 RVCE_WRITE(enc
->bs_handle
, RADEON_DOMAIN_GTT
, 0); // videoBitstreamRingAddressHi/Lo
92 RVCE_CS(enc
->bs_size
); // videoBitstreamRingSize
96 unsigned aux_offset
= enc
->cpb
.res
->buf
->size
-
97 RVCE_MAX_AUX_BUFFER_NUM
* RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE
* 2;
98 RVCE_BEGIN(0x05000002); // auxiliary buffer
99 for (i
= 0; i
< 8; ++i
) {
101 aux_offset
+= RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE
;
103 for (i
= 0; i
< 8; ++i
)
104 RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE
);
108 RVCE_BEGIN(0x03000001); // encode
109 RVCE_CS(enc
->pic
.frame_num
? 0x0 : 0x11); // insertHeaders
110 RVCE_CS(0x00000000); // pictureStructure
111 RVCE_CS(enc
->bs_size
); // allowedMaxBitstreamSize
112 RVCE_CS(0x00000000); // forceRefreshMap
113 RVCE_CS(0x00000000); // insertAUD
114 RVCE_CS(0x00000000); // endOfSequence
115 RVCE_CS(0x00000000); // endOfStream
116 RVCE_READ(enc
->handle
, RADEON_DOMAIN_VRAM
,
117 enc
->luma
->level
[0].offset
); // inputPictureLumaAddressHi/Lo
118 RVCE_READ(enc
->handle
, RADEON_DOMAIN_VRAM
,
119 enc
->chroma
->level
[0].offset
); // inputPictureChromaAddressHi/Lo
120 RVCE_CS(align(enc
->luma
->npix_y
, 16)); // encInputFrameYPitch
121 RVCE_CS(enc
->luma
->level
[0].pitch_bytes
); // encInputPicLumaPitch
122 RVCE_CS(enc
->chroma
->level
[0].pitch_bytes
); // encInputPicChromaPitch
124 RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
126 RVCE_CS(0x00010000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
127 RVCE_CS(0x00000000); // encInputPicTileConfig
128 RVCE_CS(enc
->pic
.picture_type
); // encPicType
129 RVCE_CS(enc
->pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_IDR
); // encIdrFlag
130 RVCE_CS(0x00000000); // encIdrPicId
131 RVCE_CS(0x00000000); // encMGSKeyPic
132 RVCE_CS(!enc
->pic
.not_referenced
); // encReferenceFlag
133 RVCE_CS(0x00000000); // encTemporalLayerIndex
134 RVCE_CS(0x00000000); // num_ref_idx_active_override_flag
135 RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1
136 RVCE_CS(0x00000000); // num_ref_idx_l1_active_minus1
138 i
= enc
->pic
.frame_num
- enc
->pic
.ref_idx_l0
;
139 if (i
> 1 && enc
->pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_P
) {
140 RVCE_CS(0x00000001); // encRefListModificationOp
141 RVCE_CS(i
- 1); // encRefListModificationNum
143 RVCE_CS(0x00000000); // encRefListModificationOp
144 RVCE_CS(0x00000000); // encRefListModificationNum
147 for (i
= 0; i
< 3; ++i
) {
148 RVCE_CS(0x00000000); // encRefListModificationOp
149 RVCE_CS(0x00000000); // encRefListModificationNum
151 for (i
= 0; i
< 4; ++i
) {
152 RVCE_CS(0x00000000); // encDecodedPictureMarkingOp
153 RVCE_CS(0x00000000); // encDecodedPictureMarkingNum
154 RVCE_CS(0x00000000); // encDecodedPictureMarkingIdx
155 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingOp
156 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingNum
159 // encReferencePictureL0[0]
160 RVCE_CS(0x00000000); // pictureStructure
161 if(enc
->pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_P
||
162 enc
->pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_B
) {
163 struct rvce_cpb_slot
*l0
= l0_slot(enc
);
164 rvce_frame_offset(enc
, l0
, &luma_offset
, &chroma_offset
);
165 RVCE_CS(l0
->picture_type
); // encPicType
166 RVCE_CS(l0
->frame_num
); // frameNumber
167 RVCE_CS(l0
->pic_order_cnt
); // pictureOrderCount
168 RVCE_CS(luma_offset
); // lumaOffset
169 RVCE_CS(chroma_offset
); // chromaOffset
171 RVCE_CS(0x00000000); // encPicType
172 RVCE_CS(0x00000000); // frameNumber
173 RVCE_CS(0x00000000); // pictureOrderCount
174 RVCE_CS(0xffffffff); // lumaOffset
175 RVCE_CS(0xffffffff); // chromaOffset
178 // encReferencePictureL0[1]
179 RVCE_CS(0x00000000); // pictureStructure
180 RVCE_CS(0x00000000); // encPicType
181 RVCE_CS(0x00000000); // frameNumber
182 RVCE_CS(0x00000000); // pictureOrderCount
183 RVCE_CS(0xffffffff); // lumaOffset
184 RVCE_CS(0xffffffff); // chromaOffset
186 // encReferencePictureL1[0]
187 RVCE_CS(0x00000000); // pictureStructure
188 if(enc
->pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_B
) {
189 struct rvce_cpb_slot
*l1
= l1_slot(enc
);
190 rvce_frame_offset(enc
, l1
, &luma_offset
, &chroma_offset
);
191 RVCE_CS(l1
->picture_type
); // encPicType
192 RVCE_CS(l1
->frame_num
); // frameNumber
193 RVCE_CS(l1
->pic_order_cnt
); // pictureOrderCount
194 RVCE_CS(luma_offset
); // lumaOffset
195 RVCE_CS(chroma_offset
); // chromaOffset
197 RVCE_CS(0x00000000); // encPicType
198 RVCE_CS(0x00000000); // frameNumber
199 RVCE_CS(0x00000000); // pictureOrderCount
200 RVCE_CS(0xffffffff); // lumaOffset
201 RVCE_CS(0xffffffff); // chromaOffset
204 rvce_frame_offset(enc
, current_slot(enc
), &luma_offset
, &chroma_offset
);
205 RVCE_CS(luma_offset
); // encReconstructedLumaOffset
206 RVCE_CS(chroma_offset
); // encReconstructedChromaOffset
207 RVCE_CS(0x00000000); // encColocBufferOffset
208 RVCE_CS(0x00000000); // encReconstructedRefBasePictureLumaOffset
209 RVCE_CS(0x00000000); // encReconstructedRefBasePictureChromaOffset
210 RVCE_CS(0x00000000); // encReferenceRefBasePictureLumaOffset
211 RVCE_CS(0x00000000); // encReferenceRefBasePictureChromaOffset
212 RVCE_CS(0x00000000); // pictureCount
213 RVCE_CS(enc
->pic
.frame_num
); // frameNumber
214 RVCE_CS(enc
->pic
.pic_order_cnt
); // pictureOrderCount
215 RVCE_CS(0x00000000); // numIPicRemainInRCGOP
216 RVCE_CS(0x00000000); // numPPicRemainInRCGOP
217 RVCE_CS(0x00000000); // numBPicRemainInRCGOP
218 RVCE_CS(0x00000000); // numIRPicRemainInRCGOP
219 RVCE_CS(0x00000000); // enableIntraRefresh
223 void radeon_vce_50_init(struct rvce_encoder
*enc
)
225 radeon_vce_40_2_2_init(enc
);
227 /* only the two below are different */
228 enc
->rate_control
= rate_control
;
229 enc
->encode
= encode
;