src/gallium/drivers/radeon/radeon_vce_50.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <stdio.h>
  35
  36 #include "pipe/p_video_codec.h"
  37
  38 #include "util/u_video.h"
  39 #include "util/u_memory.h"
  40
  41 #include "vl/vl_video_buffer.h"
  42
  43 #include "r600_pipe_common.h"
  44 #include "radeon_video.h"
  45 #include "radeon_vce.h"
  46
  47 static void task_info(struct rvce_encoder *enc, uint32_t taskOperation)
  48 {
  49         RVCE_BEGIN(0x00000002); // task info
  50         RVCE_CS(0xffffffff); // offsetOfNextTaskInfo
  51         RVCE_CS(taskOperation); // taskOperation
  52         RVCE_CS(0x00000000); // referencePictureDependency
  53         RVCE_CS(0x00000000); // collocateFlagDependency
  54         RVCE_CS(0x00000000); // feedbackIndex
  55         RVCE_CS(0x00000000); // videoBitstreamRingIndex
  56         RVCE_END();
  57 }
  58
  59 static void rate_control(struct rvce_encoder *enc)
  60 {
  61         RVCE_BEGIN(0x04000005); // rate control
  62         RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod
  63         RVCE_CS(enc->pic.rate_ctrl.target_bitrate); // encRateControlTargetBitRate
  64         RVCE_CS(enc->pic.rate_ctrl.peak_bitrate); // encRateControlPeakBitRate
  65         RVCE_CS(enc->pic.rate_ctrl.frame_rate_num); // encRateControlFrameRateNum
  66         RVCE_CS(0x00000000); // encGOPSize
  67         RVCE_CS(enc->pic.quant_i_frames); // encQP_I
  68         RVCE_CS(enc->pic.quant_p_frames); // encQP_P
  69         RVCE_CS(enc->pic.quant_b_frames); // encQP_B
  70         RVCE_CS(enc->pic.rate_ctrl.vbv_buffer_size); // encVBVBufferSize
  71         RVCE_CS(enc->pic.rate_ctrl.frame_rate_den); // encRateControlFrameRateDen
  72         RVCE_CS(0x00000000); // encVBVBufferLevel
  73         RVCE_CS(0x00000000); // encMaxAUSize
  74         RVCE_CS(0x00000000); // encQPInitialMode
  75         RVCE_CS(enc->pic.rate_ctrl.target_bits_picture); // encTargetBitsPerPicture
  76         RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_integer); // encPeakBitsPerPictureInteger
  77         RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_fraction); // encPeakBitsPerPictureFractional
  78         RVCE_CS(0x00000000); // encMinQP
  79         RVCE_CS(0x00000033); // encMaxQP
  80         RVCE_CS(0x00000000); // encSkipFrameEnable
  81         RVCE_CS(0x00000000); // encFillerDataEnable
  82         RVCE_CS(0x00000000); // encEnforceHRD
  83         RVCE_CS(0x00000000); // encBPicsDeltaQP
  84         RVCE_CS(0x00000000); // encReferenceBPicsDeltaQP
  85         RVCE_CS(0x00000000); // encRateControlReInitDisable
  86         RVCE_CS(0x00000000); // encLCVBRInitQPFlag
  87         RVCE_CS(0x00000000); // encLCVBRSATDBasedNonlinearBitBudgetFlag
  88         RVCE_END();
  89 }
  90
  91 static void encode(struct rvce_encoder *enc)
  92 {
  93         int i;
  94         unsigned luma_offset, chroma_offset;
  95
  96         task_info(enc, 0x00000003);
  97
  98         RVCE_BEGIN(0x05000001); // context buffer
  99         RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains); // encodeContextAddressHi
 100         RVCE_CS(0x00000000); // encodeContextAddressLo
 101         RVCE_END();
 102
 103         RVCE_BEGIN(0x05000004); // video bitstream buffer
 104         RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT); // videoBitstreamRingAddressHi
 105         RVCE_CS(0x00000000); // videoBitstreamRingAddressLo
 106         RVCE_CS(enc->bs_size); // videoBitstreamRingSize
 107         RVCE_END();
 108
 109         RVCE_BEGIN(0x03000001); // encode
 110         RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders
 111         RVCE_CS(0x00000000); // pictureStructure
 112         RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
 113         RVCE_CS(0x00000000); // forceRefreshMap
 114         RVCE_CS(0x00000000); // insertAUD
 115         RVCE_CS(0x00000000); // endOfSequence
 116         RVCE_CS(0x00000000); // endOfStream
 117         RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureLumaAddressHi
 118         RVCE_CS(enc->luma->level[0].offset); // inputPictureLumaAddressLo
 119         RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureChromaAddressHi
 120         RVCE_CS(enc->chroma->level[0].offset); // inputPictureChromaAddressLo
 121         RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
 122         RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
 123         RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
 124         RVCE_CS(0x00010000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
 125         RVCE_CS(0x00000000); // encInputPicTileConfig
 126         RVCE_CS(enc->pic.picture_type); // encPicType
 127         RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
 128         RVCE_CS(0x00000000); // encIdrPicId
 129         RVCE_CS(0x00000000); // encMGSKeyPic
 130         RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
 131         RVCE_CS(0x00000000); // encTemporalLayerIndex
 132         RVCE_CS(0x00000000); // num_ref_idx_active_override_flag
 133         RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1
 134         RVCE_CS(0x00000000); // num_ref_idx_l1_active_minus1
 135
 136         i = enc->pic.frame_num - enc->pic.ref_idx_l0;
 137         if (i > 1 && enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) {
 138                 RVCE_CS(0x00000001); // encRefListModificationOp
 139                 RVCE_CS(i - 1);      // encRefListModificationNum
 140         } else {
 141                 RVCE_CS(0x00000000); // encRefListModificationOp
 142                 RVCE_CS(0x00000000); // encRefListModificationNum
 143         }
 144
 145         for (i = 0; i < 3; ++i) {
 146                 RVCE_CS(0x00000000); // encRefListModificationOp
 147                 RVCE_CS(0x00000000); // encRefListModificationNum
 148         }
 149         for (i = 0; i < 4; ++i) {
 150                 RVCE_CS(0x00000000); // encDecodedPictureMarkingOp
 151                 RVCE_CS(0x00000000); // encDecodedPictureMarkingNum
 152                 RVCE_CS(0x00000000); // encDecodedPictureMarkingIdx
 153                 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingOp
 154                 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingNum
 155         }
 156
 157         // encReferencePictureL0[0]
 158         RVCE_CS(0x00000000); // pictureStructure
 159         if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
 160            enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
 161                 struct rvce_cpb_slot *l0 = l0_slot(enc);
 162                 rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset);
 163                 RVCE_CS(l0->picture_type); // encPicType
 164                 RVCE_CS(l0->frame_num); // frameNumber
 165                 RVCE_CS(l0->pic_order_cnt); // pictureOrderCount
 166                 RVCE_CS(luma_offset); // lumaOffset
 167                 RVCE_CS(chroma_offset); // chromaOffset
 168         } else {
 169                 RVCE_CS(0x00000000); // encPicType
 170                 RVCE_CS(0x00000000); // frameNumber
 171                 RVCE_CS(0x00000000); // pictureOrderCount
 172                 RVCE_CS(0xffffffff); // lumaOffset
 173                 RVCE_CS(0xffffffff); // chromaOffset
 174         }
 175
 176         // encReferencePictureL0[1]
 177         RVCE_CS(0x00000000); // pictureStructure
 178         RVCE_CS(0x00000000); // encPicType
 179         RVCE_CS(0x00000000); // frameNumber
 180         RVCE_CS(0x00000000); // pictureOrderCount
 181         RVCE_CS(0xffffffff); // lumaOffset
 182         RVCE_CS(0xffffffff); // chromaOffset
 183
 184         // encReferencePictureL1[0]
 185         RVCE_CS(0x00000000); // pictureStructure
 186         if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
 187                 struct rvce_cpb_slot *l1 = l1_slot(enc);
 188                 rvce_frame_offset(enc, l1, &luma_offset, &chroma_offset);
 189                 RVCE_CS(l1->picture_type); // encPicType
 190                 RVCE_CS(l1->frame_num); // frameNumber
 191                 RVCE_CS(l1->pic_order_cnt); // pictureOrderCount
 192                 RVCE_CS(luma_offset); // lumaOffset
 193                 RVCE_CS(chroma_offset); // chromaOffset
 194         } else {
 195                 RVCE_CS(0x00000000); // encPicType
 196                 RVCE_CS(0x00000000); // frameNumber
 197                 RVCE_CS(0x00000000); // pictureOrderCount
 198                 RVCE_CS(0xffffffff); // lumaOffset
 199                 RVCE_CS(0xffffffff); // chromaOffset
 200         }
 201
 202         rvce_frame_offset(enc, current_slot(enc), &luma_offset, &chroma_offset);
 203         RVCE_CS(luma_offset); // encReconstructedLumaOffset
 204         RVCE_CS(chroma_offset); // encReconstructedChromaOffset
 205         RVCE_CS(0x00000000); // encColocBufferOffset
 206         RVCE_CS(0x00000000); // encReconstructedRefBasePictureLumaOffset
 207         RVCE_CS(0x00000000); // encReconstructedRefBasePictureChromaOffset
 208         RVCE_CS(0x00000000); // encReferenceRefBasePictureLumaOffset
 209         RVCE_CS(0x00000000); // encReferenceRefBasePictureChromaOffset
 210         RVCE_CS(0x00000000); // pictureCount
 211         RVCE_CS(enc->pic.frame_num); // frameNumber
 212         RVCE_CS(enc->pic.pic_order_cnt); // pictureOrderCount
 213         RVCE_CS(0x00000000); // numIPicRemainInRCGOP
 214         RVCE_CS(0x00000000); // numPPicRemainInRCGOP
 215         RVCE_CS(0x00000000); // numBPicRemainInRCGOP
 216         RVCE_CS(0x00000000); // numIRPicRemainInRCGOP
 217         RVCE_CS(0x00000000); // enableIntraRefresh
 218         RVCE_END();
 219 }
 220
 221 void radeon_vce_50_init(struct rvce_encoder *enc)
 222 {
 223         radeon_vce_40_2_2_init(enc);
 224
 225         /* only the two below are different */
 226         enc->rate_control = rate_control;
 227         enc->encode = encode;
 228 }