winsys/radeon: use the common job queue for multithreaded command submission v2
[mesa.git] / src / gallium / drivers / radeon / radeon_vce_52.c
1 /**************************************************************************
2 *
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdio.h>
29
30 #include "pipe/p_video_codec.h"
31
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
34
35 #include "vl/vl_video_buffer.h"
36
37 #include "r600_pipe_common.h"
38 #include "radeon_video.h"
39 #include "radeon_vce.h"
40
41 static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
42
43 static void create(struct rvce_encoder *enc)
44 {
45 enc->task_info(enc, 0x00000000, 0, 0, 0);
46
47 RVCE_BEGIN(0x01000001); // create cmd
48 RVCE_CS(0x00000000); // encUseCircularBuffer
49 RVCE_CS(profiles[enc->base.profile -
50 PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
51 RVCE_CS(enc->base.level); // encLevel
52 RVCE_CS(0x00000000); // encPicStructRestriction
53 RVCE_CS(enc->base.width); // encImageWidth
54 RVCE_CS(enc->base.height); // encImageHeight
55 RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
56 RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
57 RVCE_CS(align(enc->luma->npix_y, 16) / 8); // encRefYHeightInQw
58 RVCE_CS(0x00000000); // encRefPic(Addr|Array)Mode, encPicStructRestriction, disableRDO
59
60 RVCE_CS(0x00000000); // encPreEncodeContextBufferOffset
61 RVCE_CS(0x00000000); // encPreEncodeInputLumaBufferOffset
62 RVCE_CS(0x00000000); // encPreEncodeInputChromaBufferOffs
63 RVCE_CS(0x00000000); // encPreEncodeMode|ChromaFlag|VBAQMode|SceneChangeSensitivity
64 RVCE_END();
65 }
66
67 static void encode(struct rvce_encoder *enc)
68 {
69 signed luma_offset, chroma_offset, bs_offset;
70 unsigned dep, bs_idx = enc->bs_idx++;
71 int i;
72
73 if (enc->dual_inst) {
74 if (bs_idx == 0)
75 dep = 1;
76 else if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
77 dep = 0;
78 else
79 dep = 2;
80 } else
81 dep = 0;
82
83 enc->task_info(enc, 0x00000003, dep, 0, bs_idx);
84
85 RVCE_BEGIN(0x05000001); // context buffer
86 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo
87 RVCE_END();
88
89 bs_offset = -(signed)(bs_idx * enc->bs_size);
90
91 RVCE_BEGIN(0x05000004); // video bitstream buffer
92 RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, bs_offset); // videoBitstreamRingAddressHi/Lo
93 RVCE_CS(enc->bs_size); // videoBitstreamRingSize
94 RVCE_END();
95
96 if (enc->dual_pipe) {
97 unsigned aux_offset = enc->cpb.res->buf->size -
98 RVCE_MAX_AUX_BUFFER_NUM * RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
99 RVCE_BEGIN(0x05000002); // auxiliary buffer
100 for (i = 0; i < 8; ++i) {
101 RVCE_CS(aux_offset);
102 aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
103 }
104 for (i = 0; i < 8; ++i)
105 RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE);
106 RVCE_END();
107 }
108
109 RVCE_BEGIN(0x03000001); // encode
110 RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders
111 RVCE_CS(0x00000000); // pictureStructure
112 RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
113 RVCE_CS(0x00000000); // forceRefreshMap
114 RVCE_CS(0x00000000); // insertAUD
115 RVCE_CS(0x00000000); // endOfSequence
116 RVCE_CS(0x00000000); // endOfStream
117 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
118 enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
119 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
120 enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
121 RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
122 RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
123 RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
124 if (enc->dual_pipe)
125 RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
126 else
127 RVCE_CS(0x00010000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
128 RVCE_CS(0x00000000); // encInputPicTileConfig
129 RVCE_CS(enc->pic.picture_type); // encPicType
130 RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
131 RVCE_CS(0x00000000); // encIdrPicId
132 RVCE_CS(0x00000000); // encMGSKeyPic
133 RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
134 RVCE_CS(0x00000000); // encTemporalLayerIndex
135 RVCE_CS(0x00000000); // num_ref_idx_active_override_flag
136 RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1
137 RVCE_CS(0x00000000); // num_ref_idx_l1_active_minus1
138
139 i = enc->pic.frame_num - enc->pic.ref_idx_l0;
140 if (i > 1 && enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) {
141 RVCE_CS(0x00000001); // encRefListModificationOp
142 RVCE_CS(i - 1); // encRefListModificationNum
143 } else {
144 RVCE_CS(0x00000000); // encRefListModificationOp
145 RVCE_CS(0x00000000); // encRefListModificationNum
146 }
147
148 for (i = 0; i < 3; ++i) {
149 RVCE_CS(0x00000000); // encRefListModificationOp
150 RVCE_CS(0x00000000); // encRefListModificationNum
151 }
152 for (i = 0; i < 4; ++i) {
153 RVCE_CS(0x00000000); // encDecodedPictureMarkingOp
154 RVCE_CS(0x00000000); // encDecodedPictureMarkingNum
155 RVCE_CS(0x00000000); // encDecodedPictureMarkingIdx
156 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingOp
157 RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingNum
158 }
159
160 // encReferencePictureL0[0]
161 RVCE_CS(0x00000000); // pictureStructure
162 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
163 enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
164 struct rvce_cpb_slot *l0 = l0_slot(enc);
165 rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset);
166 RVCE_CS(l0->picture_type); // encPicType
167 RVCE_CS(l0->frame_num); // frameNumber
168 RVCE_CS(l0->pic_order_cnt); // pictureOrderCount
169 RVCE_CS(luma_offset); // lumaOffset
170 RVCE_CS(chroma_offset); // chromaOffset
171 } else {
172 RVCE_CS(0x00000000); // encPicType
173 RVCE_CS(0x00000000); // frameNumber
174 RVCE_CS(0x00000000); // pictureOrderCount
175 RVCE_CS(0xffffffff); // lumaOffset
176 RVCE_CS(0xffffffff); // chromaOffset
177 }
178
179 // encReferencePictureL0[1]
180 RVCE_CS(0x00000000); // pictureStructure
181 RVCE_CS(0x00000000); // encPicType
182 RVCE_CS(0x00000000); // frameNumber
183 RVCE_CS(0x00000000); // pictureOrderCount
184 RVCE_CS(0xffffffff); // lumaOffset
185 RVCE_CS(0xffffffff); // chromaOffset
186
187 // encReferencePictureL1[0]
188 RVCE_CS(0x00000000); // pictureStructure
189 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
190 struct rvce_cpb_slot *l1 = l1_slot(enc);
191 rvce_frame_offset(enc, l1, &luma_offset, &chroma_offset);
192 RVCE_CS(l1->picture_type); // encPicType
193 RVCE_CS(l1->frame_num); // frameNumber
194 RVCE_CS(l1->pic_order_cnt); // pictureOrderCount
195 RVCE_CS(luma_offset); // lumaOffset
196 RVCE_CS(chroma_offset); // chromaOffset
197 } else {
198 RVCE_CS(0x00000000); // encPicType
199 RVCE_CS(0x00000000); // frameNumber
200 RVCE_CS(0x00000000); // pictureOrderCount
201 RVCE_CS(0xffffffff); // lumaOffset
202 RVCE_CS(0xffffffff); // chromaOffset
203 }
204
205 rvce_frame_offset(enc, current_slot(enc), &luma_offset, &chroma_offset);
206 RVCE_CS(luma_offset); // encReconstructedLumaOffset
207 RVCE_CS(chroma_offset); // encReconstructedChromaOffset
208 RVCE_CS(0x00000000); // encColocBufferOffset
209 RVCE_CS(0x00000000); // encReconstructedRefBasePictureLumaOffset
210 RVCE_CS(0x00000000); // encReconstructedRefBasePictureChromaOffset
211 RVCE_CS(0x00000000); // encReferenceRefBasePictureLumaOffset
212 RVCE_CS(0x00000000); // encReferenceRefBasePictureChromaOffset
213 RVCE_CS(0x00000000); // pictureCount
214 RVCE_CS(enc->pic.frame_num); // frameNumber
215 RVCE_CS(enc->pic.pic_order_cnt); // pictureOrderCount
216 RVCE_CS(0x00000000); // numIPicRemainInRCGOP
217 RVCE_CS(0x00000000); // numPPicRemainInRCGOP
218 RVCE_CS(0x00000000); // numBPicRemainInRCGOP
219 RVCE_CS(0x00000000); // numIRPicRemainInRCGOP
220 RVCE_CS(0x00000000); // enableIntraRefresh
221
222 RVCE_CS(0x00000000); // aq_variance_en
223 RVCE_CS(0x00000000); // aq_block_size
224 RVCE_CS(0x00000000); // aq_mb_variance_sel
225 RVCE_CS(0x00000000); // aq_frame_variance_sel
226 RVCE_CS(0x00000000); // aq_param_a
227 RVCE_CS(0x00000000); // aq_param_b
228 RVCE_CS(0x00000000); // aq_param_c
229 RVCE_CS(0x00000000); // aq_param_d
230 RVCE_CS(0x00000000); // aq_param_e
231
232 RVCE_CS(0x00000000); // contextInSFB
233 RVCE_END();
234 }
235
236 void radeon_vce_52_init(struct rvce_encoder *enc)
237 {
238 radeon_vce_50_init(enc);
239
240 enc->create = create;
241 enc->encode = encode;
242 }