projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeon/vce: use util function to get h264 profile idc
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <assert.h>
29 #include <stdio.h>
30
31 #include "pipe/p_video_codec.h"
32
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35
36 #include "vl/vl_mpeg12_decoder.h"
37
38 #include "radeonsi/si_pipe.h"
39 #include "radeon_video.h"
40 #include "radeon_vcn_dec.h"
41 #include "vl/vl_probs_table.h"
42
43 #define FB_BUFFER_OFFSET 0x1000
44 #define FB_BUFFER_SIZE 2048
45 #define IT_SCALING_TABLE_SIZE 992
46 #define VP9_PROBS_TABLE_SIZE (RDECODE_VP9_PROBS_DATA_SIZE + 256)
47 #define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)
48
49 #define RDECODE_GPCOM_VCPU_CMD 0x2070c
50 #define RDECODE_GPCOM_VCPU_DATA0 0x20710
51 #define RDECODE_GPCOM_VCPU_DATA1 0x20714
52 #define RDECODE_ENGINE_CNTL 0x20718
53
54 #define NUM_MPEG2_REFS 6
55 #define NUM_H264_REFS 17
56 #define NUM_VC1_REFS 5
57 #define NUM_VP9_REFS 8
58
59 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
60 struct pipe_h264_picture_desc *pic)
61 {
62 rvcn_dec_message_avc_t result;
63
64 memset(&result, 0, sizeof(result));
65 switch (pic->base.profile) {
66 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
67 result.profile = RDECODE_H264_PROFILE_BASELINE;
68 break;
69
70 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
71 result.profile = RDECODE_H264_PROFILE_MAIN;
72 break;
73
74 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
75 result.profile = RDECODE_H264_PROFILE_HIGH;
76 break;
77
78 default:
79 assert(0);
80 break;
81 }
82
83 result.level = dec->base.level;
84
85 result.sps_info_flags = 0;
86 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
87 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
88 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
89 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
90 result.sps_info_flags |= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT;
91
92 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
93 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
94 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
95 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
96 result.log2_max_pic_order_cnt_lsb_minus4 =
97 pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
98
99 switch (dec->base.chroma_format) {
100 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
101 break;
102 case PIPE_VIDEO_CHROMA_FORMAT_400:
103 result.chroma_format = 0;
104 break;
105 case PIPE_VIDEO_CHROMA_FORMAT_420:
106 result.chroma_format = 1;
107 break;
108 case PIPE_VIDEO_CHROMA_FORMAT_422:
109 result.chroma_format = 2;
110 break;
111 case PIPE_VIDEO_CHROMA_FORMAT_444:
112 result.chroma_format = 3;
113 break;
114 }
115
116 result.pps_info_flags = 0;
117 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
118 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
119 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
120 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
121 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
122 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
123 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
124 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
125
126 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
127 result.slice_group_map_type = pic->pps->slice_group_map_type;
128 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
129 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
130 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
131 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
132
133 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
134 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
135
136 memcpy(dec->it, result.scaling_list_4x4, 6*16);
137 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
138
139 result.num_ref_frames = pic->num_ref_frames;
140
141 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
142 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
143
144 result.frame_num = pic->frame_num;
145 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
146 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
147 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
148 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
149
150 result.decoded_pic_idx = pic->frame_num;
151
152 return result;
153 }
154
155 static void radeon_dec_destroy_associated_data(void *data)
156 {
157 /* NOOP, since we only use an intptr */
158 }
159
160 static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
161 struct pipe_video_buffer *target,
162 struct pipe_h265_picture_desc *pic)
163 {
164 rvcn_dec_message_hevc_t result;
165 unsigned i, j;
166
167 memset(&result, 0, sizeof(result));
168 result.sps_info_flags = 0;
169 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
170 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
171 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
172 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
173 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
174 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
175 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
176 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
177 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
178 if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
179 result.sps_info_flags |= 1 << 9;
180 if (pic->UseRefPicList == true)
181 result.sps_info_flags |= 1 << 10;
182
183 result.chroma_format = pic->pps->sps->chroma_format_idc;
184 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
185 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
186 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
187 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
188 result.log2_min_luma_coding_block_size_minus3 =
189 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
190 result.log2_diff_max_min_luma_coding_block_size =
191 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
192 result.log2_min_transform_block_size_minus2 =
193 pic->pps->sps->log2_min_transform_block_size_minus2;
194 result.log2_diff_max_min_transform_block_size =
195 pic->pps->sps->log2_diff_max_min_transform_block_size;
196 result.max_transform_hierarchy_depth_inter =
197 pic->pps->sps->max_transform_hierarchy_depth_inter;
198 result.max_transform_hierarchy_depth_intra =
199 pic->pps->sps->max_transform_hierarchy_depth_intra;
200 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
201 result.pcm_sample_bit_depth_chroma_minus1 =
202 pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
203 result.log2_min_pcm_luma_coding_block_size_minus3 =
204 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
205 result.log2_diff_max_min_pcm_luma_coding_block_size =
206 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
207 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
208
209 result.pps_info_flags = 0;
210 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
211 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
212 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
213 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
214 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
215 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
216 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
217 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
218 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
219 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
220 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
221 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
222 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
223 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
224 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
225 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
226 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
227 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
228 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
229 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
230
231 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
232 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
233 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
234 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
235 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
236 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
237 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
238 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
239 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
240 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
241 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
242 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
243 result.init_qp_minus26 = pic->pps->init_qp_minus26;
244
245 for (i = 0; i < 19; ++i)
246 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
247
248 for (i = 0; i < 21; ++i)
249 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
250
251 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
252 result.curr_poc = pic->CurrPicOrderCntVal;
253
254 for (i = 0 ; i < 16 ; i++) {
255 for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
256 if (dec->render_pic_list[i] == pic->ref[j])
257 break;
258 if (j == 15)
259 dec->render_pic_list[i] = NULL;
260 else if (pic->ref[j+1] == NULL)
261 dec->render_pic_list[i] = NULL;
262 }
263 }
264 for (i = 0 ; i < 16 ; i++) {
265 if (dec->render_pic_list[i] == NULL) {
266 dec->render_pic_list[i] = target;
267 result.curr_idx = i;
268 break;
269 }
270 }
271
272 vl_video_buffer_set_associated_data(target, &dec->base,
273 (void *)(uintptr_t)result.curr_idx,
274 &radeon_dec_destroy_associated_data);
275
276 for (i = 0; i < 16; ++i) {
277 struct pipe_video_buffer *ref = pic->ref[i];
278 uintptr_t ref_pic = 0;
279
280 result.poc_list[i] = pic->PicOrderCntVal[i];
281
282 if (ref)
283 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
284 else
285 ref_pic = 0x7F;
286 result.ref_pic_list[i] = ref_pic;
287 }
288
289 for (i = 0; i < 8; ++i) {
290 result.ref_pic_set_st_curr_before[i] = 0xFF;
291 result.ref_pic_set_st_curr_after[i] = 0xFF;
292 result.ref_pic_set_lt_curr[i] = 0xFF;
293 }
294
295 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
296 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
297
298 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
299 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
300
301 for (i = 0; i < pic->NumPocLtCurr; ++i)
302 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
303
304 for (i = 0; i < 6; ++i)
305 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
306
307 for (i = 0; i < 2; ++i)
308 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
309
310 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
311 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
312 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
313 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
314
315 for (i = 0 ; i < 2 ; i++) {
316 for (j = 0 ; j < 15 ; j++)
317 result.direct_reflist[i][j] = pic->RefPicList[i][j];
318 }
319
320 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
321 if (target->buffer_format == PIPE_FORMAT_P016) {
322 result.p010_mode = 1;
323 result.msb_mode = 1;
324 } else {
325 result.p010_mode = 0;
326 result.luma_10to8 = 5;
327 result.chroma_10to8 = 5;
328 result.hevc_reserved[0] = 4; /* sclr_luma10to8 */
329 result.hevc_reserved[1] = 4; /* sclr_chroma10to8 */
330 }
331 }
332
333 return result;
334 }
335
336 static void fill_probs_table(void *ptr)
337 {
338 rvcn_dec_vp9_probs_t *probs = (rvcn_dec_vp9_probs_t *)ptr;
339
340 memcpy(&probs->coef_probs[0], default_coef_probs_4x4, sizeof(default_coef_probs_4x4));
341 memcpy(&probs->coef_probs[1], default_coef_probs_8x8, sizeof(default_coef_probs_8x8));
342 memcpy(&probs->coef_probs[2], default_coef_probs_16x16, sizeof(default_coef_probs_16x16));
343 memcpy(&probs->coef_probs[3], default_coef_probs_32x32, sizeof(default_coef_probs_32x32));
344 memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
345 memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
346 memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
347 memcpy(probs->switchable_interp_prob, default_switchable_interp_prob, sizeof(default_switchable_interp_prob));
348 memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
349 memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
350 memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
351 memcpy(probs->intra_inter_prob, default_intra_inter_p, sizeof(default_intra_inter_p));
352 memcpy(probs->comp_inter_prob, default_comp_inter_p, sizeof(default_comp_inter_p));
353 memcpy(probs->comp_ref_prob, default_comp_ref_p, sizeof(default_comp_ref_p));
354 memcpy(probs->tx_probs_32x32, default_tx_probs_32x32, sizeof(default_tx_probs_32x32));
355 memcpy(probs->tx_probs_16x16, default_tx_probs_16x16, sizeof(default_tx_probs_16x16));
356 memcpy(probs->tx_probs_8x8, default_tx_probs_8x8, sizeof(default_tx_probs_8x8));
357 memcpy(probs->mv_joints, default_nmv_joints, sizeof(default_nmv_joints));
358 memcpy(&probs->mv_comps[0], default_nmv_components, sizeof(default_nmv_components));
359 memset(&probs->nmvc_mask, 0, sizeof(rvcn_dec_vp9_nmv_ctx_mask_t));
360 }
361
362 static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
363 struct pipe_video_buffer *target,
364 struct pipe_vp9_picture_desc *pic)
365 {
366 rvcn_dec_message_vp9_t result;
367 unsigned i;
368
369 memset(&result, 0, sizeof(result));
370
371 /* segment table */
372 rvcn_dec_vp9_probs_segment_t *prbs = (rvcn_dec_vp9_probs_segment_t *)(dec->probs);
373
374 if (pic->picture_parameter.pic_fields.segmentation_enabled) {
375 for (i = 0; i < 8; ++i) {
376 prbs->seg.feature_data[i] =
377 (pic->slice_parameter.seg_param[i].alt_quant & 0xffff) |
378 ((pic->slice_parameter.seg_param[i].alt_lf & 0xff) << 16) |
379 ((pic->slice_parameter.seg_param[i].segment_flags.segment_reference & 0xf) << 24);
380 prbs->seg.feature_mask[i] =
381 (pic->slice_parameter.seg_param[i].alt_quant_enabled << 0) |
382 (pic->slice_parameter.seg_param[i].alt_lf_enabled << 1) |
383 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_enabled << 2) |
384 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_skipped << 3);
385 }
386
387 for (i = 0; i < 7; ++i)
388 prbs->seg.tree_probs[i] = pic->picture_parameter.mb_segment_tree_probs[i];
389
390 for (i = 0; i < 3; ++i)
391 prbs->seg.pred_probs[i] = pic->picture_parameter.segment_pred_probs[i];
392
393 prbs->seg.abs_delta = 0;
394 } else
395 memset(&prbs->seg, 0, 256);
396
397 result.frame_header_flags =
398 (pic->picture_parameter.pic_fields.frame_type <<
399 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
400 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
401
402 result.frame_header_flags |=
403 (pic->picture_parameter.pic_fields.error_resilient_mode <<
404 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
405 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
406
407 result.frame_header_flags |=
408 (pic->picture_parameter.pic_fields.intra_only <<
409 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
410 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
411
412 result.frame_header_flags |=
413 (pic->picture_parameter.pic_fields.allow_high_precision_mv <<
414 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
415 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
416
417 result.frame_header_flags |=
418 (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode <<
419 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
420 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
421
422 result.frame_header_flags |=
423 (pic->picture_parameter.pic_fields.refresh_frame_context <<
424 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
425 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
426
427 result.frame_header_flags |=
428 (pic->picture_parameter.pic_fields.segmentation_enabled <<
429 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
430 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
431
432 result.frame_header_flags |=
433 (pic->picture_parameter.pic_fields.segmentation_update_map <<
434 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
435 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
436
437 result.frame_header_flags |=
438 (pic->picture_parameter.pic_fields.segmentation_temporal_update <<
439 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
440 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
441
442 result.frame_header_flags |=
443 (pic->picture_parameter.mode_ref_delta_enabled <<
444 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
445 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
446
447 result.frame_header_flags |=
448 (pic->picture_parameter.mode_ref_delta_update <<
449 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
450 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
451
452 result.frame_header_flags |= ((dec->show_frame &&
453 !pic->picture_parameter.pic_fields.error_resilient_mode)
454 << RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
455 RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
456 dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
457
458 result.interp_filter = pic->picture_parameter.pic_fields.mcomp_filter_type;
459
460 result.frame_context_idx = pic->picture_parameter.pic_fields.frame_context_idx;
461 result.reset_frame_context = pic->picture_parameter.pic_fields.reset_frame_context;
462
463 result.filter_level = pic->picture_parameter.filter_level;
464 result.sharpness_level = pic->picture_parameter.sharpness_level;
465
466 for (i = 0; i < 8; ++i)
467 memcpy(result.lf_adj_level[i], pic->slice_parameter.seg_param[i].filter_level, 4 * 2);
468
469 if (pic->picture_parameter.pic_fields.lossless_flag) {
470 result.base_qindex = 0;
471 result.y_dc_delta_q = 0;
472 result.uv_ac_delta_q = 0;
473 result.uv_dc_delta_q = 0;
474 } else {
475 result.base_qindex = pic->picture_parameter.base_qindex;
476 result.y_dc_delta_q = pic->picture_parameter.y_dc_delta_q;
477 result.uv_ac_delta_q = pic->picture_parameter.uv_ac_delta_q;
478 result.uv_dc_delta_q = pic->picture_parameter.uv_dc_delta_q;
479 }
480
481 result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
482 result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
483 result.chroma_format = 1;
484 result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8
485 = (pic->picture_parameter.bit_depth - 8);
486
487 result.vp9_frame_size = align(dec->bs_size, 128);
488 result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
489 result.compressed_header_size = pic->picture_parameter.first_partition_size;
490
491 assert(dec->base.max_references + 1 <= 16);
492
493 for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
494 if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
495 result.curr_pic_idx =
496 (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
497 break;
498 } else if (!dec->render_pic_list[i]) {
499 dec->render_pic_list[i] = target;
500 result.curr_pic_idx = dec->ref_idx;
501 vl_video_buffer_set_associated_data(target, &dec->base,
502 (void *)(uintptr_t)dec->ref_idx++,
503 &radeon_dec_destroy_associated_data);
504 break;
505 }
506 }
507
508 for (i = 0 ; i < 8; i++) {
509 result.ref_frame_map[i] = (pic->ref[i]) ?
510 (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) :
511 0x7f;
512 }
513
514 result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
515 result.ref_frame_sign_bias[0] = pic->picture_parameter.pic_fields.last_ref_frame_sign_bias;
516 result.frame_refs[1] = result.ref_frame_map[pic->picture_parameter.pic_fields.golden_ref_frame];
517 result.ref_frame_sign_bias[1] = pic->picture_parameter.pic_fields.golden_ref_frame_sign_bias;
518 result.frame_refs[2] = result.ref_frame_map[pic->picture_parameter.pic_fields.alt_ref_frame];
519 result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
520
521 if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
522 if (target->buffer_format == PIPE_FORMAT_P016) {
523 result.p010_mode = 1;
524 result.msb_mode = 1;
525 } else {
526 result.p010_mode = 0;
527 result.luma_10to8 = 1;
528 result.chroma_10to8 = 1;
529 }
530 }
531
532 return result;
533 }
534
535 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
536 {
537 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
538 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
539
540 unsigned max_references = dec->base.max_references + 1;
541
542 if (dec->base.width * dec->base.height >= 4096*2000)
543 max_references = MAX2(max_references, 8);
544 else
545 max_references = MAX2(max_references, 17);
546
547 width = align (width, 16);
548 height = align (height, 16);
549 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
550 }
551
552 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
553 {
554 unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
555 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
556 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
557
558 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
559 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
560 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 ||
561 pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
562
563 unsigned max_references = dec->base.max_references + 1;
564
565 if (dec->base.width * dec->base.height >= 4096*2000)
566 max_references = MAX2(max_references, 8);
567 else
568 max_references = MAX2(max_references, 17);
569
570 block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
571 log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
572
573 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
574 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
575
576 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
577 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
578 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
579
580 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
581 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
582
583 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
584 }
585
586 static rvcn_dec_message_vc1_t get_vc1_msg(struct pipe_vc1_picture_desc *pic)
587 {
588 rvcn_dec_message_vc1_t result;
589
590 memset(&result, 0, sizeof(result));
591 switch(pic->base.profile) {
592 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
593 result.profile = RDECODE_VC1_PROFILE_SIMPLE;
594 result.level = 1;
595 break;
596
597 case PIPE_VIDEO_PROFILE_VC1_MAIN:
598 result.profile = RDECODE_VC1_PROFILE_MAIN;
599 result.level = 2;
600 break;
601
602 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
603 result.profile = RDECODE_VC1_PROFILE_ADVANCED;
604 result.level = 4;
605 break;
606
607 default:
608 assert(0);
609 }
610
611 result.sps_info_flags |= pic->postprocflag << 7;
612 result.sps_info_flags |= pic->pulldown << 6;
613 result.sps_info_flags |= pic->interlace << 5;
614 result.sps_info_flags |= pic->tfcntrflag << 4;
615 result.sps_info_flags |= pic->finterpflag << 3;
616 result.sps_info_flags |= pic->psf << 1;
617
618 result.pps_info_flags |= pic->range_mapy_flag << 31;
619 result.pps_info_flags |= pic->range_mapy << 28;
620 result.pps_info_flags |= pic->range_mapuv_flag << 27;
621 result.pps_info_flags |= pic->range_mapuv << 24;
622 result.pps_info_flags |= pic->multires << 21;
623 result.pps_info_flags |= pic->maxbframes << 16;
624 result.pps_info_flags |= pic->overlap << 11;
625 result.pps_info_flags |= pic->quantizer << 9;
626 result.pps_info_flags |= pic->panscan_flag << 7;
627 result.pps_info_flags |= pic->refdist_flag << 6;
628 result.pps_info_flags |= pic->vstransform << 0;
629
630 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
631 result.pps_info_flags |= pic->syncmarker << 20;
632 result.pps_info_flags |= pic->rangered << 19;
633 result.pps_info_flags |= pic->loopfilter << 5;
634 result.pps_info_flags |= pic->fastuvmc << 4;
635 result.pps_info_flags |= pic->extended_mv << 3;
636 result.pps_info_flags |= pic->extended_dmv << 8;
637 result.pps_info_flags |= pic->dquant << 1;
638 }
639
640 result.chroma_format = 1;
641
642 return result;
643 }
644
645 static uint32_t get_ref_pic_idx(struct radeon_decoder *dec, struct pipe_video_buffer *ref)
646 {
647 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
648 uint32_t max = MAX2(dec->frame_number, 1) - 1;
649 uintptr_t frame;
650
651 /* seems to be the most sane fallback */
652 if (!ref)
653 return max;
654
655 /* get the frame number from the associated data */
656 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
657
658 /* limit the frame number to a valid range */
659 return MAX2(MIN2(frame, max), min);
660 }
661
662 static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct radeon_decoder *dec,
663 struct pipe_mpeg12_picture_desc *pic)
664 {
665 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
666 rvcn_dec_message_mpeg2_vld_t result;
667 unsigned i;
668
669 memset(&result, 0, sizeof(result));
670 result.decoded_pic_idx = dec->frame_number;
671
672 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
673 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
674
675 if(pic->intra_matrix) {
676 result.load_intra_quantiser_matrix = 1;
677 for (i = 0; i < 64; ++i) {
678 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
679 }
680 }
681 if(pic->non_intra_matrix) {
682 result.load_nonintra_quantiser_matrix = 1;
683 for (i = 0; i < 64; ++i) {
684 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
685 }
686 }
687
688 result.profile_and_level_indication = 0;
689 result.chroma_format = 0x1;
690
691 result.picture_coding_type = pic->picture_coding_type;
692 result.f_code[0][0] = pic->f_code[0][0] + 1;
693 result.f_code[0][1] = pic->f_code[0][1] + 1;
694 result.f_code[1][0] = pic->f_code[1][0] + 1;
695 result.f_code[1][1] = pic->f_code[1][1] + 1;
696 result.intra_dc_precision = pic->intra_dc_precision;
697 result.pic_structure = pic->picture_structure;
698 result.top_field_first = pic->top_field_first;
699 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
700 result.concealment_motion_vectors = pic->concealment_motion_vectors;
701 result.q_scale_type = pic->q_scale_type;
702 result.intra_vlc_format = pic->intra_vlc_format;
703 result.alternate_scan = pic->alternate_scan;
704
705 return result;
706 }
707
708 static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec,
709 struct pipe_mpeg4_picture_desc *pic)
710 {
711 rvcn_dec_message_mpeg4_asp_vld_t result;
712 unsigned i;
713
714 memset(&result, 0, sizeof(result));
715 result.decoded_pic_idx = dec->frame_number;
716
717 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
718 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
719
720 result.variant_type = 0;
721 result.profile_and_level_indication = 0xF0;
722
723 result.video_object_layer_verid = 0x5;
724 result.video_object_layer_shape = 0x0;
725
726 result.video_object_layer_width = dec->base.width;
727 result.video_object_layer_height = dec->base.height;
728
729 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
730
731 result.short_video_header = pic->short_video_header;
732 result.interlaced = pic->interlaced;
733 result.load_intra_quant_mat = 1;
734 result.load_nonintra_quant_mat = 1;
735 result.quarter_sample = pic->quarter_sample;
736 result.complexity_estimation_disable = 1;
737 result.resync_marker_disable = pic->resync_marker_disable;
738 result.newpred_enable = 0;
739 result.reduced_resolution_vop_enable = 0;
740
741 result.quant_type = pic->quant_type;
742
743 for (i = 0; i < 64; ++i) {
744 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
745 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
746 }
747
748 return result;
749 }
750
751 static void rvcn_dec_message_create(struct radeon_decoder *dec)
752 {
753 rvcn_dec_message_header_t *header = dec->msg;
754 rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
755 unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
756
757 memset(dec->msg, 0, sizes);
758 header->header_size = sizeof(rvcn_dec_message_header_t);
759 header->total_size = sizes;
760 header->num_buffers = 1;
761 header->msg_type = RDECODE_MSG_CREATE;
762 header->stream_handle = dec->stream_handle;
763 header->status_report_feedback_number = 0;
764
765 header->index[0].message_id = RDECODE_MESSAGE_CREATE;
766 header->index[0].offset = sizeof(rvcn_dec_message_header_t);
767 header->index[0].size = sizeof(rvcn_dec_message_create_t);
768 header->index[0].filled = 0;
769
770 create->stream_type = dec->stream_type;
771 create->session_flags = 0;
772 create->width_in_samples = dec->base.width;
773 create->height_in_samples = dec->base.height;
774 }
775
776 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
777 struct pipe_video_buffer *target,
778 struct pipe_picture_desc *picture)
779 {
780 struct si_texture *luma = (struct si_texture *)
781 ((struct vl_video_buffer *)target)->resources[0];
782 struct si_texture *chroma = (struct si_texture *)
783 ((struct vl_video_buffer *)target)->resources[1];
784 rvcn_dec_message_header_t *header;
785 rvcn_dec_message_index_t *index;
786 rvcn_dec_message_decode_t *decode;
787 unsigned sizes = 0, offset_decode, offset_codec;
788 void *codec;
789
790 header = dec->msg;
791 sizes += sizeof(rvcn_dec_message_header_t);
792 index = (void*)header + sizeof(rvcn_dec_message_header_t);
793 sizes += sizeof(rvcn_dec_message_index_t);
794 offset_decode = sizes;
795 decode = (void*)index + sizeof(rvcn_dec_message_index_t);
796 sizes += sizeof(rvcn_dec_message_decode_t);
797 offset_codec = sizes;
798 codec = (void*)decode + sizeof(rvcn_dec_message_decode_t);
799
800 memset(dec->msg, 0, sizes);
801 header->header_size = sizeof(rvcn_dec_message_header_t);
802 header->total_size = sizes;
803 header->num_buffers = 2;
804 header->msg_type = RDECODE_MSG_DECODE;
805 header->stream_handle = dec->stream_handle;
806 header->status_report_feedback_number = dec->frame_number;
807
808 header->index[0].message_id = RDECODE_MESSAGE_DECODE;
809 header->index[0].offset = offset_decode;
810 header->index[0].size = sizeof(rvcn_dec_message_decode_t);
811 header->index[0].filled = 0;
812
813 index->offset = offset_codec;
814 index->size = sizeof(rvcn_dec_message_avc_t);
815 index->filled = 0;
816
817 decode->stream_type = dec->stream_type;
818 decode->decode_flags = 0x1;
819 decode->width_in_samples = dec->base.width;
820 decode->height_in_samples = dec->base.height;
821
822 decode->bsd_size = align(dec->bs_size, 128);
823 decode->dpb_size = dec->dpb.res->buf->size;
824 decode->dt_size =
825 r600_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
826 r600_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
827
828 decode->sct_size = 0;
829 decode->sc_coeff_size = 0;
830
831 decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
832 decode->db_pitch = align(dec->base.width, 32);
833 decode->db_surf_tile_config = 0;
834
835 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
836 decode->dt_uv_pitch = decode->dt_pitch / 2;
837
838 decode->dt_tiling_mode = 0;
839 decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
840 decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
841 decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
842 decode->dt_surf_tile_config = 0;
843 decode->dt_uv_surf_tile_config = 0;
844
845 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
846 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
847 if (decode->dt_field_mode) {
848 decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset +
849 luma->surface.u.gfx9.surf_slice_size;
850 decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset +
851 chroma->surface.u.gfx9.surf_slice_size;
852 } else {
853 decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
854 decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
855 }
856
857 switch (u_reduce_video_profile(picture->profile)) {
858 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
859 rvcn_dec_message_avc_t avc =
860 get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
861 memcpy(codec, (void*)&avc, sizeof(rvcn_dec_message_avc_t));
862 index->message_id = RDECODE_MESSAGE_AVC;
863 break;
864 }
865 case PIPE_VIDEO_FORMAT_HEVC: {
866 rvcn_dec_message_hevc_t hevc =
867 get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
868
869 memcpy(codec, (void*)&hevc, sizeof(rvcn_dec_message_hevc_t));
870 index->message_id = RDECODE_MESSAGE_HEVC;
871 if (dec->ctx.res == NULL) {
872 unsigned ctx_size;
873 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
874 ctx_size = calc_ctx_size_h265_main10(dec,
875 (struct pipe_h265_picture_desc*)picture);
876 else
877 ctx_size = calc_ctx_size_h265_main(dec);
878 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
879 RVID_ERR("Can't allocated context buffer.\n");
880 si_vid_clear_buffer(dec->base.context, &dec->ctx);
881 }
882 break;
883 }
884 case PIPE_VIDEO_FORMAT_VC1: {
885 rvcn_dec_message_vc1_t vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
886
887 memcpy(codec, (void*)&vc1, sizeof(rvcn_dec_message_vc1_t));
888 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
889 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
890 decode->width_in_samples = align(decode->width_in_samples, 16) / 16;
891 decode->height_in_samples = align(decode->height_in_samples, 16) / 16;
892 }
893 index->message_id = RDECODE_MESSAGE_VC1;
894 break;
895
896 }
897 case PIPE_VIDEO_FORMAT_MPEG12: {
898 rvcn_dec_message_mpeg2_vld_t mpeg2 =
899 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
900
901 memcpy(codec, (void*)&mpeg2, sizeof(rvcn_dec_message_mpeg2_vld_t));
902 index->message_id = RDECODE_MESSAGE_MPEG2_VLD;
903 break;
904 }
905 case PIPE_VIDEO_FORMAT_MPEG4: {
906 rvcn_dec_message_mpeg4_asp_vld_t mpeg4 =
907 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
908
909 memcpy(codec, (void*)&mpeg4, sizeof(rvcn_dec_message_mpeg4_asp_vld_t));
910 index->message_id = RDECODE_MESSAGE_MPEG4_ASP_VLD;
911 break;
912 }
913 case PIPE_VIDEO_FORMAT_VP9: {
914 rvcn_dec_message_vp9_t vp9 =
915 get_vp9_msg(dec, target, (struct pipe_vp9_picture_desc*)picture);
916
917 memcpy(codec, (void*)&vp9, sizeof(rvcn_dec_message_vp9_t));
918 index->message_id = RDECODE_MESSAGE_VP9;
919
920 if (dec->ctx.res == NULL) {
921 unsigned ctx_size;
922 uint8_t *ptr;
923
924 /* default probability + probability data */
925 ctx_size = 2304 * 5;
926
927 /* SRE collocated context data */
928 ctx_size += 32 * 2 * 64 * 64;
929
930 /* SMP collocated context data */
931 ctx_size += 9 * 64 * 2 * 64 * 64;
932
933 /* SDB left tile pixel */
934 ctx_size += 8 * 2 * 4096;
935
936 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
937 ctx_size += 8 * 2 * 4096;
938
939 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
940 RVID_ERR("Can't allocated context buffer.\n");
941 si_vid_clear_buffer(dec->base.context, &dec->ctx);
942
943 /* ctx needs probs table */
944 ptr = dec->ws->buffer_map(dec->ctx.res->buf, dec->cs, PIPE_TRANSFER_WRITE);
945 fill_probs_table(ptr);
946 dec->ws->buffer_unmap(dec->ctx.res->buf);
947 }
948 break;
949 }
950 default:
951 assert(0);
952 return NULL;
953 }
954
955 if (dec->ctx.res)
956 decode->hw_ctxt_size = dec->ctx.res->buf->size;
957
958 return luma->buffer.buf;
959 }
960
961 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
962 {
963 rvcn_dec_message_header_t *header = dec->msg;
964
965 memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
966 header->header_size = sizeof(rvcn_dec_message_header_t);
967 header->total_size = sizeof(rvcn_dec_message_header_t) -
968 sizeof(rvcn_dec_message_index_t);
969 header->num_buffers = 0;
970 header->msg_type = RDECODE_MSG_DESTROY;
971 header->stream_handle = dec->stream_handle;
972 header->status_report_feedback_number = 0;
973 }
974
975 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
976 {
977 rvcn_dec_feedback_header_t *header = (void*)dec->fb;
978
979 header->header_size = sizeof(rvcn_dec_feedback_header_t);
980 header->total_size = sizeof(rvcn_dec_feedback_header_t);
981 header->num_buffers = 0;
982 }
983
984 /* flush IB to the hardware */
985 static int flush(struct radeon_decoder *dec, unsigned flags)
986 {
987 return dec->ws->cs_flush(dec->cs, flags, NULL);
988 }
989
990 /* add a new set register command to the IB */
991 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
992 {
993 radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
994 radeon_emit(dec->cs, val);
995 }
996
997 /* send a command to the VCPU through the GPCOM registers */
998 static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
999 struct pb_buffer* buf, uint32_t off,
1000 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
1001 {
1002 uint64_t addr;
1003
1004 dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
1005 domain, 0);
1006 addr = dec->ws->buffer_get_virtual_address(buf);
1007 addr = addr + off;
1008
1009 set_reg(dec, RDECODE_GPCOM_VCPU_DATA0, addr);
1010 set_reg(dec, RDECODE_GPCOM_VCPU_DATA1, addr >> 32);
1011 set_reg(dec, RDECODE_GPCOM_VCPU_CMD, cmd << 1);
1012 }
1013
1014 /* do the codec needs an IT buffer ?*/
1015 static bool have_it(struct radeon_decoder *dec)
1016 {
1017 return dec->stream_type == RDECODE_CODEC_H264_PERF ||
1018 dec->stream_type == RDECODE_CODEC_H265;
1019 }
1020
1021 /* do the codec needs an probs buffer? */
1022 static bool have_probs(struct radeon_decoder *dec)
1023 {
1024 return dec->stream_type == RDECODE_CODEC_VP9;
1025 }
1026
1027 /* map the next available message/feedback/itscaling buffer */
1028 static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
1029 {
1030 struct rvid_buffer* buf;
1031 uint8_t *ptr;
1032
1033 /* grab the current message/feedback buffer */
1034 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1035
1036 /* and map it for CPU access */
1037 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
1038
1039 /* calc buffer offsets */
1040 dec->msg = ptr;
1041
1042 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1043 if (have_it(dec))
1044 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1045 else if (have_probs(dec))
1046 dec->probs = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1047 }
1048
1049 /* unmap and send a message command to the VCPU */
1050 static void send_msg_buf(struct radeon_decoder *dec)
1051 {
1052 struct rvid_buffer* buf;
1053
1054 /* ignore the request if message/feedback buffer isn't mapped */
1055 if (!dec->msg || !dec->fb)
1056 return;
1057
1058 /* grab the current message buffer */
1059 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1060
1061 /* unmap the buffer */
1062 dec->ws->buffer_unmap(buf->res->buf);
1063 dec->msg = NULL;
1064 dec->fb = NULL;
1065 dec->it = NULL;
1066 dec->probs = NULL;
1067
1068 if (dec->sessionctx.res)
1069 send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
1070 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
1071 RADEON_DOMAIN_VRAM);
1072
1073 /* and send it to the hardware */
1074 send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
1075 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1076 }
1077
1078 /* cycle to the next set of buffers */
1079 static void next_buffer(struct radeon_decoder *dec)
1080 {
1081 ++dec->cur_buffer;
1082 dec->cur_buffer %= NUM_BUFFERS;
1083 }
1084
1085 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
1086 {
1087 unsigned width_in_mb, height_in_mb, ctx_size;
1088 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1089 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1090
1091 unsigned max_references = dec->base.max_references + 1;
1092
1093 // picture width & height in 16 pixel units
1094 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1095 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1096
1097 unsigned fs_in_mb = width_in_mb * height_in_mb;
1098 unsigned num_dpb_buffer;
1099 switch(dec->base.level) {
1100 case 30:
1101 num_dpb_buffer = 8100 / fs_in_mb;
1102 break;
1103 case 31:
1104 num_dpb_buffer = 18000 / fs_in_mb;
1105 break;
1106 case 32:
1107 num_dpb_buffer = 20480 / fs_in_mb;
1108 break;
1109 case 41:
1110 num_dpb_buffer = 32768 / fs_in_mb;
1111 break;
1112 case 42:
1113 num_dpb_buffer = 34816 / fs_in_mb;
1114 break;
1115 case 50:
1116 num_dpb_buffer = 110400 / fs_in_mb;
1117 break;
1118 case 51:
1119 num_dpb_buffer = 184320 / fs_in_mb;
1120 break;
1121 default:
1122 num_dpb_buffer = 184320 / fs_in_mb;
1123 break;
1124 }
1125 num_dpb_buffer++;
1126 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1127 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
1128
1129 return ctx_size;
1130 }
1131
1132 /* calculate size of reference picture buffer */
1133 static unsigned calc_dpb_size(struct radeon_decoder *dec)
1134 {
1135 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
1136
1137 // always align them to MB size for dpb calculation
1138 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1139 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1140
1141 // always one more for currently decoded picture
1142 unsigned max_references = dec->base.max_references + 1;
1143
1144 // aligned size of a single frame
1145 image_size = align(width, 32) * height;
1146 image_size += image_size / 2;
1147 image_size = align(image_size, 1024);
1148
1149 // picture width & height in 16 pixel units
1150 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1151 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1152
1153 switch (u_reduce_video_profile(dec->base.profile)) {
1154 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1155 unsigned fs_in_mb = width_in_mb * height_in_mb;
1156 unsigned num_dpb_buffer;
1157
1158 switch(dec->base.level) {
1159 case 30:
1160 num_dpb_buffer = 8100 / fs_in_mb;
1161 break;
1162 case 31:
1163 num_dpb_buffer = 18000 / fs_in_mb;
1164 break;
1165 case 32:
1166 num_dpb_buffer = 20480 / fs_in_mb;
1167 break;
1168 case 41:
1169 num_dpb_buffer = 32768 / fs_in_mb;
1170 break;
1171 case 42:
1172 num_dpb_buffer = 34816 / fs_in_mb;
1173 break;
1174 case 50:
1175 num_dpb_buffer = 110400 / fs_in_mb;
1176 break;
1177 case 51:
1178 num_dpb_buffer = 184320 / fs_in_mb;
1179 break;
1180 default:
1181 num_dpb_buffer = 184320 / fs_in_mb;
1182 break;
1183 }
1184 num_dpb_buffer++;
1185 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1186 dpb_size = image_size * max_references;
1187 break;
1188 }
1189
1190 case PIPE_VIDEO_FORMAT_HEVC:
1191 if (dec->base.width * dec->base.height >= 4096*2000)
1192 max_references = MAX2(max_references, 8);
1193 else
1194 max_references = MAX2(max_references, 17);
1195
1196 width = align (width, 16);
1197 height = align (height, 16);
1198 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1199 dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
1200 else
1201 dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
1202 break;
1203
1204 case PIPE_VIDEO_FORMAT_VC1:
1205 // the firmware seems to allways assume a minimum of ref frames
1206 max_references = MAX2(NUM_VC1_REFS, max_references);
1207
1208 // reference picture buffer
1209 dpb_size = image_size * max_references;
1210
1211 // CONTEXT_BUFFER
1212 dpb_size += width_in_mb * height_in_mb * 128;
1213
1214 // IT surface buffer
1215 dpb_size += width_in_mb * 64;
1216
1217 // DB surface buffer
1218 dpb_size += width_in_mb * 128;
1219
1220 // BP
1221 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
1222 break;
1223
1224 case PIPE_VIDEO_FORMAT_MPEG12:
1225 // reference picture buffer, must be big enough for all frames
1226 dpb_size = image_size * NUM_MPEG2_REFS;
1227 break;
1228
1229 case PIPE_VIDEO_FORMAT_MPEG4:
1230 // reference picture buffer
1231 dpb_size = image_size * max_references;
1232
1233 // CM
1234 dpb_size += width_in_mb * height_in_mb * 64;
1235
1236 // IT surface buffer
1237 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
1238
1239 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
1240 break;
1241
1242 case PIPE_VIDEO_FORMAT_VP9:
1243 max_references = MAX2(max_references, 9);
1244
1245 dpb_size = (4096 * 3000 * 3 / 2) * max_references;
1246 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1247 dpb_size *= (3 / 2);
1248 break;
1249
1250 case PIPE_VIDEO_FORMAT_JPEG:
1251 dpb_size = 0;
1252 break;
1253
1254 default:
1255 // something is missing here
1256 assert(0);
1257
1258 // at least use a sane default value
1259 dpb_size = 32 * 1024 * 1024;
1260 break;
1261 }
1262 return dpb_size;
1263 }
1264
1265 /**
1266 * destroy this video decoder
1267 */
1268 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
1269 {
1270 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1271 unsigned i;
1272
1273 assert(decoder);
1274
1275 map_msg_fb_it_probs_buf(dec);
1276 rvcn_dec_message_destroy(dec);
1277 send_msg_buf(dec);
1278
1279 flush(dec, 0);
1280
1281 dec->ws->cs_destroy(dec->cs);
1282
1283 for (i = 0; i < NUM_BUFFERS; ++i) {
1284 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1285 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1286 }
1287
1288 si_vid_destroy_buffer(&dec->dpb);
1289 si_vid_destroy_buffer(&dec->ctx);
1290 si_vid_destroy_buffer(&dec->sessionctx);
1291
1292 FREE(dec);
1293 }
1294
1295 /**
1296 * start decoding of a new frame
1297 */
1298 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
1299 struct pipe_video_buffer *target,
1300 struct pipe_picture_desc *picture)
1301 {
1302 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1303 uintptr_t frame;
1304
1305 assert(decoder);
1306
1307 frame = ++dec->frame_number;
1308 if (dec->stream_type != RDECODE_CODEC_VP9)
1309 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1310 &radeon_dec_destroy_associated_data);
1311
1312 dec->bs_size = 0;
1313 dec->bs_ptr = dec->ws->buffer_map(
1314 dec->bs_buffers[dec->cur_buffer].res->buf,
1315 dec->cs, PIPE_TRANSFER_WRITE);
1316 }
1317
1318 /**
1319 * decode a macroblock
1320 */
1321 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
1322 struct pipe_video_buffer *target,
1323 struct pipe_picture_desc *picture,
1324 const struct pipe_macroblock *macroblocks,
1325 unsigned num_macroblocks)
1326 {
1327 /* not supported (yet) */
1328 assert(0);
1329 }
1330
1331 /**
1332 * decode a bitstream
1333 */
1334 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
1335 struct pipe_video_buffer *target,
1336 struct pipe_picture_desc *picture,
1337 unsigned num_buffers,
1338 const void * const *buffers,
1339 const unsigned *sizes)
1340 {
1341 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1342 unsigned i;
1343
1344 assert(decoder);
1345
1346 if (!dec->bs_ptr)
1347 return;
1348
1349 for (i = 0; i < num_buffers; ++i) {
1350 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1351 unsigned new_size = dec->bs_size + sizes[i];
1352
1353 if (new_size > buf->res->buf->size) {
1354 dec->ws->buffer_unmap(buf->res->buf);
1355 if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1356 RVID_ERR("Can't resize bitstream buffer!");
1357 return;
1358 }
1359
1360 dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1361 PIPE_TRANSFER_WRITE);
1362 if (!dec->bs_ptr)
1363 return;
1364
1365 dec->bs_ptr += dec->bs_size;
1366 }
1367
1368 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1369 dec->bs_size += sizes[i];
1370 dec->bs_ptr += sizes[i];
1371 }
1372 }
1373
1374 /**
1375 * send cmd for vcn dec
1376 */
1377 void send_cmd_dec(struct radeon_decoder *dec,
1378 struct pipe_video_buffer *target,
1379 struct pipe_picture_desc *picture)
1380 {
1381 struct pb_buffer *dt;
1382 struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
1383
1384 msg_fb_it_probs_buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1385 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1386
1387 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
1388 dec->ws->buffer_unmap(bs_buf->res->buf);
1389
1390 map_msg_fb_it_probs_buf(dec);
1391 dt = rvcn_dec_message_decode(dec, target, picture);
1392 rvcn_dec_message_feedback(dec);
1393 send_msg_buf(dec);
1394
1395 send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1396 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1397 if (dec->ctx.res)
1398 send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1399 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1400 send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1401 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1402 send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
1403 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1404 send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf,
1405 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1406 if (have_it(dec))
1407 send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
1408 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1409 else if (have_probs(dec))
1410 send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, msg_fb_it_probs_buf->res->buf,
1411 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1412 set_reg(dec, RDECODE_ENGINE_CNTL, 1);
1413 }
1414
1415 /**
1416 * end decoding of the current frame
1417 */
1418 static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
1419 struct pipe_video_buffer *target,
1420 struct pipe_picture_desc *picture)
1421 {
1422 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1423
1424 assert(decoder);
1425
1426 if (!dec->bs_ptr)
1427 return;
1428
1429 dec->send_cmd(dec, target, picture);
1430
1431 flush(dec, PIPE_FLUSH_ASYNC);
1432 next_buffer(dec);
1433 }
1434
1435 /**
1436 * flush any outstanding command buffers to the hardware
1437 */
1438 static void radeon_dec_flush(struct pipe_video_codec *decoder)
1439 {
1440 }
1441
1442 /**
1443 * create and HW decoder
1444 */
1445 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
1446 const struct pipe_video_codec *templ)
1447 {
1448 struct si_context *sctx = (struct si_context*)context;
1449 struct radeon_winsys *ws = sctx->ws;
1450 unsigned width = templ->width, height = templ->height;
1451 unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
1452 struct radeon_decoder *dec;
1453 int r, i;
1454
1455 switch(u_reduce_video_profile(templ->profile)) {
1456 case PIPE_VIDEO_FORMAT_MPEG12:
1457 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1458 return vl_create_mpeg12_decoder(context, templ);
1459 stream_type = RDECODE_CODEC_MPEG2_VLD;
1460 break;
1461 case PIPE_VIDEO_FORMAT_MPEG4:
1462 width = align(width, VL_MACROBLOCK_WIDTH);
1463 height = align(height, VL_MACROBLOCK_HEIGHT);
1464 stream_type = RDECODE_CODEC_MPEG4;
1465 break;
1466 case PIPE_VIDEO_FORMAT_VC1:
1467 stream_type = RDECODE_CODEC_VC1;
1468 break;
1469 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1470 width = align(width, VL_MACROBLOCK_WIDTH);
1471 height = align(height, VL_MACROBLOCK_HEIGHT);
1472 stream_type = RDECODE_CODEC_H264_PERF;
1473 break;
1474 case PIPE_VIDEO_FORMAT_HEVC:
1475 stream_type = RDECODE_CODEC_H265;
1476 break;
1477 case PIPE_VIDEO_FORMAT_VP9:
1478 stream_type = RDECODE_CODEC_VP9;
1479 break;
1480 case PIPE_VIDEO_FORMAT_JPEG:
1481 stream_type = RDECODE_CODEC_JPEG;
1482 ring = RING_VCN_JPEG;
1483 break;
1484 default:
1485 assert(0);
1486 break;
1487 }
1488
1489 dec = CALLOC_STRUCT(radeon_decoder);
1490
1491 if (!dec)
1492 return NULL;
1493
1494 dec->base = *templ;
1495 dec->base.context = context;
1496 dec->base.width = width;
1497 dec->base.height = height;
1498
1499 dec->base.destroy = radeon_dec_destroy;
1500 dec->base.begin_frame = radeon_dec_begin_frame;
1501 dec->base.decode_macroblock = radeon_dec_decode_macroblock;
1502 dec->base.decode_bitstream = radeon_dec_decode_bitstream;
1503 dec->base.end_frame = radeon_dec_end_frame;
1504 dec->base.flush = radeon_dec_flush;
1505
1506 dec->stream_type = stream_type;
1507 dec->stream_handle = si_vid_alloc_stream_handle();
1508 dec->screen = context->screen;
1509 dec->ws = ws;
1510 dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL);
1511 if (!dec->cs) {
1512 RVID_ERR("Can't get command submission context.\n");
1513 goto error;
1514 }
1515
1516 for (i = 0; i < 16; i++)
1517 dec->render_pic_list[i] = NULL;
1518 bs_buf_size = width * height * (512 / (16 * 16));
1519 for (i = 0; i < NUM_BUFFERS; ++i) {
1520 unsigned msg_fb_it_probs_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1521 if (have_it(dec))
1522 msg_fb_it_probs_size += IT_SCALING_TABLE_SIZE;
1523 else if (have_probs(dec))
1524 msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
1525 /* use vram to improve performance, workaround an unknown bug */
1526 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i],
1527 msg_fb_it_probs_size, PIPE_USAGE_DEFAULT)) {
1528 RVID_ERR("Can't allocated message buffers.\n");
1529 goto error;
1530 }
1531
1532 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
1533 bs_buf_size, PIPE_USAGE_STAGING)) {
1534 RVID_ERR("Can't allocated bitstream buffers.\n");
1535 goto error;
1536 }
1537
1538 si_vid_clear_buffer(context, &dec->msg_fb_it_probs_buffers[i]);
1539 si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1540
1541 if (have_probs(dec)) {
1542 struct rvid_buffer* buf;
1543 void *ptr;
1544
1545 buf = &dec->msg_fb_it_probs_buffers[i];
1546 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
1547 ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1548 fill_probs_table(ptr);
1549 dec->ws->buffer_unmap(buf->res->buf);
1550 }
1551 }
1552
1553 dpb_size = calc_dpb_size(dec);
1554 if (dpb_size) {
1555 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1556 RVID_ERR("Can't allocated dpb.\n");
1557 goto error;
1558 }
1559 si_vid_clear_buffer(context, &dec->dpb);
1560 }
1561
1562 if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
1563 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1564 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1565 RVID_ERR("Can't allocated context buffer.\n");
1566 goto error;
1567 }
1568 si_vid_clear_buffer(context, &dec->ctx);
1569 }
1570
1571 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
1572 RDECODE_SESSION_CONTEXT_SIZE,
1573 PIPE_USAGE_DEFAULT)) {
1574 RVID_ERR("Can't allocated session ctx.\n");
1575 goto error;
1576 }
1577 si_vid_clear_buffer(context, &dec->sessionctx);
1578
1579 map_msg_fb_it_probs_buf(dec);
1580 rvcn_dec_message_create(dec);
1581 send_msg_buf(dec);
1582 r = flush(dec, 0);
1583 if (r)
1584 goto error;
1585
1586 next_buffer(dec);
1587
1588 if (stream_type == RDECODE_CODEC_JPEG)
1589 dec->send_cmd = send_cmd_jpeg;
1590 else
1591 dec->send_cmd = send_cmd_dec;
1592
1593 return &dec->base;
1594
1595 error:
1596 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1597
1598 for (i = 0; i < NUM_BUFFERS; ++i) {
1599 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1600 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1601 }
1602
1603 si_vid_destroy_buffer(&dec->dpb);
1604 si_vid_destroy_buffer(&dec->ctx);
1605 si_vid_destroy_buffer(&dec->sessionctx);
1606
1607 FREE(dec);
1608
1609 return NULL;
1610 }