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radeonsi: use r600_resource() typecast helper
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <assert.h>
29 #include <stdio.h>
30
31 #include "pipe/p_video_codec.h"
32
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35
36 #include "vl/vl_mpeg12_decoder.h"
37
38 #include "radeonsi/si_pipe.h"
39 #include "radeon_video.h"
40 #include "radeon_vcn_dec.h"
41 #include "vl/vl_probs_table.h"
42
43 #define FB_BUFFER_OFFSET 0x1000
44 #define FB_BUFFER_SIZE 2048
45 #define IT_SCALING_TABLE_SIZE 992
46 #define VP9_PROBS_TABLE_SIZE (RDECODE_VP9_PROBS_DATA_SIZE + 256)
47 #define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)
48
49 #define RDECODE_GPCOM_VCPU_CMD 0x2070c
50 #define RDECODE_GPCOM_VCPU_DATA0 0x20710
51 #define RDECODE_GPCOM_VCPU_DATA1 0x20714
52 #define RDECODE_ENGINE_CNTL 0x20718
53
54 #define NUM_BUFFERS 4
55 #define NUM_MPEG2_REFS 6
56 #define NUM_H264_REFS 17
57 #define NUM_VC1_REFS 5
58 #define NUM_VP9_REFS 8
59
60 struct radeon_decoder {
61 struct pipe_video_codec base;
62
63 unsigned stream_handle;
64 unsigned stream_type;
65 unsigned frame_number;
66
67 struct pipe_screen *screen;
68 struct radeon_winsys *ws;
69 struct radeon_winsys_cs *cs;
70
71 void *msg;
72 uint32_t *fb;
73 uint8_t *it;
74 uint8_t *probs;
75 void *bs_ptr;
76
77 struct rvid_buffer msg_fb_it_probs_buffers[NUM_BUFFERS];
78 struct rvid_buffer bs_buffers[NUM_BUFFERS];
79 struct rvid_buffer dpb;
80 struct rvid_buffer ctx;
81 struct rvid_buffer sessionctx;
82
83 unsigned bs_size;
84 unsigned cur_buffer;
85 void *render_pic_list[16];
86 bool show_frame;
87 unsigned ref_idx;
88 };
89
90 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
91 struct pipe_h264_picture_desc *pic)
92 {
93 rvcn_dec_message_avc_t result;
94
95 memset(&result, 0, sizeof(result));
96 switch (pic->base.profile) {
97 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
98 result.profile = RDECODE_H264_PROFILE_BASELINE;
99 break;
100
101 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
102 result.profile = RDECODE_H264_PROFILE_MAIN;
103 break;
104
105 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
106 result.profile = RDECODE_H264_PROFILE_HIGH;
107 break;
108
109 default:
110 assert(0);
111 break;
112 }
113
114 result.level = dec->base.level;
115
116 result.sps_info_flags = 0;
117 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
118 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
119 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
120 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
121 result.sps_info_flags |= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT;
122
123 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
124 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
125 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
126 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
127 result.log2_max_pic_order_cnt_lsb_minus4 =
128 pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
129
130 switch (dec->base.chroma_format) {
131 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
132 break;
133 case PIPE_VIDEO_CHROMA_FORMAT_400:
134 result.chroma_format = 0;
135 break;
136 case PIPE_VIDEO_CHROMA_FORMAT_420:
137 result.chroma_format = 1;
138 break;
139 case PIPE_VIDEO_CHROMA_FORMAT_422:
140 result.chroma_format = 2;
141 break;
142 case PIPE_VIDEO_CHROMA_FORMAT_444:
143 result.chroma_format = 3;
144 break;
145 }
146
147 result.pps_info_flags = 0;
148 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
149 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
150 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
151 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
152 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
153 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
154 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
155 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
156
157 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
158 result.slice_group_map_type = pic->pps->slice_group_map_type;
159 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
160 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
161 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
162 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
163
164 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
165 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
166
167 memcpy(dec->it, result.scaling_list_4x4, 6*16);
168 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
169
170 result.num_ref_frames = pic->num_ref_frames;
171
172 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
173 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
174
175 result.frame_num = pic->frame_num;
176 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
177 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
178 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
179 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
180
181 result.decoded_pic_idx = pic->frame_num;
182
183 return result;
184 }
185
186 static void radeon_dec_destroy_associated_data(void *data)
187 {
188 /* NOOP, since we only use an intptr */
189 }
190
191 static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
192 struct pipe_video_buffer *target,
193 struct pipe_h265_picture_desc *pic)
194 {
195 rvcn_dec_message_hevc_t result;
196 unsigned i, j;
197
198 memset(&result, 0, sizeof(result));
199 result.sps_info_flags = 0;
200 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
201 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
202 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
203 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
204 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
205 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
206 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
207 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
208 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
209 if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
210 result.sps_info_flags |= 1 << 9;
211 if (pic->UseRefPicList == true)
212 result.sps_info_flags |= 1 << 10;
213
214 result.chroma_format = pic->pps->sps->chroma_format_idc;
215 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
216 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
217 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
218 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
219 result.log2_min_luma_coding_block_size_minus3 =
220 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
221 result.log2_diff_max_min_luma_coding_block_size =
222 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
223 result.log2_min_transform_block_size_minus2 =
224 pic->pps->sps->log2_min_transform_block_size_minus2;
225 result.log2_diff_max_min_transform_block_size =
226 pic->pps->sps->log2_diff_max_min_transform_block_size;
227 result.max_transform_hierarchy_depth_inter =
228 pic->pps->sps->max_transform_hierarchy_depth_inter;
229 result.max_transform_hierarchy_depth_intra =
230 pic->pps->sps->max_transform_hierarchy_depth_intra;
231 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
232 result.pcm_sample_bit_depth_chroma_minus1 =
233 pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
234 result.log2_min_pcm_luma_coding_block_size_minus3 =
235 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
236 result.log2_diff_max_min_pcm_luma_coding_block_size =
237 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
238 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
239
240 result.pps_info_flags = 0;
241 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
242 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
243 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
244 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
245 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
246 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
247 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
248 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
249 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
250 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
251 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
252 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
253 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
254 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
255 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
256 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
257 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
258 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
259 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
260 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
261
262 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
263 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
264 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
265 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
266 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
267 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
268 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
269 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
270 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
271 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
272 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
273 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
274 result.init_qp_minus26 = pic->pps->init_qp_minus26;
275
276 for (i = 0; i < 19; ++i)
277 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
278
279 for (i = 0; i < 21; ++i)
280 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
281
282 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
283 result.curr_poc = pic->CurrPicOrderCntVal;
284
285 for (i = 0 ; i < 16 ; i++) {
286 for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
287 if (dec->render_pic_list[i] == pic->ref[j])
288 break;
289 if (j == 15)
290 dec->render_pic_list[i] = NULL;
291 else if (pic->ref[j+1] == NULL)
292 dec->render_pic_list[i] = NULL;
293 }
294 }
295 for (i = 0 ; i < 16 ; i++) {
296 if (dec->render_pic_list[i] == NULL) {
297 dec->render_pic_list[i] = target;
298 result.curr_idx = i;
299 break;
300 }
301 }
302
303 vl_video_buffer_set_associated_data(target, &dec->base,
304 (void *)(uintptr_t)result.curr_idx,
305 &radeon_dec_destroy_associated_data);
306
307 for (i = 0; i < 16; ++i) {
308 struct pipe_video_buffer *ref = pic->ref[i];
309 uintptr_t ref_pic = 0;
310
311 result.poc_list[i] = pic->PicOrderCntVal[i];
312
313 if (ref)
314 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
315 else
316 ref_pic = 0x7F;
317 result.ref_pic_list[i] = ref_pic;
318 }
319
320 for (i = 0; i < 8; ++i) {
321 result.ref_pic_set_st_curr_before[i] = 0xFF;
322 result.ref_pic_set_st_curr_after[i] = 0xFF;
323 result.ref_pic_set_lt_curr[i] = 0xFF;
324 }
325
326 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
327 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
328
329 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
330 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
331
332 for (i = 0; i < pic->NumPocLtCurr; ++i)
333 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
334
335 for (i = 0; i < 6; ++i)
336 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
337
338 for (i = 0; i < 2; ++i)
339 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
340
341 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
342 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
343 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
344 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
345
346 for (i = 0 ; i < 2 ; i++) {
347 for (j = 0 ; j < 15 ; j++)
348 result.direct_reflist[i][j] = pic->RefPicList[i][j];
349 }
350
351 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
352 if (target->buffer_format == PIPE_FORMAT_P016) {
353 result.p010_mode = 1;
354 result.msb_mode = 1;
355 } else {
356 result.p010_mode = 0;
357 result.luma_10to8 = 5;
358 result.chroma_10to8 = 5;
359 result.hevc_reserved[0] = 4; /* sclr_luma10to8 */
360 result.hevc_reserved[1] = 4; /* sclr_chroma10to8 */
361 }
362 }
363
364 return result;
365 }
366
367 static void fill_probs_table(void *ptr)
368 {
369 rvcn_dec_vp9_probs_t *probs = (rvcn_dec_vp9_probs_t *)ptr;
370
371 memcpy(&probs->coef_probs[0], default_coef_probs_4x4, sizeof(default_coef_probs_4x4));
372 memcpy(&probs->coef_probs[1], default_coef_probs_8x8, sizeof(default_coef_probs_8x8));
373 memcpy(&probs->coef_probs[2], default_coef_probs_16x16, sizeof(default_coef_probs_16x16));
374 memcpy(&probs->coef_probs[3], default_coef_probs_32x32, sizeof(default_coef_probs_32x32));
375 memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
376 memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
377 memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
378 memcpy(probs->switchable_interp_prob, default_switchable_interp_prob, sizeof(default_switchable_interp_prob));
379 memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
380 memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
381 memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
382 memcpy(probs->intra_inter_prob, default_intra_inter_p, sizeof(default_intra_inter_p));
383 memcpy(probs->comp_inter_prob, default_comp_inter_p, sizeof(default_comp_inter_p));
384 memcpy(probs->comp_ref_prob, default_comp_ref_p, sizeof(default_comp_ref_p));
385 memcpy(probs->tx_probs_32x32, default_tx_probs_32x32, sizeof(default_tx_probs_32x32));
386 memcpy(probs->tx_probs_16x16, default_tx_probs_16x16, sizeof(default_tx_probs_16x16));
387 memcpy(probs->tx_probs_8x8, default_tx_probs_8x8, sizeof(default_tx_probs_8x8));
388 memcpy(probs->mv_joints, default_nmv_joints, sizeof(default_nmv_joints));
389 memcpy(&probs->mv_comps[0], default_nmv_components, sizeof(default_nmv_components));
390 memset(&probs->nmvc_mask, 0, sizeof(rvcn_dec_vp9_nmv_ctx_mask_t));
391 }
392
393 static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
394 struct pipe_video_buffer *target,
395 struct pipe_vp9_picture_desc *pic)
396 {
397 rvcn_dec_message_vp9_t result;
398 unsigned i;
399
400 memset(&result, 0, sizeof(result));
401
402 /* segment table */
403 rvcn_dec_vp9_probs_segment_t *prbs = (rvcn_dec_vp9_probs_segment_t *)(dec->probs);
404
405 if (pic->picture_parameter.pic_fields.segmentation_enabled) {
406 for (i = 0; i < 8; ++i) {
407 prbs->seg.feature_data[i] =
408 (pic->slice_parameter.seg_param[i].alt_quant & 0xffff) |
409 ((pic->slice_parameter.seg_param[i].alt_lf & 0xff) << 16) |
410 ((pic->slice_parameter.seg_param[i].segment_flags.segment_reference & 0xf) << 24);
411 prbs->seg.feature_mask[i] =
412 (pic->slice_parameter.seg_param[i].alt_quant_enabled << 0) |
413 (pic->slice_parameter.seg_param[i].alt_lf_enabled << 1) |
414 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_enabled << 2) |
415 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_skipped << 3);
416 }
417
418 for (i = 0; i < 7; ++i)
419 prbs->seg.tree_probs[i] = pic->picture_parameter.mb_segment_tree_probs[i];
420
421 for (i = 0; i < 3; ++i)
422 prbs->seg.pred_probs[i] = pic->picture_parameter.segment_pred_probs[i];
423
424 prbs->seg.abs_delta = 0;
425 } else
426 memset(&prbs->seg, 0, 256);
427
428 result.frame_header_flags =
429 (pic->picture_parameter.pic_fields.frame_type <<
430 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
431 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
432
433 result.frame_header_flags |=
434 (pic->picture_parameter.pic_fields.error_resilient_mode <<
435 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
436 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
437
438 result.frame_header_flags |=
439 (pic->picture_parameter.pic_fields.intra_only <<
440 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
441 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
442
443 result.frame_header_flags |=
444 (pic->picture_parameter.pic_fields.allow_high_precision_mv <<
445 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
446 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
447
448 result.frame_header_flags |=
449 (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode <<
450 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
451 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
452
453 result.frame_header_flags |=
454 (pic->picture_parameter.pic_fields.refresh_frame_context <<
455 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
456 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
457
458 result.frame_header_flags |=
459 (pic->picture_parameter.pic_fields.segmentation_enabled <<
460 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
461 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
462
463 result.frame_header_flags |=
464 (pic->picture_parameter.pic_fields.segmentation_update_map <<
465 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
466 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
467
468 result.frame_header_flags |=
469 (pic->picture_parameter.pic_fields.segmentation_temporal_update <<
470 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
471 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
472
473 result.frame_header_flags |=
474 (pic->picture_parameter.mode_ref_delta_enabled <<
475 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
476 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
477
478 result.frame_header_flags |=
479 (pic->picture_parameter.mode_ref_delta_update <<
480 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
481 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
482
483 result.frame_header_flags |= ((dec->show_frame &&
484 !pic->picture_parameter.pic_fields.error_resilient_mode)
485 << RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
486 RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
487 dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
488
489 result.interp_filter = pic->picture_parameter.pic_fields.mcomp_filter_type;
490
491 result.frame_context_idx = pic->picture_parameter.pic_fields.frame_context_idx;
492 result.reset_frame_context = pic->picture_parameter.pic_fields.reset_frame_context;
493
494 result.filter_level = pic->picture_parameter.filter_level;
495 result.sharpness_level = pic->picture_parameter.sharpness_level;
496
497 for (i = 0; i < 8; ++i)
498 memcpy(result.lf_adj_level[i], pic->slice_parameter.seg_param[i].filter_level, 4 * 2);
499
500 if (pic->picture_parameter.pic_fields.lossless_flag) {
501 result.base_qindex = 0;
502 result.y_dc_delta_q = 0;
503 result.uv_ac_delta_q = 0;
504 result.uv_dc_delta_q = 0;
505 } else {
506 result.base_qindex = pic->picture_parameter.base_qindex;
507 result.y_dc_delta_q = pic->picture_parameter.y_dc_delta_q;
508 result.uv_ac_delta_q = pic->picture_parameter.uv_ac_delta_q;
509 result.uv_dc_delta_q = pic->picture_parameter.uv_dc_delta_q;
510 }
511
512 result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
513 result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
514 result.chroma_format = 1;
515 result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8
516 = (pic->picture_parameter.bit_depth - 8);
517
518 result.vp9_frame_size = align(dec->bs_size, 128);
519 result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
520 result.compressed_header_size = pic->picture_parameter.first_partition_size;
521
522 assert(dec->base.max_references + 1 <= 16);
523
524 for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
525 if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
526 result.curr_pic_idx =
527 (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
528 break;
529 } else if (!dec->render_pic_list[i]) {
530 dec->render_pic_list[i] = target;
531 result.curr_pic_idx = dec->ref_idx;
532 vl_video_buffer_set_associated_data(target, &dec->base,
533 (void *)(uintptr_t)dec->ref_idx++,
534 &radeon_dec_destroy_associated_data);
535 break;
536 }
537 }
538
539 for (i = 0 ; i < 8; i++) {
540 result.ref_frame_map[i] = (pic->ref[i]) ?
541 (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) :
542 0x7f;
543 }
544
545 result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
546 result.ref_frame_sign_bias[0] = pic->picture_parameter.pic_fields.last_ref_frame_sign_bias;
547 result.frame_refs[1] = result.ref_frame_map[pic->picture_parameter.pic_fields.golden_ref_frame];
548 result.ref_frame_sign_bias[1] = pic->picture_parameter.pic_fields.golden_ref_frame_sign_bias;
549 result.frame_refs[2] = result.ref_frame_map[pic->picture_parameter.pic_fields.alt_ref_frame];
550 result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
551
552 if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
553 if (target->buffer_format == PIPE_FORMAT_P016) {
554 result.p010_mode = 1;
555 result.msb_mode = 1;
556 } else {
557 result.p010_mode = 0;
558 result.luma_10to8 = 1;
559 result.chroma_10to8 = 1;
560 }
561 }
562
563 return result;
564 }
565
566 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
567 {
568 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
569 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
570
571 unsigned max_references = dec->base.max_references + 1;
572
573 if (dec->base.width * dec->base.height >= 4096*2000)
574 max_references = MAX2(max_references, 8);
575 else
576 max_references = MAX2(max_references, 17);
577
578 width = align (width, 16);
579 height = align (height, 16);
580 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
581 }
582
583 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
584 {
585 unsigned block_size, log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
586 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
587 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
588
589 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
590 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
591 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 ||
592 pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
593
594 unsigned max_references = dec->base.max_references + 1;
595
596 if (dec->base.width * dec->base.height >= 4096*2000)
597 max_references = MAX2(max_references, 8);
598 else
599 max_references = MAX2(max_references, 17);
600
601 block_size = (1 << (pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3));
602 log2_ctb_size = block_size + pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
603
604 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
605 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
606
607 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
608 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
609 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
610
611 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
612 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
613
614 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
615 }
616
617 static rvcn_dec_message_vc1_t get_vc1_msg(struct pipe_vc1_picture_desc *pic)
618 {
619 rvcn_dec_message_vc1_t result;
620
621 memset(&result, 0, sizeof(result));
622 switch(pic->base.profile) {
623 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
624 result.profile = RDECODE_VC1_PROFILE_SIMPLE;
625 result.level = 1;
626 break;
627
628 case PIPE_VIDEO_PROFILE_VC1_MAIN:
629 result.profile = RDECODE_VC1_PROFILE_MAIN;
630 result.level = 2;
631 break;
632
633 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
634 result.profile = RDECODE_VC1_PROFILE_ADVANCED;
635 result.level = 4;
636 break;
637
638 default:
639 assert(0);
640 }
641
642 result.sps_info_flags |= pic->postprocflag << 7;
643 result.sps_info_flags |= pic->pulldown << 6;
644 result.sps_info_flags |= pic->interlace << 5;
645 result.sps_info_flags |= pic->tfcntrflag << 4;
646 result.sps_info_flags |= pic->finterpflag << 3;
647 result.sps_info_flags |= pic->psf << 1;
648
649 result.pps_info_flags |= pic->range_mapy_flag << 31;
650 result.pps_info_flags |= pic->range_mapy << 28;
651 result.pps_info_flags |= pic->range_mapuv_flag << 27;
652 result.pps_info_flags |= pic->range_mapuv << 24;
653 result.pps_info_flags |= pic->multires << 21;
654 result.pps_info_flags |= pic->maxbframes << 16;
655 result.pps_info_flags |= pic->overlap << 11;
656 result.pps_info_flags |= pic->quantizer << 9;
657 result.pps_info_flags |= pic->panscan_flag << 7;
658 result.pps_info_flags |= pic->refdist_flag << 6;
659 result.pps_info_flags |= pic->vstransform << 0;
660
661 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
662 result.pps_info_flags |= pic->syncmarker << 20;
663 result.pps_info_flags |= pic->rangered << 19;
664 result.pps_info_flags |= pic->loopfilter << 5;
665 result.pps_info_flags |= pic->fastuvmc << 4;
666 result.pps_info_flags |= pic->extended_mv << 3;
667 result.pps_info_flags |= pic->extended_dmv << 8;
668 result.pps_info_flags |= pic->dquant << 1;
669 }
670
671 result.chroma_format = 1;
672
673 return result;
674 }
675
676 static uint32_t get_ref_pic_idx(struct radeon_decoder *dec, struct pipe_video_buffer *ref)
677 {
678 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
679 uint32_t max = MAX2(dec->frame_number, 1) - 1;
680 uintptr_t frame;
681
682 /* seems to be the most sane fallback */
683 if (!ref)
684 return max;
685
686 /* get the frame number from the associated data */
687 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
688
689 /* limit the frame number to a valid range */
690 return MAX2(MIN2(frame, max), min);
691 }
692
693 static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct radeon_decoder *dec,
694 struct pipe_mpeg12_picture_desc *pic)
695 {
696 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
697 rvcn_dec_message_mpeg2_vld_t result;
698 unsigned i;
699
700 memset(&result, 0, sizeof(result));
701 result.decoded_pic_idx = dec->frame_number;
702
703 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
704 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
705
706 if(pic->intra_matrix) {
707 result.load_intra_quantiser_matrix = 1;
708 for (i = 0; i < 64; ++i) {
709 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
710 }
711 }
712 if(pic->non_intra_matrix) {
713 result.load_nonintra_quantiser_matrix = 1;
714 for (i = 0; i < 64; ++i) {
715 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
716 }
717 }
718
719 result.profile_and_level_indication = 0;
720 result.chroma_format = 0x1;
721
722 result.picture_coding_type = pic->picture_coding_type;
723 result.f_code[0][0] = pic->f_code[0][0] + 1;
724 result.f_code[0][1] = pic->f_code[0][1] + 1;
725 result.f_code[1][0] = pic->f_code[1][0] + 1;
726 result.f_code[1][1] = pic->f_code[1][1] + 1;
727 result.intra_dc_precision = pic->intra_dc_precision;
728 result.pic_structure = pic->picture_structure;
729 result.top_field_first = pic->top_field_first;
730 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
731 result.concealment_motion_vectors = pic->concealment_motion_vectors;
732 result.q_scale_type = pic->q_scale_type;
733 result.intra_vlc_format = pic->intra_vlc_format;
734 result.alternate_scan = pic->alternate_scan;
735
736 return result;
737 }
738
739 static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec,
740 struct pipe_mpeg4_picture_desc *pic)
741 {
742 rvcn_dec_message_mpeg4_asp_vld_t result;
743 unsigned i;
744
745 memset(&result, 0, sizeof(result));
746 result.decoded_pic_idx = dec->frame_number;
747
748 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
749 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
750
751 result.variant_type = 0;
752 result.profile_and_level_indication = 0xF0;
753
754 result.video_object_layer_verid = 0x5;
755 result.video_object_layer_shape = 0x0;
756
757 result.video_object_layer_width = dec->base.width;
758 result.video_object_layer_height = dec->base.height;
759
760 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
761
762 result.short_video_header = pic->short_video_header;
763 result.interlaced = pic->interlaced;
764 result.load_intra_quant_mat = 1;
765 result.load_nonintra_quant_mat = 1;
766 result.quarter_sample = pic->quarter_sample;
767 result.complexity_estimation_disable = 1;
768 result.resync_marker_disable = pic->resync_marker_disable;
769 result.newpred_enable = 0;
770 result.reduced_resolution_vop_enable = 0;
771
772 result.quant_type = pic->quant_type;
773
774 for (i = 0; i < 64; ++i) {
775 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
776 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
777 }
778
779 return result;
780 }
781
782 static void rvcn_dec_message_create(struct radeon_decoder *dec)
783 {
784 rvcn_dec_message_header_t *header = dec->msg;
785 rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
786 unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
787
788 memset(dec->msg, 0, sizes);
789 header->header_size = sizeof(rvcn_dec_message_header_t);
790 header->total_size = sizes;
791 header->num_buffers = 1;
792 header->msg_type = RDECODE_MSG_CREATE;
793 header->stream_handle = dec->stream_handle;
794 header->status_report_feedback_number = 0;
795
796 header->index[0].message_id = RDECODE_MESSAGE_CREATE;
797 header->index[0].offset = sizeof(rvcn_dec_message_header_t);
798 header->index[0].size = sizeof(rvcn_dec_message_create_t);
799 header->index[0].filled = 0;
800
801 create->stream_type = dec->stream_type;
802 create->session_flags = 0;
803 create->width_in_samples = dec->base.width;
804 create->height_in_samples = dec->base.height;
805 }
806
807 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
808 struct pipe_video_buffer *target,
809 struct pipe_picture_desc *picture)
810 {
811 struct r600_texture *luma = (struct r600_texture *)
812 ((struct vl_video_buffer *)target)->resources[0];
813 struct r600_texture *chroma = (struct r600_texture *)
814 ((struct vl_video_buffer *)target)->resources[1];
815 rvcn_dec_message_header_t *header;
816 rvcn_dec_message_index_t *index;
817 rvcn_dec_message_decode_t *decode;
818 unsigned sizes = 0, offset_decode, offset_codec;
819 void *codec;
820
821 header = dec->msg;
822 sizes += sizeof(rvcn_dec_message_header_t);
823 index = (void*)header + sizeof(rvcn_dec_message_header_t);
824 sizes += sizeof(rvcn_dec_message_index_t);
825 offset_decode = sizes;
826 decode = (void*)index + sizeof(rvcn_dec_message_index_t);
827 sizes += sizeof(rvcn_dec_message_decode_t);
828 offset_codec = sizes;
829 codec = (void*)decode + sizeof(rvcn_dec_message_decode_t);
830
831 memset(dec->msg, 0, sizes);
832 header->header_size = sizeof(rvcn_dec_message_header_t);
833 header->total_size = sizes;
834 header->num_buffers = 2;
835 header->msg_type = RDECODE_MSG_DECODE;
836 header->stream_handle = dec->stream_handle;
837 header->status_report_feedback_number = dec->frame_number;
838
839 header->index[0].message_id = RDECODE_MESSAGE_DECODE;
840 header->index[0].offset = offset_decode;
841 header->index[0].size = sizeof(rvcn_dec_message_decode_t);
842 header->index[0].filled = 0;
843
844 index->offset = offset_codec;
845 index->size = sizeof(rvcn_dec_message_avc_t);
846 index->filled = 0;
847
848 decode->stream_type = dec->stream_type;
849 decode->decode_flags = 0x1;
850 decode->width_in_samples = dec->base.width;
851 decode->height_in_samples = dec->base.height;
852
853 decode->bsd_size = align(dec->bs_size, 128);
854 decode->dpb_size = dec->dpb.res->buf->size;
855 decode->dt_size =
856 r600_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
857 r600_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
858
859 decode->sct_size = 0;
860 decode->sc_coeff_size = 0;
861
862 decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
863 decode->db_pitch = align(dec->base.width, 32);
864 decode->db_surf_tile_config = 0;
865
866 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
867 decode->dt_uv_pitch = decode->dt_pitch / 2;
868
869 decode->dt_tiling_mode = 0;
870 decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
871 decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
872 decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
873 decode->dt_surf_tile_config = 0;
874 decode->dt_uv_surf_tile_config = 0;
875
876 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
877 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
878 if (decode->dt_field_mode) {
879 decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset +
880 luma->surface.u.gfx9.surf_slice_size;
881 decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset +
882 chroma->surface.u.gfx9.surf_slice_size;
883 } else {
884 decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
885 decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
886 }
887
888 switch (u_reduce_video_profile(picture->profile)) {
889 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
890 rvcn_dec_message_avc_t avc =
891 get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
892 memcpy(codec, (void*)&avc, sizeof(rvcn_dec_message_avc_t));
893 index->message_id = RDECODE_MESSAGE_AVC;
894 break;
895 }
896 case PIPE_VIDEO_FORMAT_HEVC: {
897 rvcn_dec_message_hevc_t hevc =
898 get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
899
900 memcpy(codec, (void*)&hevc, sizeof(rvcn_dec_message_hevc_t));
901 index->message_id = RDECODE_MESSAGE_HEVC;
902 if (dec->ctx.res == NULL) {
903 unsigned ctx_size;
904 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
905 ctx_size = calc_ctx_size_h265_main10(dec,
906 (struct pipe_h265_picture_desc*)picture);
907 else
908 ctx_size = calc_ctx_size_h265_main(dec);
909 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
910 RVID_ERR("Can't allocated context buffer.\n");
911 si_vid_clear_buffer(dec->base.context, &dec->ctx);
912 }
913 break;
914 }
915 case PIPE_VIDEO_FORMAT_VC1: {
916 rvcn_dec_message_vc1_t vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
917
918 memcpy(codec, (void*)&vc1, sizeof(rvcn_dec_message_vc1_t));
919 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
920 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
921 decode->width_in_samples = align(decode->width_in_samples, 16) / 16;
922 decode->height_in_samples = align(decode->height_in_samples, 16) / 16;
923 }
924 index->message_id = RDECODE_MESSAGE_VC1;
925 break;
926
927 }
928 case PIPE_VIDEO_FORMAT_MPEG12: {
929 rvcn_dec_message_mpeg2_vld_t mpeg2 =
930 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
931
932 memcpy(codec, (void*)&mpeg2, sizeof(rvcn_dec_message_mpeg2_vld_t));
933 index->message_id = RDECODE_MESSAGE_MPEG2_VLD;
934 break;
935 }
936 case PIPE_VIDEO_FORMAT_MPEG4: {
937 rvcn_dec_message_mpeg4_asp_vld_t mpeg4 =
938 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
939
940 memcpy(codec, (void*)&mpeg4, sizeof(rvcn_dec_message_mpeg4_asp_vld_t));
941 index->message_id = RDECODE_MESSAGE_MPEG4_ASP_VLD;
942 break;
943 }
944 case PIPE_VIDEO_FORMAT_VP9: {
945 rvcn_dec_message_vp9_t vp9 =
946 get_vp9_msg(dec, target, (struct pipe_vp9_picture_desc*)picture);
947
948 memcpy(codec, (void*)&vp9, sizeof(rvcn_dec_message_vp9_t));
949 index->message_id = RDECODE_MESSAGE_VP9;
950
951 if (dec->ctx.res == NULL) {
952 unsigned ctx_size;
953 uint8_t *ptr;
954
955 /* default probability + probability data */
956 ctx_size = 2304 * 5;
957
958 /* SRE collocated context data */
959 ctx_size += 32 * 2 * 64 * 64;
960
961 /* SMP collocated context data */
962 ctx_size += 9 * 64 * 2 * 64 * 64;
963
964 /* SDB left tile pixel */
965 ctx_size += 8 * 2 * 4096;
966
967 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
968 ctx_size += 8 * 2 * 4096;
969
970 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
971 RVID_ERR("Can't allocated context buffer.\n");
972 si_vid_clear_buffer(dec->base.context, &dec->ctx);
973
974 /* ctx needs probs table */
975 ptr = dec->ws->buffer_map(dec->ctx.res->buf, dec->cs, PIPE_TRANSFER_WRITE);
976 fill_probs_table(ptr);
977 dec->ws->buffer_unmap(dec->ctx.res->buf);
978 }
979 break;
980 }
981 default:
982 assert(0);
983 return NULL;
984 }
985
986 if (dec->ctx.res)
987 decode->hw_ctxt_size = dec->ctx.res->buf->size;
988
989 return luma->resource.buf;
990 }
991
992 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
993 {
994 rvcn_dec_message_header_t *header = dec->msg;
995
996 memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
997 header->header_size = sizeof(rvcn_dec_message_header_t);
998 header->total_size = sizeof(rvcn_dec_message_header_t) -
999 sizeof(rvcn_dec_message_index_t);
1000 header->num_buffers = 0;
1001 header->msg_type = RDECODE_MSG_DESTROY;
1002 header->stream_handle = dec->stream_handle;
1003 header->status_report_feedback_number = 0;
1004 }
1005
1006 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
1007 {
1008 rvcn_dec_feedback_header_t *header = (void*)dec->fb;
1009
1010 header->header_size = sizeof(rvcn_dec_feedback_header_t);
1011 header->total_size = sizeof(rvcn_dec_feedback_header_t);
1012 header->num_buffers = 0;
1013 }
1014
1015 /* flush IB to the hardware */
1016 static int flush(struct radeon_decoder *dec, unsigned flags)
1017 {
1018 return dec->ws->cs_flush(dec->cs, flags, NULL);
1019 }
1020
1021 /* add a new set register command to the IB */
1022 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
1023 {
1024 radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
1025 radeon_emit(dec->cs, val);
1026 }
1027
1028 /* send a command to the VCPU through the GPCOM registers */
1029 static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
1030 struct pb_buffer* buf, uint32_t off,
1031 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
1032 {
1033 uint64_t addr;
1034
1035 dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
1036 domain, RADEON_PRIO_UVD);
1037 addr = dec->ws->buffer_get_virtual_address(buf);
1038 addr = addr + off;
1039
1040 set_reg(dec, RDECODE_GPCOM_VCPU_DATA0, addr);
1041 set_reg(dec, RDECODE_GPCOM_VCPU_DATA1, addr >> 32);
1042 set_reg(dec, RDECODE_GPCOM_VCPU_CMD, cmd << 1);
1043 }
1044
1045 /* do the codec needs an IT buffer ?*/
1046 static bool have_it(struct radeon_decoder *dec)
1047 {
1048 return dec->stream_type == RDECODE_CODEC_H264_PERF ||
1049 dec->stream_type == RDECODE_CODEC_H265;
1050 }
1051
1052 /* do the codec needs an probs buffer? */
1053 static bool have_probs(struct radeon_decoder *dec)
1054 {
1055 return dec->stream_type == RDECODE_CODEC_VP9;
1056 }
1057
1058 /* map the next available message/feedback/itscaling buffer */
1059 static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
1060 {
1061 struct rvid_buffer* buf;
1062 uint8_t *ptr;
1063
1064 /* grab the current message/feedback buffer */
1065 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1066
1067 /* and map it for CPU access */
1068 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
1069
1070 /* calc buffer offsets */
1071 dec->msg = ptr;
1072
1073 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1074 if (have_it(dec))
1075 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1076 else if (have_probs(dec))
1077 dec->probs = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1078 }
1079
1080 /* unmap and send a message command to the VCPU */
1081 static void send_msg_buf(struct radeon_decoder *dec)
1082 {
1083 struct rvid_buffer* buf;
1084
1085 /* ignore the request if message/feedback buffer isn't mapped */
1086 if (!dec->msg || !dec->fb)
1087 return;
1088
1089 /* grab the current message buffer */
1090 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1091
1092 /* unmap the buffer */
1093 dec->ws->buffer_unmap(buf->res->buf);
1094 dec->msg = NULL;
1095 dec->fb = NULL;
1096 dec->it = NULL;
1097 dec->probs = NULL;
1098
1099 if (dec->sessionctx.res)
1100 send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
1101 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
1102 RADEON_DOMAIN_VRAM);
1103
1104 /* and send it to the hardware */
1105 send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
1106 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1107 }
1108
1109 /* cycle to the next set of buffers */
1110 static void next_buffer(struct radeon_decoder *dec)
1111 {
1112 ++dec->cur_buffer;
1113 dec->cur_buffer %= NUM_BUFFERS;
1114 }
1115
1116 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
1117 {
1118 unsigned width_in_mb, height_in_mb, ctx_size;
1119 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1120 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1121
1122 unsigned max_references = dec->base.max_references + 1;
1123
1124 // picture width & height in 16 pixel units
1125 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1126 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1127
1128 unsigned fs_in_mb = width_in_mb * height_in_mb;
1129 unsigned num_dpb_buffer;
1130 switch(dec->base.level) {
1131 case 30:
1132 num_dpb_buffer = 8100 / fs_in_mb;
1133 break;
1134 case 31:
1135 num_dpb_buffer = 18000 / fs_in_mb;
1136 break;
1137 case 32:
1138 num_dpb_buffer = 20480 / fs_in_mb;
1139 break;
1140 case 41:
1141 num_dpb_buffer = 32768 / fs_in_mb;
1142 break;
1143 case 42:
1144 num_dpb_buffer = 34816 / fs_in_mb;
1145 break;
1146 case 50:
1147 num_dpb_buffer = 110400 / fs_in_mb;
1148 break;
1149 case 51:
1150 num_dpb_buffer = 184320 / fs_in_mb;
1151 break;
1152 default:
1153 num_dpb_buffer = 184320 / fs_in_mb;
1154 break;
1155 }
1156 num_dpb_buffer++;
1157 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1158 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
1159
1160 return ctx_size;
1161 }
1162
1163 /* calculate size of reference picture buffer */
1164 static unsigned calc_dpb_size(struct radeon_decoder *dec)
1165 {
1166 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
1167
1168 // always align them to MB size for dpb calculation
1169 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1170 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1171
1172 // always one more for currently decoded picture
1173 unsigned max_references = dec->base.max_references + 1;
1174
1175 // aligned size of a single frame
1176 image_size = align(width, 32) * height;
1177 image_size += image_size / 2;
1178 image_size = align(image_size, 1024);
1179
1180 // picture width & height in 16 pixel units
1181 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1182 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1183
1184 switch (u_reduce_video_profile(dec->base.profile)) {
1185 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1186 unsigned fs_in_mb = width_in_mb * height_in_mb;
1187 unsigned num_dpb_buffer;
1188
1189 switch(dec->base.level) {
1190 case 30:
1191 num_dpb_buffer = 8100 / fs_in_mb;
1192 break;
1193 case 31:
1194 num_dpb_buffer = 18000 / fs_in_mb;
1195 break;
1196 case 32:
1197 num_dpb_buffer = 20480 / fs_in_mb;
1198 break;
1199 case 41:
1200 num_dpb_buffer = 32768 / fs_in_mb;
1201 break;
1202 case 42:
1203 num_dpb_buffer = 34816 / fs_in_mb;
1204 break;
1205 case 50:
1206 num_dpb_buffer = 110400 / fs_in_mb;
1207 break;
1208 case 51:
1209 num_dpb_buffer = 184320 / fs_in_mb;
1210 break;
1211 default:
1212 num_dpb_buffer = 184320 / fs_in_mb;
1213 break;
1214 }
1215 num_dpb_buffer++;
1216 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1217 dpb_size = image_size * max_references;
1218 break;
1219 }
1220
1221 case PIPE_VIDEO_FORMAT_HEVC:
1222 if (dec->base.width * dec->base.height >= 4096*2000)
1223 max_references = MAX2(max_references, 8);
1224 else
1225 max_references = MAX2(max_references, 17);
1226
1227 width = align (width, 16);
1228 height = align (height, 16);
1229 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1230 dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
1231 else
1232 dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
1233 break;
1234
1235 case PIPE_VIDEO_FORMAT_VC1:
1236 // the firmware seems to allways assume a minimum of ref frames
1237 max_references = MAX2(NUM_VC1_REFS, max_references);
1238
1239 // reference picture buffer
1240 dpb_size = image_size * max_references;
1241
1242 // CONTEXT_BUFFER
1243 dpb_size += width_in_mb * height_in_mb * 128;
1244
1245 // IT surface buffer
1246 dpb_size += width_in_mb * 64;
1247
1248 // DB surface buffer
1249 dpb_size += width_in_mb * 128;
1250
1251 // BP
1252 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
1253 break;
1254
1255 case PIPE_VIDEO_FORMAT_MPEG12:
1256 // reference picture buffer, must be big enough for all frames
1257 dpb_size = image_size * NUM_MPEG2_REFS;
1258 break;
1259
1260 case PIPE_VIDEO_FORMAT_MPEG4:
1261 // reference picture buffer
1262 dpb_size = image_size * max_references;
1263
1264 // CM
1265 dpb_size += width_in_mb * height_in_mb * 64;
1266
1267 // IT surface buffer
1268 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
1269
1270 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
1271 break;
1272
1273 case PIPE_VIDEO_FORMAT_VP9:
1274 max_references = MAX2(max_references, 9);
1275
1276 dpb_size = (4096 * 3000 * 3 / 2) * max_references;
1277 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1278 dpb_size *= (3 / 2);
1279 break;
1280
1281 default:
1282 // something is missing here
1283 assert(0);
1284
1285 // at least use a sane default value
1286 dpb_size = 32 * 1024 * 1024;
1287 break;
1288 }
1289 return dpb_size;
1290 }
1291
1292 /**
1293 * destroy this video decoder
1294 */
1295 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
1296 {
1297 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1298 unsigned i;
1299
1300 assert(decoder);
1301
1302 map_msg_fb_it_probs_buf(dec);
1303 rvcn_dec_message_destroy(dec);
1304 send_msg_buf(dec);
1305
1306 flush(dec, 0);
1307
1308 dec->ws->cs_destroy(dec->cs);
1309
1310 for (i = 0; i < NUM_BUFFERS; ++i) {
1311 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1312 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1313 }
1314
1315 si_vid_destroy_buffer(&dec->dpb);
1316 si_vid_destroy_buffer(&dec->ctx);
1317 si_vid_destroy_buffer(&dec->sessionctx);
1318
1319 FREE(dec);
1320 }
1321
1322 /**
1323 * start decoding of a new frame
1324 */
1325 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
1326 struct pipe_video_buffer *target,
1327 struct pipe_picture_desc *picture)
1328 {
1329 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1330 uintptr_t frame;
1331
1332 assert(decoder);
1333
1334 frame = ++dec->frame_number;
1335 if (dec->stream_type != RDECODE_CODEC_VP9)
1336 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1337 &radeon_dec_destroy_associated_data);
1338
1339 dec->bs_size = 0;
1340 dec->bs_ptr = dec->ws->buffer_map(
1341 dec->bs_buffers[dec->cur_buffer].res->buf,
1342 dec->cs, PIPE_TRANSFER_WRITE);
1343 }
1344
1345 /**
1346 * decode a macroblock
1347 */
1348 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
1349 struct pipe_video_buffer *target,
1350 struct pipe_picture_desc *picture,
1351 const struct pipe_macroblock *macroblocks,
1352 unsigned num_macroblocks)
1353 {
1354 /* not supported (yet) */
1355 assert(0);
1356 }
1357
1358 /**
1359 * decode a bitstream
1360 */
1361 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
1362 struct pipe_video_buffer *target,
1363 struct pipe_picture_desc *picture,
1364 unsigned num_buffers,
1365 const void * const *buffers,
1366 const unsigned *sizes)
1367 {
1368 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1369 unsigned i;
1370
1371 assert(decoder);
1372
1373 if (!dec->bs_ptr)
1374 return;
1375
1376 for (i = 0; i < num_buffers; ++i) {
1377 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1378 unsigned new_size = dec->bs_size + sizes[i];
1379
1380 if (new_size > buf->res->buf->size) {
1381 dec->ws->buffer_unmap(buf->res->buf);
1382 if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1383 RVID_ERR("Can't resize bitstream buffer!");
1384 return;
1385 }
1386
1387 dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1388 PIPE_TRANSFER_WRITE);
1389 if (!dec->bs_ptr)
1390 return;
1391
1392 dec->bs_ptr += dec->bs_size;
1393 }
1394
1395 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1396 dec->bs_size += sizes[i];
1397 dec->bs_ptr += sizes[i];
1398 }
1399 }
1400
1401 /**
1402 * end decoding of the current frame
1403 */
1404 static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
1405 struct pipe_video_buffer *target,
1406 struct pipe_picture_desc *picture)
1407 {
1408 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1409 struct pb_buffer *dt;
1410 struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
1411
1412 assert(decoder);
1413
1414 if (!dec->bs_ptr)
1415 return;
1416
1417 msg_fb_it_probs_buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1418 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1419
1420 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
1421 dec->ws->buffer_unmap(bs_buf->res->buf);
1422
1423 map_msg_fb_it_probs_buf(dec);
1424 dt = rvcn_dec_message_decode(dec, target, picture);
1425 rvcn_dec_message_feedback(dec);
1426 send_msg_buf(dec);
1427
1428 send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1429 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1430 if (dec->ctx.res)
1431 send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1432 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1433 send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1434 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1435 send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
1436 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1437 send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf,
1438 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1439 if (have_it(dec))
1440 send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
1441 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1442 else if (have_probs(dec))
1443 send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, msg_fb_it_probs_buf->res->buf,
1444 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1445 set_reg(dec, RDECODE_ENGINE_CNTL, 1);
1446
1447 flush(dec, PIPE_FLUSH_ASYNC);
1448 next_buffer(dec);
1449 }
1450
1451 /**
1452 * flush any outstanding command buffers to the hardware
1453 */
1454 static void radeon_dec_flush(struct pipe_video_codec *decoder)
1455 {
1456 }
1457
1458 /**
1459 * create and HW decoder
1460 */
1461 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
1462 const struct pipe_video_codec *templ)
1463 {
1464 struct si_context *sctx = (struct si_context*)context;
1465 struct radeon_winsys *ws = sctx->ws;
1466 unsigned width = templ->width, height = templ->height;
1467 unsigned dpb_size, bs_buf_size, stream_type = 0;
1468 struct radeon_decoder *dec;
1469 int r, i;
1470
1471 switch(u_reduce_video_profile(templ->profile)) {
1472 case PIPE_VIDEO_FORMAT_MPEG12:
1473 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1474 return vl_create_mpeg12_decoder(context, templ);
1475 stream_type = RDECODE_CODEC_MPEG2_VLD;
1476 break;
1477 case PIPE_VIDEO_FORMAT_MPEG4:
1478 width = align(width, VL_MACROBLOCK_WIDTH);
1479 height = align(height, VL_MACROBLOCK_HEIGHT);
1480 stream_type = RDECODE_CODEC_MPEG4;
1481 break;
1482 case PIPE_VIDEO_FORMAT_VC1:
1483 stream_type = RDECODE_CODEC_VC1;
1484 break;
1485 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1486 width = align(width, VL_MACROBLOCK_WIDTH);
1487 height = align(height, VL_MACROBLOCK_HEIGHT);
1488 stream_type = RDECODE_CODEC_H264_PERF;
1489 break;
1490 case PIPE_VIDEO_FORMAT_HEVC:
1491 stream_type = RDECODE_CODEC_H265;
1492 break;
1493 case PIPE_VIDEO_FORMAT_VP9:
1494 stream_type = RDECODE_CODEC_VP9;
1495 break;
1496 default:
1497 assert(0);
1498 break;
1499 }
1500
1501 dec = CALLOC_STRUCT(radeon_decoder);
1502
1503 if (!dec)
1504 return NULL;
1505
1506 dec->base = *templ;
1507 dec->base.context = context;
1508 dec->base.width = width;
1509 dec->base.height = height;
1510
1511 dec->base.destroy = radeon_dec_destroy;
1512 dec->base.begin_frame = radeon_dec_begin_frame;
1513 dec->base.decode_macroblock = radeon_dec_decode_macroblock;
1514 dec->base.decode_bitstream = radeon_dec_decode_bitstream;
1515 dec->base.end_frame = radeon_dec_end_frame;
1516 dec->base.flush = radeon_dec_flush;
1517
1518 dec->stream_type = stream_type;
1519 dec->stream_handle = si_vid_alloc_stream_handle();
1520 dec->screen = context->screen;
1521 dec->ws = ws;
1522 dec->cs = ws->cs_create(sctx->ctx, RING_VCN_DEC, NULL, NULL);
1523 if (!dec->cs) {
1524 RVID_ERR("Can't get command submission context.\n");
1525 goto error;
1526 }
1527
1528 for (i = 0; i < 16; i++)
1529 dec->render_pic_list[i] = NULL;
1530 bs_buf_size = width * height * (512 / (16 * 16));
1531 for (i = 0; i < NUM_BUFFERS; ++i) {
1532 unsigned msg_fb_it_probs_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1533 if (have_it(dec))
1534 msg_fb_it_probs_size += IT_SCALING_TABLE_SIZE;
1535 else if (have_probs(dec))
1536 msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
1537 /* use vram to improve performance, workaround an unknown bug */
1538 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i],
1539 msg_fb_it_probs_size, PIPE_USAGE_DEFAULT)) {
1540 RVID_ERR("Can't allocated message buffers.\n");
1541 goto error;
1542 }
1543
1544 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
1545 bs_buf_size, PIPE_USAGE_STAGING)) {
1546 RVID_ERR("Can't allocated bitstream buffers.\n");
1547 goto error;
1548 }
1549
1550 si_vid_clear_buffer(context, &dec->msg_fb_it_probs_buffers[i]);
1551 si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1552
1553 if (have_probs(dec)) {
1554 struct rvid_buffer* buf;
1555 void *ptr;
1556
1557 buf = &dec->msg_fb_it_probs_buffers[i];
1558 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
1559 ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1560 fill_probs_table(ptr);
1561 dec->ws->buffer_unmap(buf->res->buf);
1562 }
1563 }
1564
1565 dpb_size = calc_dpb_size(dec);
1566
1567 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1568 RVID_ERR("Can't allocated dpb.\n");
1569 goto error;
1570 }
1571
1572 si_vid_clear_buffer(context, &dec->dpb);
1573
1574 if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
1575 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1576 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1577 RVID_ERR("Can't allocated context buffer.\n");
1578 goto error;
1579 }
1580 si_vid_clear_buffer(context, &dec->ctx);
1581 }
1582
1583 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
1584 RDECODE_SESSION_CONTEXT_SIZE,
1585 PIPE_USAGE_DEFAULT)) {
1586 RVID_ERR("Can't allocated session ctx.\n");
1587 goto error;
1588 }
1589 si_vid_clear_buffer(context, &dec->sessionctx);
1590
1591 map_msg_fb_it_probs_buf(dec);
1592 rvcn_dec_message_create(dec);
1593 send_msg_buf(dec);
1594 r = flush(dec, 0);
1595 if (r)
1596 goto error;
1597
1598 next_buffer(dec);
1599
1600 return &dec->base;
1601
1602 error:
1603 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1604
1605 for (i = 0; i < NUM_BUFFERS; ++i) {
1606 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1607 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1608 }
1609
1610 si_vid_destroy_buffer(&dec->dpb);
1611 si_vid_destroy_buffer(&dec->ctx);
1612 si_vid_destroy_buffer(&dec->sessionctx);
1613
1614 FREE(dec);
1615
1616 return NULL;
1617 }