src/gallium/drivers/radeon/radeon_vcn_dec.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <assert.h>
  29 #include <stdio.h>
  30
  31 #include "pipe/p_video_codec.h"
  32
  33 #include "util/u_memory.h"
  34 #include "util/u_video.h"
  35
  36 #include "vl/vl_mpeg12_decoder.h"
  37
  38 #include "r600_pipe_common.h"
  39 #include "radeon_video.h"
  40 #include "radeon_vcn_dec.h"
  41
  42 #define FB_BUFFER_OFFSET                0x1000
  43 #define FB_BUFFER_SIZE                  2048
  44 #define IT_SCALING_TABLE_SIZE           992
  45 #define RDECODE_SESSION_CONTEXT_SIZE    (128 * 1024)
  46
  47 #define RDECODE_GPCOM_VCPU_CMD          0x2070c
  48 #define RDECODE_GPCOM_VCPU_DATA0        0x20710
  49 #define RDECODE_GPCOM_VCPU_DATA1        0x20714
  50 #define RDECODE_ENGINE_CNTL             0x20718
  51
  52 #define NUM_BUFFERS                     4
  53 #define NUM_MPEG2_REFS                  6
  54 #define NUM_H264_REFS                   17
  55 #define NUM_VC1_REFS                    5
  56
  57 struct radeon_decoder {
  58         struct pipe_video_codec         base;
  59
  60         unsigned                        stream_handle;
  61         unsigned                        stream_type;
  62         unsigned                        frame_number;
  63
  64         struct pipe_screen              *screen;
  65         struct radeon_winsys            *ws;
  66         struct radeon_winsys_cs         *cs;
  67
  68         void                            *msg;
  69         uint32_t                        *fb;
  70         uint8_t                         *it;
  71         void                            *bs_ptr;
  72
  73         struct rvid_buffer              msg_fb_it_buffers[NUM_BUFFERS];
  74         struct rvid_buffer              bs_buffers[NUM_BUFFERS];
  75         struct rvid_buffer              dpb;
  76         struct rvid_buffer              ctx;
  77         struct rvid_buffer              sessionctx;
  78
  79         unsigned                        bs_size;
  80         unsigned                        cur_buffer;
  81 };
  82
  83 static void radeon_dec_destroy_associated_data(void *data)
  84 {
  85         /* NOOP, since we only use an intptr */
  86 }
  87
  88 static void rvcn_dec_message_create(struct radeon_decoder *dec)
  89 {
  90         rvcn_dec_message_header_t *header = dec->msg;
  91         rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
  92         unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
  93
  94         memset(dec->msg, 0, sizes);
  95         header->header_size = sizeof(rvcn_dec_message_header_t);
  96         header->total_size = sizes;
  97         header->num_buffers = 1;
  98         header->msg_type = RDECODE_MSG_CREATE;
  99         header->stream_handle = dec->stream_handle;
 100         header->status_report_feedback_number = 0;
 101
 102         header->index[0].message_id = RDECODE_MESSAGE_CREATE;
 103         header->index[0].offset = sizeof(rvcn_dec_message_header_t);
 104         header->index[0].size = sizeof(rvcn_dec_message_create_t);
 105         header->index[0].filled = 0;
 106
 107         create->stream_type = dec->stream_type;
 108         create->session_flags = 0;
 109         create->width_in_samples = dec->base.width;
 110         create->height_in_samples = dec->base.height;
 111 }
 112
 113 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec)
 114 {
 115         /* TODO */
 116         return NULL;
 117 }
 118
 119 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
 120 {
 121         /* TODO */
 122 }
 123
 124 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
 125 {
 126         /* TODO */
 127 }
 128
 129 /* flush IB to the hardware */
 130 static int flush(struct radeon_decoder *dec, unsigned flags)
 131 {
 132         return dec->ws->cs_flush(dec->cs, flags, NULL);
 133 }
 134
 135 /* add a new set register command to the IB */
 136 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
 137 {
 138         radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
 139         radeon_emit(dec->cs, val);
 140 }
 141
 142 /* send a command to the VCPU through the GPCOM registers */
 143 static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
 144                      struct pb_buffer* buf, uint32_t off,
 145                      enum radeon_bo_usage usage, enum radeon_bo_domain domain)
 146 {
 147         uint64_t addr;
 148
 149         dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
 150                            domain, RADEON_PRIO_UVD);
 151         addr = dec->ws->buffer_get_virtual_address(buf);
 152         addr = addr + off;
 153
 154         set_reg(dec, RDECODE_GPCOM_VCPU_DATA0, addr);
 155         set_reg(dec, RDECODE_GPCOM_VCPU_DATA1, addr >> 32);
 156         set_reg(dec, RDECODE_GPCOM_VCPU_CMD, cmd << 1);
 157 }
 158
 159 /* do the codec needs an IT buffer ?*/
 160 static bool have_it(struct radeon_decoder *dec)
 161 {
 162         return dec->stream_type == RDECODE_CODEC_H264_PERF ||
 163                 dec->stream_type == RDECODE_CODEC_H265;
 164 }
 165
 166 /* map the next available message/feedback/itscaling buffer */
 167 static void map_msg_fb_it_buf(struct radeon_decoder *dec)
 168 {
 169         struct rvid_buffer* buf;
 170         uint8_t *ptr;
 171
 172         /* grab the current message/feedback buffer */
 173         buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
 174
 175         /* and map it for CPU access */
 176         ptr = dec->ws->buffer_map(buf->res->buf, dec->cs, PIPE_TRANSFER_WRITE);
 177
 178         /* calc buffer offsets */
 179         dec->msg = ptr;
 180
 181         dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
 182         if (have_it(dec))
 183                 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
 184 }
 185
 186 /* unmap and send a message command to the VCPU */
 187 static void send_msg_buf(struct radeon_decoder *dec)
 188 {
 189         struct rvid_buffer* buf;
 190
 191         /* ignore the request if message/feedback buffer isn't mapped */
 192         if (!dec->msg || !dec->fb)
 193                 return;
 194
 195         /* grab the current message buffer */
 196         buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
 197
 198         /* unmap the buffer */
 199         dec->ws->buffer_unmap(buf->res->buf);
 200         dec->msg = NULL;
 201         dec->fb = NULL;
 202         dec->it = NULL;
 203
 204         if (dec->sessionctx.res)
 205                 send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
 206                          dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
 207                          RADEON_DOMAIN_VRAM);
 208
 209         /* and send it to the hardware */
 210         send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
 211                  RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
 212 }
 213
 214 /* cycle to the next set of buffers */
 215 static void next_buffer(struct radeon_decoder *dec)
 216 {
 217         ++dec->cur_buffer;
 218         dec->cur_buffer %= NUM_BUFFERS;
 219 }
 220
 221 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
 222 {
 223         unsigned width_in_mb, height_in_mb, ctx_size;
 224         unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
 225         unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
 226
 227         unsigned max_references = dec->base.max_references + 1;
 228
 229         // picture width & height in 16 pixel units
 230         width_in_mb = width / VL_MACROBLOCK_WIDTH;
 231         height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
 232
 233         unsigned fs_in_mb = width_in_mb * height_in_mb;
 234         unsigned num_dpb_buffer;
 235         switch(dec->base.level) {
 236         case 30:
 237                 num_dpb_buffer = 8100 / fs_in_mb;
 238                 break;
 239         case 31:
 240                 num_dpb_buffer = 18000 / fs_in_mb;
 241                 break;
 242         case 32:
 243                 num_dpb_buffer = 20480 / fs_in_mb;
 244                 break;
 245         case 41:
 246                 num_dpb_buffer = 32768 / fs_in_mb;
 247                 break;
 248         case 42:
 249                 num_dpb_buffer = 34816 / fs_in_mb;
 250                 break;
 251         case 50:
 252                 num_dpb_buffer = 110400 / fs_in_mb;
 253                 break;
 254         case 51:
 255                 num_dpb_buffer = 184320 / fs_in_mb;
 256                 break;
 257         default:
 258                 num_dpb_buffer = 184320 / fs_in_mb;
 259                 break;
 260         }
 261         num_dpb_buffer++;
 262         max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
 263         ctx_size = max_references * align(width_in_mb * height_in_mb  * 192, 256);
 264
 265         return ctx_size;
 266 }
 267
 268 /* calculate size of reference picture buffer */
 269 static unsigned calc_dpb_size(struct radeon_decoder *dec)
 270 {
 271         unsigned width_in_mb, height_in_mb, image_size, dpb_size;
 272
 273         // always align them to MB size for dpb calculation
 274         unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
 275         unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
 276
 277         // always one more for currently decoded picture
 278         unsigned max_references = dec->base.max_references + 1;
 279
 280         // aligned size of a single frame
 281         image_size = align(width, 32) * height;
 282         image_size += image_size / 2;
 283         image_size = align(image_size, 1024);
 284
 285         // picture width & height in 16 pixel units
 286         width_in_mb = width / VL_MACROBLOCK_WIDTH;
 287         height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
 288
 289         switch (u_reduce_video_profile(dec->base.profile)) {
 290         case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
 291                 unsigned fs_in_mb = width_in_mb * height_in_mb;
 292                 unsigned num_dpb_buffer;
 293
 294                 switch(dec->base.level) {
 295                 case 30:
 296                         num_dpb_buffer = 8100 / fs_in_mb;
 297                         break;
 298                 case 31:
 299                         num_dpb_buffer = 18000 / fs_in_mb;
 300                         break;
 301                 case 32:
 302                         num_dpb_buffer = 20480 / fs_in_mb;
 303                         break;
 304                 case 41:
 305                         num_dpb_buffer = 32768 / fs_in_mb;
 306                         break;
 307                 case 42:
 308                         num_dpb_buffer = 34816 / fs_in_mb;
 309                         break;
 310                 case 50:
 311                         num_dpb_buffer = 110400 / fs_in_mb;
 312                         break;
 313                 case 51:
 314                         num_dpb_buffer = 184320 / fs_in_mb;
 315                         break;
 316                 default:
 317                         num_dpb_buffer = 184320 / fs_in_mb;
 318                         break;
 319                 }
 320                 num_dpb_buffer++;
 321                 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
 322                 dpb_size = image_size * max_references;
 323                 break;
 324         }
 325
 326         case PIPE_VIDEO_FORMAT_HEVC:
 327                 if (dec->base.width * dec->base.height >= 4096*2000)
 328                         max_references = MAX2(max_references, 8);
 329                 else
 330                         max_references = MAX2(max_references, 17);
 331
 332                 width = align (width, 16);
 333                 height = align (height, 16);
 334                 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 335                         dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
 336                 else
 337                         dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
 338                 break;
 339
 340         case PIPE_VIDEO_FORMAT_VC1:
 341                 // the firmware seems to allways assume a minimum of ref frames
 342                 max_references = MAX2(NUM_VC1_REFS, max_references);
 343
 344                 // reference picture buffer
 345                 dpb_size = image_size * max_references;
 346
 347                 // CONTEXT_BUFFER
 348                 dpb_size += width_in_mb * height_in_mb * 128;
 349
 350                 // IT surface buffer
 351                 dpb_size += width_in_mb * 64;
 352
 353                 // DB surface buffer
 354                 dpb_size += width_in_mb * 128;
 355
 356                 // BP
 357                 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
 358                 break;
 359
 360         case PIPE_VIDEO_FORMAT_MPEG12:
 361                 // reference picture buffer, must be big enough for all frames
 362                 dpb_size = image_size * NUM_MPEG2_REFS;
 363                 break;
 364
 365         case PIPE_VIDEO_FORMAT_MPEG4:
 366                 // reference picture buffer
 367                 dpb_size = image_size * max_references;
 368
 369                 // CM
 370                 dpb_size += width_in_mb * height_in_mb * 64;
 371
 372                 // IT surface buffer
 373                 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
 374
 375                 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
 376                 break;
 377
 378         default:
 379                 // something is missing here
 380                 assert(0);
 381
 382                 // at least use a sane default value
 383                 dpb_size = 32 * 1024 * 1024;
 384                 break;
 385         }
 386         return dpb_size;
 387 }
 388
 389 /**
 390  * destroy this video decoder
 391  */
 392 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
 393 {
 394         struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
 395         unsigned i;
 396
 397         assert(decoder);
 398
 399         map_msg_fb_it_buf(dec);
 400         rvcn_dec_message_destroy(dec);
 401         send_msg_buf(dec);
 402
 403         flush(dec, 0);
 404
 405         dec->ws->cs_destroy(dec->cs);
 406
 407         for (i = 0; i < NUM_BUFFERS; ++i) {
 408                 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
 409                 rvid_destroy_buffer(&dec->bs_buffers[i]);
 410         }
 411
 412         rvid_destroy_buffer(&dec->dpb);
 413         rvid_destroy_buffer(&dec->ctx);
 414         rvid_destroy_buffer(&dec->sessionctx);
 415
 416         FREE(dec);
 417 }
 418
 419 /**
 420  * start decoding of a new frame
 421  */
 422 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
 423                              struct pipe_video_buffer *target,
 424                              struct pipe_picture_desc *picture)
 425 {
 426         struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
 427         uintptr_t frame;
 428
 429         assert(decoder);
 430
 431         frame = ++dec->frame_number;
 432         vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
 433                                             &radeon_dec_destroy_associated_data);
 434
 435         dec->bs_size = 0;
 436         dec->bs_ptr = dec->ws->buffer_map(
 437                 dec->bs_buffers[dec->cur_buffer].res->buf,
 438                 dec->cs, PIPE_TRANSFER_WRITE);
 439 }
 440
 441 /**
 442  * decode a macroblock
 443  */
 444 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
 445                                    struct pipe_video_buffer *target,
 446                                    struct pipe_picture_desc *picture,
 447                                    const struct pipe_macroblock *macroblocks,
 448                                    unsigned num_macroblocks)
 449 {
 450         /* not supported (yet) */
 451         assert(0);
 452 }
 453
 454 /**
 455  * decode a bitstream
 456  */
 457 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
 458                                   struct pipe_video_buffer *target,
 459                                   struct pipe_picture_desc *picture,
 460                                   unsigned num_buffers,
 461                                   const void * const *buffers,
 462                                   const unsigned *sizes)
 463 {
 464         struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
 465         unsigned i;
 466
 467         assert(decoder);
 468
 469         if (!dec->bs_ptr)
 470                 return;
 471
 472         for (i = 0; i < num_buffers; ++i) {
 473                 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
 474                 unsigned new_size = dec->bs_size + sizes[i];
 475
 476                 if (new_size > buf->res->buf->size) {
 477                         dec->ws->buffer_unmap(buf->res->buf);
 478                         if (!rvid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
 479                                 RVID_ERR("Can't resize bitstream buffer!");
 480                                 return;
 481                         }
 482
 483                         dec->bs_ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
 484                                                           PIPE_TRANSFER_WRITE);
 485                         if (!dec->bs_ptr)
 486                                 return;
 487
 488                         dec->bs_ptr += dec->bs_size;
 489                 }
 490
 491                 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
 492                 dec->bs_size += sizes[i];
 493                 dec->bs_ptr += sizes[i];
 494         }
 495 }
 496
 497 /**
 498  * end decoding of the current frame
 499  */
 500 static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
 501                            struct pipe_video_buffer *target,
 502                            struct pipe_picture_desc *picture)
 503 {
 504         struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
 505         struct pb_buffer *dt;
 506         struct rvid_buffer *msg_fb_it_buf, *bs_buf;
 507
 508         assert(decoder);
 509
 510         if (!dec->bs_ptr)
 511                 return;
 512
 513         msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
 514         bs_buf = &dec->bs_buffers[dec->cur_buffer];
 515
 516         memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
 517         dec->ws->buffer_unmap(bs_buf->res->buf);
 518
 519         map_msg_fb_it_buf(dec);
 520         dt = rvcn_dec_message_decode(dec);
 521         rvcn_dec_message_feedback(dec);
 522         send_msg_buf(dec);
 523
 524         send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
 525                  RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
 526         if (dec->ctx.res)
 527                 send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
 528                         RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
 529         send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
 530                  0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
 531         send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
 532                  RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
 533         send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf,
 534                  FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
 535         if (have_it(dec))
 536                 send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
 537                          FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
 538         set_reg(dec, RDECODE_ENGINE_CNTL, 1);
 539
 540         flush(dec, RADEON_FLUSH_ASYNC);
 541         next_buffer(dec);
 542 }
 543
 544 /**
 545  * flush any outstanding command buffers to the hardware
 546  */
 547 static void radeon_dec_flush(struct pipe_video_codec *decoder)
 548 {
 549 }
 550
 551 /**
 552  * create and HW decoder
 553  */
 554 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
 555                                              const struct pipe_video_codec *templ)
 556 {
 557         struct radeon_winsys* ws = ((struct r600_common_context *)context)->ws;
 558         struct r600_common_context *rctx = (struct r600_common_context*)context;
 559         unsigned width = templ->width, height = templ->height;
 560         unsigned dpb_size, bs_buf_size, stream_type = 0;
 561         struct radeon_decoder *dec;
 562         int r, i;
 563
 564         switch(u_reduce_video_profile(templ->profile)) {
 565         case PIPE_VIDEO_FORMAT_MPEG12:
 566                 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
 567                         return vl_create_mpeg12_decoder(context, templ);
 568                 stream_type = RDECODE_CODEC_MPEG2_VLD;
 569                 break;
 570         case PIPE_VIDEO_FORMAT_MPEG4:
 571                 width = align(width, VL_MACROBLOCK_WIDTH);
 572                 height = align(height, VL_MACROBLOCK_HEIGHT);
 573                 stream_type = RDECODE_CODEC_MPEG4;
 574                 break;
 575         case PIPE_VIDEO_FORMAT_VC1:
 576                 stream_type = RDECODE_CODEC_VC1;
 577                 break;
 578         case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 579                 width = align(width, VL_MACROBLOCK_WIDTH);
 580                 height = align(height, VL_MACROBLOCK_HEIGHT);
 581                 stream_type = RDECODE_CODEC_H264_PERF;
 582                 break;
 583         case PIPE_VIDEO_FORMAT_HEVC:
 584                 stream_type = RDECODE_CODEC_H265;
 585                 break;
 586         default:
 587                 assert(0);
 588                 break;
 589         }
 590
 591         dec = CALLOC_STRUCT(radeon_decoder);
 592
 593         if (!dec)
 594                 return NULL;
 595
 596         dec->base = *templ;
 597         dec->base.context = context;
 598         dec->base.width = width;
 599         dec->base.height = height;
 600
 601         dec->base.destroy = radeon_dec_destroy;
 602         dec->base.begin_frame = radeon_dec_begin_frame;
 603         dec->base.decode_macroblock = radeon_dec_decode_macroblock;
 604         dec->base.decode_bitstream = radeon_dec_decode_bitstream;
 605         dec->base.end_frame = radeon_dec_end_frame;
 606         dec->base.flush = radeon_dec_flush;
 607
 608         dec->stream_type = stream_type;
 609         dec->stream_handle = rvid_alloc_stream_handle();
 610         dec->screen = context->screen;
 611         dec->ws = ws;
 612         dec->cs = ws->cs_create(rctx->ctx, RING_VCN_DEC, NULL, NULL);
 613         if (!dec->cs) {
 614                 RVID_ERR("Can't get command submission context.\n");
 615                 goto error;
 616         }
 617
 618         bs_buf_size = width * height * (512 / (16 * 16));
 619         for (i = 0; i < NUM_BUFFERS; ++i) {
 620                 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
 621                 if (have_it(dec))
 622                         msg_fb_it_size += IT_SCALING_TABLE_SIZE;
 623                 if (!rvid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i],
 624                                         msg_fb_it_size, PIPE_USAGE_STAGING)) {
 625                         RVID_ERR("Can't allocated message buffers.\n");
 626                         goto error;
 627                 }
 628
 629                 if (!rvid_create_buffer(dec->screen, &dec->bs_buffers[i],
 630                                         bs_buf_size, PIPE_USAGE_STAGING)) {
 631                         RVID_ERR("Can't allocated bitstream buffers.\n");
 632                         goto error;
 633                 }
 634
 635                 rvid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
 636                 rvid_clear_buffer(context, &dec->bs_buffers[i]);
 637         }
 638
 639         dpb_size = calc_dpb_size(dec);
 640
 641         if (!rvid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
 642                 RVID_ERR("Can't allocated dpb.\n");
 643                 goto error;
 644         }
 645
 646         rvid_clear_buffer(context, &dec->dpb);
 647
 648         if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
 649                 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
 650                 if (!rvid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
 651                         RVID_ERR("Can't allocated context buffer.\n");
 652                         goto error;
 653                 }
 654                 rvid_clear_buffer(context, &dec->ctx);
 655         }
 656
 657         if (!rvid_create_buffer(dec->screen, &dec->sessionctx,
 658                                 RDECODE_SESSION_CONTEXT_SIZE,
 659                                 PIPE_USAGE_DEFAULT)) {
 660                 RVID_ERR("Can't allocated session ctx.\n");
 661                 goto error;
 662         }
 663         rvid_clear_buffer(context, &dec->sessionctx);
 664
 665         map_msg_fb_it_buf(dec);
 666         rvcn_dec_message_create(dec);
 667         send_msg_buf(dec);
 668         r = flush(dec, 0);
 669         if (r)
 670                 goto error;
 671
 672         next_buffer(dec);
 673
 674         return &dec->base;
 675
 676 error:
 677         if (dec->cs) dec->ws->cs_destroy(dec->cs);
 678
 679         for (i = 0; i < NUM_BUFFERS; ++i) {
 680                 rvid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
 681                 rvid_destroy_buffer(&dec->bs_buffers[i]);
 682         }
 683
 684         rvid_destroy_buffer(&dec->dpb);
 685         rvid_destroy_buffer(&dec->ctx);
 686         rvid_destroy_buffer(&dec->sessionctx);
 687
 688         FREE(dec);
 689
 690         return NULL;
 691 }