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radeon/vcn: add Arcturus decode support
[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_dec.c
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <assert.h>
29 #include <stdio.h>
30
31 #include "pipe/p_video_codec.h"
32
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35
36 #include "vl/vl_mpeg12_decoder.h"
37
38 #include "radeonsi/si_pipe.h"
39 #include "radeon_video.h"
40 #include "radeon_vcn_dec.h"
41 #include "vl/vl_probs_table.h"
42
43 #define FB_BUFFER_OFFSET 0x1000
44 #define FB_BUFFER_SIZE 2048
45 #define IT_SCALING_TABLE_SIZE 992
46 #define VP9_PROBS_TABLE_SIZE (RDECODE_VP9_PROBS_DATA_SIZE + 256)
47 #define RDECODE_SESSION_CONTEXT_SIZE (128 * 1024)
48
49 #define RDECODE_VCN1_GPCOM_VCPU_CMD 0x2070c
50 #define RDECODE_VCN1_GPCOM_VCPU_DATA0 0x20710
51 #define RDECODE_VCN1_GPCOM_VCPU_DATA1 0x20714
52 #define RDECODE_VCN1_ENGINE_CNTL 0x20718
53
54 #define RDECODE_VCN2_GPCOM_VCPU_CMD (0x503 << 2)
55 #define RDECODE_VCN2_GPCOM_VCPU_DATA0 (0x504 << 2)
56 #define RDECODE_VCN2_GPCOM_VCPU_DATA1 (0x505 << 2)
57 #define RDECODE_VCN2_ENGINE_CNTL (0x506 << 2)
58
59 #define RDECODE_VCN2_5_GPCOM_VCPU_CMD 0x3c
60 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA0 0x40
61 #define RDECODE_VCN2_5_GPCOM_VCPU_DATA1 0x44
62 #define RDECODE_VCN2_5_ENGINE_CNTL 0x9b4
63
64 #define NUM_MPEG2_REFS 6
65 #define NUM_H264_REFS 17
66 #define NUM_VC1_REFS 5
67 #define NUM_VP9_REFS 8
68
69 static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
70 struct pipe_h264_picture_desc *pic)
71 {
72 rvcn_dec_message_avc_t result;
73
74 memset(&result, 0, sizeof(result));
75 switch (pic->base.profile) {
76 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
77 case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
78 result.profile = RDECODE_H264_PROFILE_BASELINE;
79 break;
80
81 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
82 result.profile = RDECODE_H264_PROFILE_MAIN;
83 break;
84
85 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
86 result.profile = RDECODE_H264_PROFILE_HIGH;
87 break;
88
89 default:
90 assert(0);
91 break;
92 }
93
94 result.level = dec->base.level;
95
96 result.sps_info_flags = 0;
97 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
98 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
99 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
100 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
101 result.sps_info_flags |= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT;
102
103 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
104 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
105 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
106 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
107 result.log2_max_pic_order_cnt_lsb_minus4 =
108 pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
109
110 switch (dec->base.chroma_format) {
111 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
112 break;
113 case PIPE_VIDEO_CHROMA_FORMAT_400:
114 result.chroma_format = 0;
115 break;
116 case PIPE_VIDEO_CHROMA_FORMAT_420:
117 result.chroma_format = 1;
118 break;
119 case PIPE_VIDEO_CHROMA_FORMAT_422:
120 result.chroma_format = 2;
121 break;
122 case PIPE_VIDEO_CHROMA_FORMAT_444:
123 result.chroma_format = 3;
124 break;
125 }
126
127 result.pps_info_flags = 0;
128 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
129 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
130 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
131 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
132 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
133 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
134 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
135 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
136
137 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
138 result.slice_group_map_type = pic->pps->slice_group_map_type;
139 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
140 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
141 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
142 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
143
144 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6*16);
145 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2*64);
146
147 memcpy(dec->it, result.scaling_list_4x4, 6*16);
148 memcpy((dec->it + 96), result.scaling_list_8x8, 2*64);
149
150 result.num_ref_frames = pic->num_ref_frames;
151
152 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
153 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
154
155 result.frame_num = pic->frame_num;
156 memcpy(result.frame_num_list, pic->frame_num_list, 4*16);
157 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
158 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
159 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2);
160
161 result.decoded_pic_idx = pic->frame_num;
162
163 return result;
164 }
165
166 static void radeon_dec_destroy_associated_data(void *data)
167 {
168 /* NOOP, since we only use an intptr */
169 }
170
171 static rvcn_dec_message_hevc_t get_h265_msg(struct radeon_decoder *dec,
172 struct pipe_video_buffer *target,
173 struct pipe_h265_picture_desc *pic)
174 {
175 rvcn_dec_message_hevc_t result;
176 unsigned i, j;
177
178 memset(&result, 0, sizeof(result));
179 result.sps_info_flags = 0;
180 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
181 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
182 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
183 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
184 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
185 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
186 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
187 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
188 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
189 if (((struct si_screen*)dec->screen)->info.family == CHIP_CARRIZO)
190 result.sps_info_flags |= 1 << 9;
191 if (pic->UseRefPicList == true)
192 result.sps_info_flags |= 1 << 10;
193
194 result.chroma_format = pic->pps->sps->chroma_format_idc;
195 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
196 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
197 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
198 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
199 result.log2_min_luma_coding_block_size_minus3 =
200 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
201 result.log2_diff_max_min_luma_coding_block_size =
202 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
203 result.log2_min_transform_block_size_minus2 =
204 pic->pps->sps->log2_min_transform_block_size_minus2;
205 result.log2_diff_max_min_transform_block_size =
206 pic->pps->sps->log2_diff_max_min_transform_block_size;
207 result.max_transform_hierarchy_depth_inter =
208 pic->pps->sps->max_transform_hierarchy_depth_inter;
209 result.max_transform_hierarchy_depth_intra =
210 pic->pps->sps->max_transform_hierarchy_depth_intra;
211 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
212 result.pcm_sample_bit_depth_chroma_minus1 =
213 pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
214 result.log2_min_pcm_luma_coding_block_size_minus3 =
215 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
216 result.log2_diff_max_min_pcm_luma_coding_block_size =
217 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
218 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
219
220 result.pps_info_flags = 0;
221 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
222 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
223 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
224 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
225 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
226 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
227 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
228 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
229 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
230 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
231 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
232 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
233 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
234 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
235 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
236 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
237 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
238 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
239 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
240 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
241
242 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
243 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
244 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
245 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
246 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
247 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
248 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
249 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
250 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
251 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
252 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
253 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
254 result.init_qp_minus26 = pic->pps->init_qp_minus26;
255
256 for (i = 0; i < 19; ++i)
257 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
258
259 for (i = 0; i < 21; ++i)
260 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
261
262 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
263 result.curr_poc = pic->CurrPicOrderCntVal;
264
265 for (i = 0 ; i < 16 ; i++) {
266 for (j = 0; (pic->ref[j] != NULL) && (j < 16) ; j++) {
267 if (dec->render_pic_list[i] == pic->ref[j])
268 break;
269 if (j == 15)
270 dec->render_pic_list[i] = NULL;
271 else if (pic->ref[j+1] == NULL)
272 dec->render_pic_list[i] = NULL;
273 }
274 }
275 for (i = 0 ; i < 16 ; i++) {
276 if (dec->render_pic_list[i] == NULL) {
277 dec->render_pic_list[i] = target;
278 result.curr_idx = i;
279 break;
280 }
281 }
282
283 vl_video_buffer_set_associated_data(target, &dec->base,
284 (void *)(uintptr_t)result.curr_idx,
285 &radeon_dec_destroy_associated_data);
286
287 for (i = 0; i < 16; ++i) {
288 struct pipe_video_buffer *ref = pic->ref[i];
289 uintptr_t ref_pic = 0;
290
291 result.poc_list[i] = pic->PicOrderCntVal[i];
292
293 if (ref)
294 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
295 else
296 ref_pic = 0x7F;
297 result.ref_pic_list[i] = ref_pic;
298 }
299
300 for (i = 0; i < 8; ++i) {
301 result.ref_pic_set_st_curr_before[i] = 0xFF;
302 result.ref_pic_set_st_curr_after[i] = 0xFF;
303 result.ref_pic_set_lt_curr[i] = 0xFF;
304 }
305
306 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
307 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
308
309 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
310 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
311
312 for (i = 0; i < pic->NumPocLtCurr; ++i)
313 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
314
315 for (i = 0; i < 6; ++i)
316 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
317
318 for (i = 0; i < 2; ++i)
319 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
320
321 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
322 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
323 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
324 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
325
326 for (i = 0 ; i < 2 ; i++) {
327 for (j = 0 ; j < 15 ; j++)
328 result.direct_reflist[i][j] = pic->RefPicList[i][j];
329 }
330
331 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
332 if (target->buffer_format == PIPE_FORMAT_P016) {
333 result.p010_mode = 1;
334 result.msb_mode = 1;
335 } else {
336 result.p010_mode = 0;
337 result.luma_10to8 = 5;
338 result.chroma_10to8 = 5;
339 result.hevc_reserved[0] = 4; /* sclr_luma10to8 */
340 result.hevc_reserved[1] = 4; /* sclr_chroma10to8 */
341 }
342 }
343
344 return result;
345 }
346
347 static void fill_probs_table(void *ptr)
348 {
349 rvcn_dec_vp9_probs_t *probs = (rvcn_dec_vp9_probs_t *)ptr;
350
351 memcpy(&probs->coef_probs[0], default_coef_probs_4x4, sizeof(default_coef_probs_4x4));
352 memcpy(&probs->coef_probs[1], default_coef_probs_8x8, sizeof(default_coef_probs_8x8));
353 memcpy(&probs->coef_probs[2], default_coef_probs_16x16, sizeof(default_coef_probs_16x16));
354 memcpy(&probs->coef_probs[3], default_coef_probs_32x32, sizeof(default_coef_probs_32x32));
355 memcpy(probs->y_mode_prob, default_if_y_probs, sizeof(default_if_y_probs));
356 memcpy(probs->uv_mode_prob, default_if_uv_probs, sizeof(default_if_uv_probs));
357 memcpy(probs->single_ref_prob, default_single_ref_p, sizeof(default_single_ref_p));
358 memcpy(probs->switchable_interp_prob, default_switchable_interp_prob, sizeof(default_switchable_interp_prob));
359 memcpy(probs->partition_prob, default_partition_probs, sizeof(default_partition_probs));
360 memcpy(probs->inter_mode_probs, default_inter_mode_probs, sizeof(default_inter_mode_probs));
361 memcpy(probs->mbskip_probs, default_skip_probs, sizeof(default_skip_probs));
362 memcpy(probs->intra_inter_prob, default_intra_inter_p, sizeof(default_intra_inter_p));
363 memcpy(probs->comp_inter_prob, default_comp_inter_p, sizeof(default_comp_inter_p));
364 memcpy(probs->comp_ref_prob, default_comp_ref_p, sizeof(default_comp_ref_p));
365 memcpy(probs->tx_probs_32x32, default_tx_probs_32x32, sizeof(default_tx_probs_32x32));
366 memcpy(probs->tx_probs_16x16, default_tx_probs_16x16, sizeof(default_tx_probs_16x16));
367 memcpy(probs->tx_probs_8x8, default_tx_probs_8x8, sizeof(default_tx_probs_8x8));
368 memcpy(probs->mv_joints, default_nmv_joints, sizeof(default_nmv_joints));
369 memcpy(&probs->mv_comps[0], default_nmv_components, sizeof(default_nmv_components));
370 memset(&probs->nmvc_mask, 0, sizeof(rvcn_dec_vp9_nmv_ctx_mask_t));
371 }
372
373 static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
374 struct pipe_video_buffer *target,
375 struct pipe_vp9_picture_desc *pic)
376 {
377 rvcn_dec_message_vp9_t result;
378 unsigned i;
379
380 memset(&result, 0, sizeof(result));
381
382 /* segment table */
383 rvcn_dec_vp9_probs_segment_t *prbs = (rvcn_dec_vp9_probs_segment_t *)(dec->probs);
384
385 if (pic->picture_parameter.pic_fields.segmentation_enabled) {
386 for (i = 0; i < 8; ++i) {
387 prbs->seg.feature_data[i] =
388 (pic->slice_parameter.seg_param[i].alt_quant & 0xffff) |
389 ((pic->slice_parameter.seg_param[i].alt_lf & 0xff) << 16) |
390 ((pic->slice_parameter.seg_param[i].segment_flags.segment_reference & 0xf) << 24);
391 prbs->seg.feature_mask[i] =
392 (pic->slice_parameter.seg_param[i].alt_quant_enabled << 0) |
393 (pic->slice_parameter.seg_param[i].alt_lf_enabled << 1) |
394 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_enabled << 2) |
395 (pic->slice_parameter.seg_param[i].segment_flags.segment_reference_skipped << 3);
396 }
397
398 for (i = 0; i < 7; ++i)
399 prbs->seg.tree_probs[i] = pic->picture_parameter.mb_segment_tree_probs[i];
400
401 for (i = 0; i < 3; ++i)
402 prbs->seg.pred_probs[i] = pic->picture_parameter.segment_pred_probs[i];
403
404 prbs->seg.abs_delta = 0;
405 } else
406 memset(&prbs->seg, 0, 256);
407
408 result.frame_header_flags =
409 (pic->picture_parameter.pic_fields.frame_type <<
410 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT) &
411 RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK;
412
413 result.frame_header_flags |=
414 (pic->picture_parameter.pic_fields.error_resilient_mode <<
415 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT) &
416 RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK;
417
418 result.frame_header_flags |=
419 (pic->picture_parameter.pic_fields.intra_only <<
420 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT) &
421 RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK;
422
423 result.frame_header_flags |=
424 (pic->picture_parameter.pic_fields.allow_high_precision_mv <<
425 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT) &
426 RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK;
427
428 result.frame_header_flags |=
429 (pic->picture_parameter.pic_fields.frame_parallel_decoding_mode <<
430 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT) &
431 RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK;
432
433 result.frame_header_flags |=
434 (pic->picture_parameter.pic_fields.refresh_frame_context <<
435 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT) &
436 RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK;
437
438 result.frame_header_flags |=
439 (pic->picture_parameter.pic_fields.segmentation_enabled <<
440 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT) &
441 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK;
442
443 result.frame_header_flags |=
444 (pic->picture_parameter.pic_fields.segmentation_update_map <<
445 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT) &
446 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK;
447
448 result.frame_header_flags |=
449 (pic->picture_parameter.pic_fields.segmentation_temporal_update <<
450 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT) &
451 RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK;
452
453 result.frame_header_flags |=
454 (pic->picture_parameter.mode_ref_delta_enabled <<
455 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT) &
456 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK;
457
458 result.frame_header_flags |=
459 (pic->picture_parameter.mode_ref_delta_update <<
460 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT) &
461 RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK;
462
463 result.frame_header_flags |= ((dec->show_frame &&
464 !pic->picture_parameter.pic_fields.error_resilient_mode)
465 << RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT) &
466 RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK;
467 dec->show_frame = pic->picture_parameter.pic_fields.show_frame;
468
469 result.interp_filter = pic->picture_parameter.pic_fields.mcomp_filter_type;
470
471 result.frame_context_idx = pic->picture_parameter.pic_fields.frame_context_idx;
472 result.reset_frame_context = pic->picture_parameter.pic_fields.reset_frame_context;
473
474 result.filter_level = pic->picture_parameter.filter_level;
475 result.sharpness_level = pic->picture_parameter.sharpness_level;
476
477 for (i = 0; i < 8; ++i)
478 memcpy(result.lf_adj_level[i], pic->slice_parameter.seg_param[i].filter_level, 4 * 2);
479
480 if (pic->picture_parameter.pic_fields.lossless_flag) {
481 result.base_qindex = 0;
482 result.y_dc_delta_q = 0;
483 result.uv_ac_delta_q = 0;
484 result.uv_dc_delta_q = 0;
485 } else {
486 result.base_qindex = pic->picture_parameter.base_qindex;
487 result.y_dc_delta_q = pic->picture_parameter.y_dc_delta_q;
488 result.uv_ac_delta_q = pic->picture_parameter.uv_ac_delta_q;
489 result.uv_dc_delta_q = pic->picture_parameter.uv_dc_delta_q;
490 }
491
492 result.log2_tile_cols = pic->picture_parameter.log2_tile_columns;
493 result.log2_tile_rows = pic->picture_parameter.log2_tile_rows;
494 result.chroma_format = 1;
495 result.bit_depth_luma_minus8 = result.bit_depth_chroma_minus8
496 = (pic->picture_parameter.bit_depth - 8);
497
498 result.vp9_frame_size = align(dec->bs_size, 128);
499 result.uncompressed_header_size = pic->picture_parameter.frame_header_length_in_bytes;
500 result.compressed_header_size = pic->picture_parameter.first_partition_size;
501
502 assert(dec->base.max_references + 1 <= 16);
503
504 for (i = 0 ; i < 16 ; ++i) {
505 if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
506 result.curr_pic_idx =
507 (uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
508 break;
509 } else if (!dec->render_pic_list[i]) {
510 dec->render_pic_list[i] = target;
511 result.curr_pic_idx = dec->ref_idx;
512 vl_video_buffer_set_associated_data(target, &dec->base,
513 (void *)(uintptr_t)dec->ref_idx++,
514 &radeon_dec_destroy_associated_data);
515 break;
516 }
517 }
518
519 for (i = 0 ; i < 8; i++) {
520 result.ref_frame_map[i] = (pic->ref[i]) ?
521 (uintptr_t)vl_video_buffer_get_associated_data(pic->ref[i], &dec->base) :
522 0x7f;
523 }
524
525 result.frame_refs[0] = result.ref_frame_map[pic->picture_parameter.pic_fields.last_ref_frame];
526 result.ref_frame_sign_bias[0] = pic->picture_parameter.pic_fields.last_ref_frame_sign_bias;
527 result.frame_refs[1] = result.ref_frame_map[pic->picture_parameter.pic_fields.golden_ref_frame];
528 result.ref_frame_sign_bias[1] = pic->picture_parameter.pic_fields.golden_ref_frame_sign_bias;
529 result.frame_refs[2] = result.ref_frame_map[pic->picture_parameter.pic_fields.alt_ref_frame];
530 result.ref_frame_sign_bias[2] = pic->picture_parameter.pic_fields.alt_ref_frame_sign_bias;
531
532 if (pic->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2) {
533 if (target->buffer_format == PIPE_FORMAT_P016) {
534 result.p010_mode = 1;
535 result.msb_mode = 1;
536 } else {
537 result.p010_mode = 0;
538 result.luma_10to8 = 1;
539 result.chroma_10to8 = 1;
540 }
541 }
542
543 return result;
544 }
545
546 static unsigned calc_ctx_size_h265_main(struct radeon_decoder *dec)
547 {
548 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
549 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
550
551 unsigned max_references = dec->base.max_references + 1;
552
553 if (dec->base.width * dec->base.height >= 4096*2000)
554 max_references = MAX2(max_references, 8);
555 else
556 max_references = MAX2(max_references, 17);
557
558 width = align (width, 16);
559 height = align (height, 16);
560 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
561 }
562
563 static unsigned calc_ctx_size_h265_main10(struct radeon_decoder *dec, struct pipe_h265_picture_desc *pic)
564 {
565 unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
566 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
567 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
568
569 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
570 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
571 unsigned coeff_10bit = (pic->pps->sps->bit_depth_luma_minus8 ||
572 pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
573
574 unsigned max_references = dec->base.max_references + 1;
575
576 if (dec->base.width * dec->base.height >= 4096*2000)
577 max_references = MAX2(max_references, 8);
578 else
579 max_references = MAX2(max_references, 17);
580
581 log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
582 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
583
584 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
585 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
586
587 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
588 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
589 max_mb_address = (unsigned) ceil(height * 8 / 2048.0);
590
591 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
592 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
593
594 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
595 }
596
597 static rvcn_dec_message_vc1_t get_vc1_msg(struct pipe_vc1_picture_desc *pic)
598 {
599 rvcn_dec_message_vc1_t result;
600
601 memset(&result, 0, sizeof(result));
602 switch(pic->base.profile) {
603 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
604 result.profile = RDECODE_VC1_PROFILE_SIMPLE;
605 result.level = 1;
606 break;
607
608 case PIPE_VIDEO_PROFILE_VC1_MAIN:
609 result.profile = RDECODE_VC1_PROFILE_MAIN;
610 result.level = 2;
611 break;
612
613 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
614 result.profile = RDECODE_VC1_PROFILE_ADVANCED;
615 result.level = 4;
616 break;
617
618 default:
619 assert(0);
620 }
621
622 result.sps_info_flags |= pic->postprocflag << 7;
623 result.sps_info_flags |= pic->pulldown << 6;
624 result.sps_info_flags |= pic->interlace << 5;
625 result.sps_info_flags |= pic->tfcntrflag << 4;
626 result.sps_info_flags |= pic->finterpflag << 3;
627 result.sps_info_flags |= pic->psf << 1;
628
629 result.pps_info_flags |= pic->range_mapy_flag << 31;
630 result.pps_info_flags |= pic->range_mapy << 28;
631 result.pps_info_flags |= pic->range_mapuv_flag << 27;
632 result.pps_info_flags |= pic->range_mapuv << 24;
633 result.pps_info_flags |= pic->multires << 21;
634 result.pps_info_flags |= pic->maxbframes << 16;
635 result.pps_info_flags |= pic->overlap << 11;
636 result.pps_info_flags |= pic->quantizer << 9;
637 result.pps_info_flags |= pic->panscan_flag << 7;
638 result.pps_info_flags |= pic->refdist_flag << 6;
639 result.pps_info_flags |= pic->vstransform << 0;
640
641 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
642 result.pps_info_flags |= pic->syncmarker << 20;
643 result.pps_info_flags |= pic->rangered << 19;
644 result.pps_info_flags |= pic->loopfilter << 5;
645 result.pps_info_flags |= pic->fastuvmc << 4;
646 result.pps_info_flags |= pic->extended_mv << 3;
647 result.pps_info_flags |= pic->extended_dmv << 8;
648 result.pps_info_flags |= pic->dquant << 1;
649 }
650
651 result.chroma_format = 1;
652
653 return result;
654 }
655
656 static uint32_t get_ref_pic_idx(struct radeon_decoder *dec, struct pipe_video_buffer *ref)
657 {
658 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
659 uint32_t max = MAX2(dec->frame_number, 1) - 1;
660 uintptr_t frame;
661
662 /* seems to be the most sane fallback */
663 if (!ref)
664 return max;
665
666 /* get the frame number from the associated data */
667 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
668
669 /* limit the frame number to a valid range */
670 return MAX2(MIN2(frame, max), min);
671 }
672
673 static rvcn_dec_message_mpeg2_vld_t get_mpeg2_msg(struct radeon_decoder *dec,
674 struct pipe_mpeg12_picture_desc *pic)
675 {
676 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
677 rvcn_dec_message_mpeg2_vld_t result;
678 unsigned i;
679
680 memset(&result, 0, sizeof(result));
681 result.decoded_pic_idx = dec->frame_number;
682
683 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
684 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
685
686 if(pic->intra_matrix) {
687 result.load_intra_quantiser_matrix = 1;
688 for (i = 0; i < 64; ++i) {
689 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
690 }
691 }
692 if(pic->non_intra_matrix) {
693 result.load_nonintra_quantiser_matrix = 1;
694 for (i = 0; i < 64; ++i) {
695 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
696 }
697 }
698
699 result.profile_and_level_indication = 0;
700 result.chroma_format = 0x1;
701
702 result.picture_coding_type = pic->picture_coding_type;
703 result.f_code[0][0] = pic->f_code[0][0] + 1;
704 result.f_code[0][1] = pic->f_code[0][1] + 1;
705 result.f_code[1][0] = pic->f_code[1][0] + 1;
706 result.f_code[1][1] = pic->f_code[1][1] + 1;
707 result.intra_dc_precision = pic->intra_dc_precision;
708 result.pic_structure = pic->picture_structure;
709 result.top_field_first = pic->top_field_first;
710 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
711 result.concealment_motion_vectors = pic->concealment_motion_vectors;
712 result.q_scale_type = pic->q_scale_type;
713 result.intra_vlc_format = pic->intra_vlc_format;
714 result.alternate_scan = pic->alternate_scan;
715
716 return result;
717 }
718
719 static rvcn_dec_message_mpeg4_asp_vld_t get_mpeg4_msg(struct radeon_decoder *dec,
720 struct pipe_mpeg4_picture_desc *pic)
721 {
722 rvcn_dec_message_mpeg4_asp_vld_t result;
723 unsigned i;
724
725 memset(&result, 0, sizeof(result));
726 result.decoded_pic_idx = dec->frame_number;
727
728 result.forward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[0]);
729 result.backward_ref_pic_idx = get_ref_pic_idx(dec, pic->ref[1]);
730
731 result.variant_type = 0;
732 result.profile_and_level_indication = 0xF0;
733
734 result.video_object_layer_verid = 0x5;
735 result.video_object_layer_shape = 0x0;
736
737 result.video_object_layer_width = dec->base.width;
738 result.video_object_layer_height = dec->base.height;
739
740 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
741
742 result.short_video_header = pic->short_video_header;
743 result.interlaced = pic->interlaced;
744 result.load_intra_quant_mat = 1;
745 result.load_nonintra_quant_mat = 1;
746 result.quarter_sample = pic->quarter_sample;
747 result.complexity_estimation_disable = 1;
748 result.resync_marker_disable = pic->resync_marker_disable;
749 result.newpred_enable = 0;
750 result.reduced_resolution_vop_enable = 0;
751
752 result.quant_type = pic->quant_type;
753
754 for (i = 0; i < 64; ++i) {
755 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
756 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
757 }
758
759 return result;
760 }
761
762 static void rvcn_dec_message_create(struct radeon_decoder *dec)
763 {
764 rvcn_dec_message_header_t *header = dec->msg;
765 rvcn_dec_message_create_t *create = dec->msg + sizeof(rvcn_dec_message_header_t);
766 unsigned sizes = sizeof(rvcn_dec_message_header_t) + sizeof(rvcn_dec_message_create_t);
767
768 memset(dec->msg, 0, sizes);
769 header->header_size = sizeof(rvcn_dec_message_header_t);
770 header->total_size = sizes;
771 header->num_buffers = 1;
772 header->msg_type = RDECODE_MSG_CREATE;
773 header->stream_handle = dec->stream_handle;
774 header->status_report_feedback_number = 0;
775
776 header->index[0].message_id = RDECODE_MESSAGE_CREATE;
777 header->index[0].offset = sizeof(rvcn_dec_message_header_t);
778 header->index[0].size = sizeof(rvcn_dec_message_create_t);
779 header->index[0].filled = 0;
780
781 create->stream_type = dec->stream_type;
782 create->session_flags = 0;
783 create->width_in_samples = dec->base.width;
784 create->height_in_samples = dec->base.height;
785 }
786
787 static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
788 struct pipe_video_buffer *target,
789 struct pipe_picture_desc *picture)
790 {
791 struct si_texture *luma = (struct si_texture *)
792 ((struct vl_video_buffer *)target)->resources[0];
793 struct si_texture *chroma = (struct si_texture *)
794 ((struct vl_video_buffer *)target)->resources[1];
795 rvcn_dec_message_header_t *header;
796 rvcn_dec_message_index_t *index;
797 rvcn_dec_message_decode_t *decode;
798 unsigned sizes = 0, offset_decode, offset_codec;
799 void *codec;
800
801 header = dec->msg;
802 sizes += sizeof(rvcn_dec_message_header_t);
803 index = (void*)header + sizeof(rvcn_dec_message_header_t);
804 sizes += sizeof(rvcn_dec_message_index_t);
805 offset_decode = sizes;
806 decode = (void*)index + sizeof(rvcn_dec_message_index_t);
807 sizes += sizeof(rvcn_dec_message_decode_t);
808 offset_codec = sizes;
809 codec = (void*)decode + sizeof(rvcn_dec_message_decode_t);
810
811 memset(dec->msg, 0, sizes);
812 header->header_size = sizeof(rvcn_dec_message_header_t);
813 header->total_size = sizes;
814 header->num_buffers = 2;
815 header->msg_type = RDECODE_MSG_DECODE;
816 header->stream_handle = dec->stream_handle;
817 header->status_report_feedback_number = dec->frame_number;
818
819 header->index[0].message_id = RDECODE_MESSAGE_DECODE;
820 header->index[0].offset = offset_decode;
821 header->index[0].size = sizeof(rvcn_dec_message_decode_t);
822 header->index[0].filled = 0;
823
824 index->offset = offset_codec;
825 index->size = sizeof(rvcn_dec_message_avc_t);
826 index->filled = 0;
827
828 decode->stream_type = dec->stream_type;
829 decode->decode_flags = 0x1;
830 decode->width_in_samples = dec->base.width;
831 decode->height_in_samples = dec->base.height;
832
833 decode->bsd_size = align(dec->bs_size, 128);
834 decode->dpb_size = dec->dpb.res->buf->size;
835 decode->dt_size =
836 si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size +
837 si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size;
838
839 decode->sct_size = 0;
840 decode->sc_coeff_size = 0;
841
842 decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
843 decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10 &&
844 dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
845 align(dec->base.width, 64) :
846 align(dec->base.width, 32) ;
847 decode->db_surf_tile_config = 0;
848
849 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
850 decode->dt_uv_pitch = decode->dt_pitch / 2;
851
852 decode->dt_tiling_mode = 0;
853 decode->dt_swizzle_mode = RDECODE_SW_MODE_LINEAR;
854 decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
855 decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
856 decode->dt_surf_tile_config = 0;
857 decode->dt_uv_surf_tile_config = 0;
858
859 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
860 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
861 if (decode->dt_field_mode) {
862 decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset +
863 luma->surface.u.gfx9.surf_slice_size;
864 decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset +
865 chroma->surface.u.gfx9.surf_slice_size;
866 } else {
867 decode->dt_luma_bottom_offset = decode->dt_luma_top_offset;
868 decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
869 }
870
871 switch (u_reduce_video_profile(picture->profile)) {
872 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
873 rvcn_dec_message_avc_t avc =
874 get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture);
875 memcpy(codec, (void*)&avc, sizeof(rvcn_dec_message_avc_t));
876 index->message_id = RDECODE_MESSAGE_AVC;
877 break;
878 }
879 case PIPE_VIDEO_FORMAT_HEVC: {
880 rvcn_dec_message_hevc_t hevc =
881 get_h265_msg(dec, target, (struct pipe_h265_picture_desc*)picture);
882
883 memcpy(codec, (void*)&hevc, sizeof(rvcn_dec_message_hevc_t));
884 index->message_id = RDECODE_MESSAGE_HEVC;
885 if (dec->ctx.res == NULL) {
886 unsigned ctx_size;
887 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
888 ctx_size = calc_ctx_size_h265_main10(dec,
889 (struct pipe_h265_picture_desc*)picture);
890 else
891 ctx_size = calc_ctx_size_h265_main(dec);
892 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
893 RVID_ERR("Can't allocated context buffer.\n");
894 si_vid_clear_buffer(dec->base.context, &dec->ctx);
895 }
896 break;
897 }
898 case PIPE_VIDEO_FORMAT_VC1: {
899 rvcn_dec_message_vc1_t vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture);
900
901 memcpy(codec, (void*)&vc1, sizeof(rvcn_dec_message_vc1_t));
902 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
903 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
904 decode->width_in_samples = align(decode->width_in_samples, 16) / 16;
905 decode->height_in_samples = align(decode->height_in_samples, 16) / 16;
906 }
907 index->message_id = RDECODE_MESSAGE_VC1;
908 break;
909
910 }
911 case PIPE_VIDEO_FORMAT_MPEG12: {
912 rvcn_dec_message_mpeg2_vld_t mpeg2 =
913 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture);
914
915 memcpy(codec, (void*)&mpeg2, sizeof(rvcn_dec_message_mpeg2_vld_t));
916 index->message_id = RDECODE_MESSAGE_MPEG2_VLD;
917 break;
918 }
919 case PIPE_VIDEO_FORMAT_MPEG4: {
920 rvcn_dec_message_mpeg4_asp_vld_t mpeg4 =
921 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture);
922
923 memcpy(codec, (void*)&mpeg4, sizeof(rvcn_dec_message_mpeg4_asp_vld_t));
924 index->message_id = RDECODE_MESSAGE_MPEG4_ASP_VLD;
925 break;
926 }
927 case PIPE_VIDEO_FORMAT_VP9: {
928 rvcn_dec_message_vp9_t vp9 =
929 get_vp9_msg(dec, target, (struct pipe_vp9_picture_desc*)picture);
930
931 memcpy(codec, (void*)&vp9, sizeof(rvcn_dec_message_vp9_t));
932 index->message_id = RDECODE_MESSAGE_VP9;
933
934 if (dec->ctx.res == NULL) {
935 unsigned ctx_size;
936 uint8_t *ptr;
937
938 /* default probability + probability data */
939 ctx_size = 2304 * 5;
940
941 if (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10) {
942 /* SRE collocated context data */
943 ctx_size += 32 * 2 * 128 * 68;
944 /* SMP collocated context data */
945 ctx_size += 9 * 64 * 2 * 128 * 68;
946 /* SDB left tile pixel */
947 ctx_size += 8 * 2 * 8192;
948 } else {
949 ctx_size += 32 * 2 * 64 * 64;
950 ctx_size += 9 * 64 * 2 * 64 * 64;
951 ctx_size += 8 * 2 * 4096;
952 }
953
954 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
955 ctx_size += 8 * 2 * 4096;
956
957 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT))
958 RVID_ERR("Can't allocated context buffer.\n");
959 si_vid_clear_buffer(dec->base.context, &dec->ctx);
960
961 /* ctx needs probs table */
962 ptr = dec->ws->buffer_map(
963 dec->ctx.res->buf, dec->cs,
964 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
965 fill_probs_table(ptr);
966 dec->ws->buffer_unmap(dec->ctx.res->buf);
967 }
968 break;
969 }
970 default:
971 assert(0);
972 return NULL;
973 }
974
975 if (dec->ctx.res)
976 decode->hw_ctxt_size = dec->ctx.res->buf->size;
977
978 return luma->buffer.buf;
979 }
980
981 static void rvcn_dec_message_destroy(struct radeon_decoder *dec)
982 {
983 rvcn_dec_message_header_t *header = dec->msg;
984
985 memset(dec->msg, 0, sizeof(rvcn_dec_message_header_t));
986 header->header_size = sizeof(rvcn_dec_message_header_t);
987 header->total_size = sizeof(rvcn_dec_message_header_t) -
988 sizeof(rvcn_dec_message_index_t);
989 header->num_buffers = 0;
990 header->msg_type = RDECODE_MSG_DESTROY;
991 header->stream_handle = dec->stream_handle;
992 header->status_report_feedback_number = 0;
993 }
994
995 static void rvcn_dec_message_feedback(struct radeon_decoder *dec)
996 {
997 rvcn_dec_feedback_header_t *header = (void*)dec->fb;
998
999 header->header_size = sizeof(rvcn_dec_feedback_header_t);
1000 header->total_size = sizeof(rvcn_dec_feedback_header_t);
1001 header->num_buffers = 0;
1002 }
1003
1004 /* flush IB to the hardware */
1005 static int flush(struct radeon_decoder *dec, unsigned flags)
1006 {
1007 return dec->ws->cs_flush(dec->cs, flags, NULL);
1008 }
1009
1010 /* add a new set register command to the IB */
1011 static void set_reg(struct radeon_decoder *dec, unsigned reg, uint32_t val)
1012 {
1013 radeon_emit(dec->cs, RDECODE_PKT0(reg >> 2, 0));
1014 radeon_emit(dec->cs, val);
1015 }
1016
1017 /* send a command to the VCPU through the GPCOM registers */
1018 static void send_cmd(struct radeon_decoder *dec, unsigned cmd,
1019 struct pb_buffer* buf, uint32_t off,
1020 enum radeon_bo_usage usage, enum radeon_bo_domain domain)
1021 {
1022 uint64_t addr;
1023
1024 dec->ws->cs_add_buffer(dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
1025 domain, 0);
1026 addr = dec->ws->buffer_get_virtual_address(buf);
1027 addr = addr + off;
1028
1029 set_reg(dec, dec->reg.data0, addr);
1030 set_reg(dec, dec->reg.data1, addr >> 32);
1031 set_reg(dec, dec->reg.cmd, cmd << 1);
1032 }
1033
1034 /* do the codec needs an IT buffer ?*/
1035 static bool have_it(struct radeon_decoder *dec)
1036 {
1037 return dec->stream_type == RDECODE_CODEC_H264_PERF ||
1038 dec->stream_type == RDECODE_CODEC_H265;
1039 }
1040
1041 /* do the codec needs an probs buffer? */
1042 static bool have_probs(struct radeon_decoder *dec)
1043 {
1044 return dec->stream_type == RDECODE_CODEC_VP9;
1045 }
1046
1047 /* map the next available message/feedback/itscaling buffer */
1048 static void map_msg_fb_it_probs_buf(struct radeon_decoder *dec)
1049 {
1050 struct rvid_buffer* buf;
1051 uint8_t *ptr;
1052
1053 /* grab the current message/feedback buffer */
1054 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1055
1056 /* and map it for CPU access */
1057 ptr = dec->ws->buffer_map(buf->res->buf, dec->cs,
1058 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1059
1060 /* calc buffer offsets */
1061 dec->msg = ptr;
1062
1063 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
1064 if (have_it(dec))
1065 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1066 else if (have_probs(dec))
1067 dec->probs = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
1068 }
1069
1070 /* unmap and send a message command to the VCPU */
1071 static void send_msg_buf(struct radeon_decoder *dec)
1072 {
1073 struct rvid_buffer* buf;
1074
1075 /* ignore the request if message/feedback buffer isn't mapped */
1076 if (!dec->msg || !dec->fb)
1077 return;
1078
1079 /* grab the current message buffer */
1080 buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1081
1082 /* unmap the buffer */
1083 dec->ws->buffer_unmap(buf->res->buf);
1084 dec->msg = NULL;
1085 dec->fb = NULL;
1086 dec->it = NULL;
1087 dec->probs = NULL;
1088
1089 if (dec->sessionctx.res)
1090 send_cmd(dec, RDECODE_CMD_SESSION_CONTEXT_BUFFER,
1091 dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
1092 RADEON_DOMAIN_VRAM);
1093
1094 /* and send it to the hardware */
1095 send_cmd(dec, RDECODE_CMD_MSG_BUFFER, buf->res->buf, 0,
1096 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1097 }
1098
1099 /* cycle to the next set of buffers */
1100 static void next_buffer(struct radeon_decoder *dec)
1101 {
1102 ++dec->cur_buffer;
1103 dec->cur_buffer %= NUM_BUFFERS;
1104 }
1105
1106 static unsigned calc_ctx_size_h264_perf(struct radeon_decoder *dec)
1107 {
1108 unsigned width_in_mb, height_in_mb, ctx_size;
1109 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1110 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1111
1112 unsigned max_references = dec->base.max_references + 1;
1113
1114 // picture width & height in 16 pixel units
1115 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1116 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1117
1118 unsigned fs_in_mb = width_in_mb * height_in_mb;
1119 unsigned num_dpb_buffer;
1120 switch(dec->base.level) {
1121 case 30:
1122 num_dpb_buffer = 8100 / fs_in_mb;
1123 break;
1124 case 31:
1125 num_dpb_buffer = 18000 / fs_in_mb;
1126 break;
1127 case 32:
1128 num_dpb_buffer = 20480 / fs_in_mb;
1129 break;
1130 case 41:
1131 num_dpb_buffer = 32768 / fs_in_mb;
1132 break;
1133 case 42:
1134 num_dpb_buffer = 34816 / fs_in_mb;
1135 break;
1136 case 50:
1137 num_dpb_buffer = 110400 / fs_in_mb;
1138 break;
1139 case 51:
1140 num_dpb_buffer = 184320 / fs_in_mb;
1141 break;
1142 default:
1143 num_dpb_buffer = 184320 / fs_in_mb;
1144 break;
1145 }
1146 num_dpb_buffer++;
1147 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1148 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
1149
1150 return ctx_size;
1151 }
1152
1153 /* calculate size of reference picture buffer */
1154 static unsigned calc_dpb_size(struct radeon_decoder *dec)
1155 {
1156 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
1157
1158 // always align them to MB size for dpb calculation
1159 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
1160 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
1161
1162 // always one more for currently decoded picture
1163 unsigned max_references = dec->base.max_references + 1;
1164
1165 // aligned size of a single frame
1166 image_size = align(width, 32) * height;
1167 image_size += image_size / 2;
1168 image_size = align(image_size, 1024);
1169
1170 // picture width & height in 16 pixel units
1171 width_in_mb = width / VL_MACROBLOCK_WIDTH;
1172 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
1173
1174 switch (u_reduce_video_profile(dec->base.profile)) {
1175 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
1176 unsigned fs_in_mb = width_in_mb * height_in_mb;
1177 unsigned num_dpb_buffer;
1178
1179 switch(dec->base.level) {
1180 case 30:
1181 num_dpb_buffer = 8100 / fs_in_mb;
1182 break;
1183 case 31:
1184 num_dpb_buffer = 18000 / fs_in_mb;
1185 break;
1186 case 32:
1187 num_dpb_buffer = 20480 / fs_in_mb;
1188 break;
1189 case 41:
1190 num_dpb_buffer = 32768 / fs_in_mb;
1191 break;
1192 case 42:
1193 num_dpb_buffer = 34816 / fs_in_mb;
1194 break;
1195 case 50:
1196 num_dpb_buffer = 110400 / fs_in_mb;
1197 break;
1198 case 51:
1199 num_dpb_buffer = 184320 / fs_in_mb;
1200 break;
1201 default:
1202 num_dpb_buffer = 184320 / fs_in_mb;
1203 break;
1204 }
1205 num_dpb_buffer++;
1206 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer), max_references);
1207 dpb_size = image_size * max_references;
1208 break;
1209 }
1210
1211 case PIPE_VIDEO_FORMAT_HEVC:
1212 if (dec->base.width * dec->base.height >= 4096*2000)
1213 max_references = MAX2(max_references, 8);
1214 else
1215 max_references = MAX2(max_references, 17);
1216
1217 width = align (width, 16);
1218 height = align (height, 16);
1219 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1220 dpb_size = align((align(width, 32) * height * 9) / 4, 256) * max_references;
1221 else
1222 dpb_size = align((align(width, 32) * height * 3) / 2, 256) * max_references;
1223 break;
1224
1225 case PIPE_VIDEO_FORMAT_VC1:
1226 // the firmware seems to allways assume a minimum of ref frames
1227 max_references = MAX2(NUM_VC1_REFS, max_references);
1228
1229 // reference picture buffer
1230 dpb_size = image_size * max_references;
1231
1232 // CONTEXT_BUFFER
1233 dpb_size += width_in_mb * height_in_mb * 128;
1234
1235 // IT surface buffer
1236 dpb_size += width_in_mb * 64;
1237
1238 // DB surface buffer
1239 dpb_size += width_in_mb * 128;
1240
1241 // BP
1242 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
1243 break;
1244
1245 case PIPE_VIDEO_FORMAT_MPEG12:
1246 // reference picture buffer, must be big enough for all frames
1247 dpb_size = image_size * NUM_MPEG2_REFS;
1248 break;
1249
1250 case PIPE_VIDEO_FORMAT_MPEG4:
1251 // reference picture buffer
1252 dpb_size = image_size * max_references;
1253
1254 // CM
1255 dpb_size += width_in_mb * height_in_mb * 64;
1256
1257 // IT surface buffer
1258 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
1259
1260 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
1261 break;
1262
1263 case PIPE_VIDEO_FORMAT_VP9:
1264 max_references = MAX2(max_references, 9);
1265
1266 dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI10) ?
1267 (8192 * 4320 * 3 / 2) * max_references :
1268 (4096 * 3000 * 3 / 2) * max_references;
1269
1270 if (dec->base.profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
1271 dpb_size *= (3 / 2);
1272 break;
1273
1274 case PIPE_VIDEO_FORMAT_JPEG:
1275 dpb_size = 0;
1276 break;
1277
1278 default:
1279 // something is missing here
1280 assert(0);
1281
1282 // at least use a sane default value
1283 dpb_size = 32 * 1024 * 1024;
1284 break;
1285 }
1286 return dpb_size;
1287 }
1288
1289 /**
1290 * destroy this video decoder
1291 */
1292 static void radeon_dec_destroy(struct pipe_video_codec *decoder)
1293 {
1294 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1295 unsigned i;
1296
1297 assert(decoder);
1298
1299 map_msg_fb_it_probs_buf(dec);
1300 rvcn_dec_message_destroy(dec);
1301 send_msg_buf(dec);
1302
1303 flush(dec, 0);
1304
1305 dec->ws->cs_destroy(dec->cs);
1306
1307 for (i = 0; i < NUM_BUFFERS; ++i) {
1308 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1309 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1310 }
1311
1312 si_vid_destroy_buffer(&dec->dpb);
1313 si_vid_destroy_buffer(&dec->ctx);
1314 si_vid_destroy_buffer(&dec->sessionctx);
1315
1316 FREE(dec);
1317 }
1318
1319 /**
1320 * start decoding of a new frame
1321 */
1322 static void radeon_dec_begin_frame(struct pipe_video_codec *decoder,
1323 struct pipe_video_buffer *target,
1324 struct pipe_picture_desc *picture)
1325 {
1326 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1327 uintptr_t frame;
1328
1329 assert(decoder);
1330
1331 frame = ++dec->frame_number;
1332 if (dec->stream_type != RDECODE_CODEC_VP9)
1333 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1334 &radeon_dec_destroy_associated_data);
1335
1336 dec->bs_size = 0;
1337 dec->bs_ptr = dec->ws->buffer_map(
1338 dec->bs_buffers[dec->cur_buffer].res->buf,
1339 dec->cs, PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1340 }
1341
1342 /**
1343 * decode a macroblock
1344 */
1345 static void radeon_dec_decode_macroblock(struct pipe_video_codec *decoder,
1346 struct pipe_video_buffer *target,
1347 struct pipe_picture_desc *picture,
1348 const struct pipe_macroblock *macroblocks,
1349 unsigned num_macroblocks)
1350 {
1351 /* not supported (yet) */
1352 assert(0);
1353 }
1354
1355 /**
1356 * decode a bitstream
1357 */
1358 static void radeon_dec_decode_bitstream(struct pipe_video_codec *decoder,
1359 struct pipe_video_buffer *target,
1360 struct pipe_picture_desc *picture,
1361 unsigned num_buffers,
1362 const void * const *buffers,
1363 const unsigned *sizes)
1364 {
1365 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1366 unsigned i;
1367
1368 assert(decoder);
1369
1370 if (!dec->bs_ptr)
1371 return;
1372
1373 for (i = 0; i < num_buffers; ++i) {
1374 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1375 unsigned new_size = dec->bs_size + sizes[i];
1376
1377 if (new_size > buf->res->buf->size) {
1378 dec->ws->buffer_unmap(buf->res->buf);
1379 if (!si_vid_resize_buffer(dec->screen, dec->cs, buf, new_size)) {
1380 RVID_ERR("Can't resize bitstream buffer!");
1381 return;
1382 }
1383
1384 dec->bs_ptr = dec->ws->buffer_map(
1385 buf->res->buf, dec->cs,
1386 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1387 if (!dec->bs_ptr)
1388 return;
1389
1390 dec->bs_ptr += dec->bs_size;
1391 }
1392
1393 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1394 dec->bs_size += sizes[i];
1395 dec->bs_ptr += sizes[i];
1396 }
1397 }
1398
1399 /**
1400 * send cmd for vcn dec
1401 */
1402 void send_cmd_dec(struct radeon_decoder *dec,
1403 struct pipe_video_buffer *target,
1404 struct pipe_picture_desc *picture)
1405 {
1406 struct pb_buffer *dt;
1407 struct rvid_buffer *msg_fb_it_probs_buf, *bs_buf;
1408
1409 msg_fb_it_probs_buf = &dec->msg_fb_it_probs_buffers[dec->cur_buffer];
1410 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1411
1412 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
1413 dec->ws->buffer_unmap(bs_buf->res->buf);
1414
1415 map_msg_fb_it_probs_buf(dec);
1416 dt = rvcn_dec_message_decode(dec, target, picture);
1417 rvcn_dec_message_feedback(dec);
1418 send_msg_buf(dec);
1419
1420 send_cmd(dec, RDECODE_CMD_DPB_BUFFER, dec->dpb.res->buf, 0,
1421 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1422 if (dec->ctx.res)
1423 send_cmd(dec, RDECODE_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0,
1424 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
1425 send_cmd(dec, RDECODE_CMD_BITSTREAM_BUFFER, bs_buf->res->buf,
1426 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1427 send_cmd(dec, RDECODE_CMD_DECODING_TARGET_BUFFER, dt, 0,
1428 RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1429 send_cmd(dec, RDECODE_CMD_FEEDBACK_BUFFER, msg_fb_it_probs_buf->res->buf,
1430 FB_BUFFER_OFFSET, RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1431 if (have_it(dec))
1432 send_cmd(dec, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, msg_fb_it_probs_buf->res->buf,
1433 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1434 else if (have_probs(dec))
1435 send_cmd(dec, RDECODE_CMD_PROB_TBL_BUFFER, msg_fb_it_probs_buf->res->buf,
1436 FB_BUFFER_OFFSET + FB_BUFFER_SIZE, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1437 set_reg(dec, dec->reg.cntl, 1);
1438 }
1439
1440 /**
1441 * end decoding of the current frame
1442 */
1443 static void radeon_dec_end_frame(struct pipe_video_codec *decoder,
1444 struct pipe_video_buffer *target,
1445 struct pipe_picture_desc *picture)
1446 {
1447 struct radeon_decoder *dec = (struct radeon_decoder*)decoder;
1448
1449 assert(decoder);
1450
1451 if (!dec->bs_ptr)
1452 return;
1453
1454 dec->send_cmd(dec, target, picture);
1455 flush(dec, PIPE_FLUSH_ASYNC);
1456 next_buffer(dec);
1457 }
1458
1459 /**
1460 * flush any outstanding command buffers to the hardware
1461 */
1462 static void radeon_dec_flush(struct pipe_video_codec *decoder)
1463 {
1464 }
1465
1466 /**
1467 * create and HW decoder
1468 */
1469 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
1470 const struct pipe_video_codec *templ)
1471 {
1472 struct si_context *sctx = (struct si_context*)context;
1473 struct radeon_winsys *ws = sctx->ws;
1474 unsigned width = templ->width, height = templ->height;
1475 unsigned dpb_size, bs_buf_size, stream_type = 0, ring = RING_VCN_DEC;
1476 struct radeon_decoder *dec;
1477 int r, i;
1478
1479 switch(u_reduce_video_profile(templ->profile)) {
1480 case PIPE_VIDEO_FORMAT_MPEG12:
1481 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1482 return vl_create_mpeg12_decoder(context, templ);
1483 stream_type = RDECODE_CODEC_MPEG2_VLD;
1484 break;
1485 case PIPE_VIDEO_FORMAT_MPEG4:
1486 width = align(width, VL_MACROBLOCK_WIDTH);
1487 height = align(height, VL_MACROBLOCK_HEIGHT);
1488 stream_type = RDECODE_CODEC_MPEG4;
1489 break;
1490 case PIPE_VIDEO_FORMAT_VC1:
1491 stream_type = RDECODE_CODEC_VC1;
1492 break;
1493 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1494 width = align(width, VL_MACROBLOCK_WIDTH);
1495 height = align(height, VL_MACROBLOCK_HEIGHT);
1496 stream_type = RDECODE_CODEC_H264_PERF;
1497 break;
1498 case PIPE_VIDEO_FORMAT_HEVC:
1499 stream_type = RDECODE_CODEC_H265;
1500 break;
1501 case PIPE_VIDEO_FORMAT_VP9:
1502 stream_type = RDECODE_CODEC_VP9;
1503 break;
1504 case PIPE_VIDEO_FORMAT_JPEG:
1505 stream_type = RDECODE_CODEC_JPEG;
1506 ring = RING_VCN_JPEG;
1507 break;
1508 default:
1509 assert(0);
1510 break;
1511 }
1512
1513 dec = CALLOC_STRUCT(radeon_decoder);
1514
1515 if (!dec)
1516 return NULL;
1517
1518 dec->base = *templ;
1519 dec->base.context = context;
1520 dec->base.width = width;
1521 dec->base.height = height;
1522
1523 dec->base.destroy = radeon_dec_destroy;
1524 dec->base.begin_frame = radeon_dec_begin_frame;
1525 dec->base.decode_macroblock = radeon_dec_decode_macroblock;
1526 dec->base.decode_bitstream = radeon_dec_decode_bitstream;
1527 dec->base.end_frame = radeon_dec_end_frame;
1528 dec->base.flush = radeon_dec_flush;
1529
1530 dec->stream_type = stream_type;
1531 dec->stream_handle = si_vid_alloc_stream_handle();
1532 dec->screen = context->screen;
1533 dec->ws = ws;
1534 dec->cs = ws->cs_create(sctx->ctx, ring, NULL, NULL, false);
1535 if (!dec->cs) {
1536 RVID_ERR("Can't get command submission context.\n");
1537 goto error;
1538 }
1539
1540 for (i = 0; i < 16; i++)
1541 dec->render_pic_list[i] = NULL;
1542 bs_buf_size = width * height * (512 / (16 * 16));
1543 for (i = 0; i < NUM_BUFFERS; ++i) {
1544 unsigned msg_fb_it_probs_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1545 if (have_it(dec))
1546 msg_fb_it_probs_size += IT_SCALING_TABLE_SIZE;
1547 else if (have_probs(dec))
1548 msg_fb_it_probs_size += VP9_PROBS_TABLE_SIZE;
1549 /* use vram to improve performance, workaround an unknown bug */
1550 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_probs_buffers[i],
1551 msg_fb_it_probs_size, PIPE_USAGE_DEFAULT)) {
1552 RVID_ERR("Can't allocated message buffers.\n");
1553 goto error;
1554 }
1555
1556 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i],
1557 bs_buf_size, PIPE_USAGE_STAGING)) {
1558 RVID_ERR("Can't allocated bitstream buffers.\n");
1559 goto error;
1560 }
1561
1562 si_vid_clear_buffer(context, &dec->msg_fb_it_probs_buffers[i]);
1563 si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1564
1565 if (have_probs(dec)) {
1566 struct rvid_buffer* buf;
1567 void *ptr;
1568
1569 buf = &dec->msg_fb_it_probs_buffers[i];
1570 ptr = dec->ws->buffer_map(
1571 buf->res->buf, dec->cs,
1572 PIPE_TRANSFER_WRITE | RADEON_TRANSFER_TEMPORARY);
1573 ptr += FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
1574 fill_probs_table(ptr);
1575 dec->ws->buffer_unmap(buf->res->buf);
1576 }
1577 }
1578
1579 dpb_size = calc_dpb_size(dec);
1580 if (dpb_size) {
1581 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1582 RVID_ERR("Can't allocated dpb.\n");
1583 goto error;
1584 }
1585 si_vid_clear_buffer(context, &dec->dpb);
1586 }
1587
1588 if (dec->stream_type == RDECODE_CODEC_H264_PERF) {
1589 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1590 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1591 RVID_ERR("Can't allocated context buffer.\n");
1592 goto error;
1593 }
1594 si_vid_clear_buffer(context, &dec->ctx);
1595 }
1596
1597 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
1598 RDECODE_SESSION_CONTEXT_SIZE,
1599 PIPE_USAGE_DEFAULT)) {
1600 RVID_ERR("Can't allocated session ctx.\n");
1601 goto error;
1602 }
1603 si_vid_clear_buffer(context, &dec->sessionctx);
1604
1605 if (sctx->family == CHIP_ARCTURUS) {
1606 dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
1607 dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
1608 dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
1609 dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
1610 } else if (sctx->family >= CHIP_NAVI10) {
1611 dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
1612 dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
1613 dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
1614 dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
1615 dec->jpg.direct_reg = true;
1616 } else {
1617 dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
1618 dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
1619 dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
1620 dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
1621 dec->jpg.direct_reg = false;
1622 }
1623
1624 map_msg_fb_it_probs_buf(dec);
1625 rvcn_dec_message_create(dec);
1626 send_msg_buf(dec);
1627 r = flush(dec, 0);
1628 if (r)
1629 goto error;
1630
1631 next_buffer(dec);
1632
1633 if (stream_type == RDECODE_CODEC_JPEG)
1634 dec->send_cmd = send_cmd_jpeg;
1635 else
1636 dec->send_cmd = send_cmd_dec;
1637
1638 return &dec->base;
1639
1640 error:
1641 if (dec->cs) dec->ws->cs_destroy(dec->cs);
1642
1643 for (i = 0; i < NUM_BUFFERS; ++i) {
1644 si_vid_destroy_buffer(&dec->msg_fb_it_probs_buffers[i]);
1645 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1646 }
1647
1648 si_vid_destroy_buffer(&dec->dpb);
1649 si_vid_destroy_buffer(&dec->ctx);
1650 si_vid_destroy_buffer(&dec->sessionctx);
1651
1652 FREE(dec);
1653
1654 return NULL;
1655 }