1 /**************************************************************************
3 * Copyright 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "pipe/p_video_codec.h"
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
35 #include "vl/vl_video_buffer.h"
37 #include "radeonsi/si_pipe.h"
38 #include "radeon_video.h"
39 #include "radeon_vcn_enc.h"
41 static void radeon_vcn_enc_get_param(struct radeon_encoder
*enc
, struct pipe_picture_desc
*picture
)
43 if (u_reduce_video_profile(picture
->profile
) == PIPE_VIDEO_FORMAT_MPEG4_AVC
) {
44 struct pipe_h264_enc_picture_desc
*pic
= (struct pipe_h264_enc_picture_desc
*)picture
;
45 enc
->enc_pic
.picture_type
= pic
->picture_type
;
46 enc
->enc_pic
.frame_num
= pic
->frame_num
;
47 enc
->enc_pic
.pic_order_cnt
= pic
->pic_order_cnt
;
48 enc
->enc_pic
.pic_order_cnt_type
= pic
->pic_order_cnt_type
;
49 enc
->enc_pic
.ref_idx_l0
= pic
->ref_idx_l0
;
50 enc
->enc_pic
.ref_idx_l1
= pic
->ref_idx_l1
;
51 enc
->enc_pic
.not_referenced
= pic
->not_referenced
;
52 enc
->enc_pic
.is_idr
= (pic
->picture_type
== PIPE_H264_ENC_PICTURE_TYPE_IDR
);
53 enc
->enc_pic
.crop_left
= 0;
54 enc
->enc_pic
.crop_right
= (align(enc
->base
.width
, 16) - enc
->base
.width
) / 2;
55 enc
->enc_pic
.crop_top
= 0;
56 enc
->enc_pic
.crop_bottom
= (align(enc
->base
.height
, 16) - enc
->base
.height
) / 2;
57 } else if (u_reduce_video_profile(picture
->profile
) == PIPE_VIDEO_FORMAT_HEVC
) {
58 struct pipe_h265_enc_picture_desc
*pic
= (struct pipe_h265_enc_picture_desc
*)picture
;
59 enc
->enc_pic
.picture_type
= pic
->picture_type
;
60 enc
->enc_pic
.frame_num
= pic
->frame_num
;
61 enc
->enc_pic
.pic_order_cnt
= pic
->pic_order_cnt
;
62 enc
->enc_pic
.pic_order_cnt_type
= pic
->pic_order_cnt_type
;
63 enc
->enc_pic
.ref_idx_l0
= pic
->ref_idx_l0
;
64 enc
->enc_pic
.ref_idx_l1
= pic
->ref_idx_l1
;
65 enc
->enc_pic
.not_referenced
= pic
->not_referenced
;
66 enc
->enc_pic
.is_idr
= (pic
->picture_type
== PIPE_H265_ENC_PICTURE_TYPE_IDR
) ||
67 (pic
->picture_type
== PIPE_H265_ENC_PICTURE_TYPE_I
);
68 enc
->enc_pic
.crop_left
= 0;
69 enc
->enc_pic
.crop_right
= (align(enc
->base
.width
, 16) - enc
->base
.width
) / 2;
70 enc
->enc_pic
.crop_top
= 0;
71 enc
->enc_pic
.crop_bottom
= (align(enc
->base
.height
, 16) - enc
->base
.height
) / 2;
72 enc
->enc_pic
.general_tier_flag
= pic
->seq
.general_tier_flag
;
73 enc
->enc_pic
.general_profile_idc
= pic
->seq
.general_profile_idc
;
74 enc
->enc_pic
.general_level_idc
= pic
->seq
.general_level_idc
;
75 enc
->enc_pic
.max_poc
= pic
->seq
.intra_period
;
76 enc
->enc_pic
.log2_max_poc
= 0;
77 for (int i
= enc
->enc_pic
.max_poc
; i
!= 0; enc
->enc_pic
.log2_max_poc
++)
79 enc
->enc_pic
.chroma_format_idc
= pic
->seq
.chroma_format_idc
;
80 enc
->enc_pic
.pic_width_in_luma_samples
= pic
->seq
.pic_width_in_luma_samples
;
81 enc
->enc_pic
.pic_height_in_luma_samples
= pic
->seq
.pic_height_in_luma_samples
;
82 enc
->enc_pic
.log2_diff_max_min_luma_coding_block_size
= pic
->seq
.log2_diff_max_min_luma_coding_block_size
;
83 enc
->enc_pic
.log2_min_transform_block_size_minus2
= pic
->seq
.log2_min_transform_block_size_minus2
;
84 enc
->enc_pic
.log2_diff_max_min_transform_block_size
= pic
->seq
.log2_diff_max_min_transform_block_size
;
85 enc
->enc_pic
.max_transform_hierarchy_depth_inter
= pic
->seq
.max_transform_hierarchy_depth_inter
;
86 enc
->enc_pic
.max_transform_hierarchy_depth_intra
= pic
->seq
.max_transform_hierarchy_depth_intra
;
87 enc
->enc_pic
.log2_parallel_merge_level_minus2
= pic
->pic
.log2_parallel_merge_level_minus2
;
88 enc
->enc_pic
.bit_depth_luma_minus8
= pic
->seq
.bit_depth_luma_minus8
;
89 enc
->enc_pic
.bit_depth_chroma_minus8
= pic
->seq
.bit_depth_chroma_minus8
;
90 enc
->enc_pic
.nal_unit_type
= pic
->pic
.nal_unit_type
;
91 enc
->enc_pic
.max_num_merge_cand
= pic
->slice
.max_num_merge_cand
;
92 enc
->enc_pic
.sample_adaptive_offset_enabled_flag
= pic
->seq
.sample_adaptive_offset_enabled_flag
;
93 enc
->enc_pic
.pcm_enabled_flag
= pic
->seq
.pcm_enabled_flag
;
94 enc
->enc_pic
.sps_temporal_mvp_enabled_flag
= pic
->seq
.sps_temporal_mvp_enabled_flag
;
98 static void flush(struct radeon_encoder
*enc
)
100 enc
->ws
->cs_flush(enc
->cs
, PIPE_FLUSH_ASYNC
, NULL
);
103 static void radeon_enc_flush(struct pipe_video_codec
*encoder
)
105 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
109 static void radeon_enc_cs_flush(void *ctx
, unsigned flags
,
110 struct pipe_fence_handle
**fence
)
115 static unsigned get_cpb_num(struct radeon_encoder
*enc
)
117 unsigned w
= align(enc
->base
.width
, 16) / 16;
118 unsigned h
= align(enc
->base
.height
, 16) / 16;
121 switch (enc
->base
.level
) {
163 return MIN2(dpb
/ (w
* h
), 16);
166 static void radeon_enc_begin_frame(struct pipe_video_codec
*encoder
,
167 struct pipe_video_buffer
*source
,
168 struct pipe_picture_desc
*picture
)
170 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
171 struct vl_video_buffer
*vid_buf
= (struct vl_video_buffer
*)source
;
173 radeon_vcn_enc_get_param(enc
, picture
);
175 enc
->get_buffer(vid_buf
->resources
[0], &enc
->handle
, &enc
->luma
);
176 enc
->get_buffer(vid_buf
->resources
[1], NULL
, &enc
->chroma
);
178 enc
->need_feedback
= false;
180 if (!enc
->stream_handle
) {
181 struct rvid_buffer fb
;
182 enc
->stream_handle
= si_vid_alloc_stream_handle();
183 enc
->si
= CALLOC_STRUCT(rvid_buffer
);
184 si_vid_create_buffer(enc
->screen
, enc
->si
, 128 * 1024, PIPE_USAGE_STAGING
);
185 si_vid_create_buffer(enc
->screen
, &fb
, 4096, PIPE_USAGE_STAGING
);
187 enc
->begin(enc
, picture
);
189 si_vid_destroy_buffer(&fb
);
193 static void radeon_enc_encode_bitstream(struct pipe_video_codec
*encoder
,
194 struct pipe_video_buffer
*source
,
195 struct pipe_resource
*destination
,
198 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
199 enc
->get_buffer(destination
, &enc
->bs_handle
, NULL
);
200 enc
->bs_size
= destination
->width0
;
202 *fb
= enc
->fb
= CALLOC_STRUCT(rvid_buffer
);
204 if (!si_vid_create_buffer(enc
->screen
, enc
->fb
, 4096, PIPE_USAGE_STAGING
)) {
205 RVID_ERR("Can't create feedback buffer.\n");
209 enc
->need_feedback
= true;
213 static void radeon_enc_end_frame(struct pipe_video_codec
*encoder
,
214 struct pipe_video_buffer
*source
,
215 struct pipe_picture_desc
*picture
)
217 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
221 static void radeon_enc_destroy(struct pipe_video_codec
*encoder
)
223 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
225 if (enc
->stream_handle
) {
226 struct rvid_buffer fb
;
227 enc
->need_feedback
= false;
228 si_vid_create_buffer(enc
->screen
, &fb
, 512, PIPE_USAGE_STAGING
);
232 si_vid_destroy_buffer(&fb
);
235 si_vid_destroy_buffer(&enc
->cpb
);
236 enc
->ws
->cs_destroy(enc
->cs
);
240 static void radeon_enc_get_feedback(struct pipe_video_codec
*encoder
,
241 void *feedback
, unsigned *size
)
243 struct radeon_encoder
*enc
= (struct radeon_encoder
*)encoder
;
244 struct rvid_buffer
*fb
= feedback
;
247 uint32_t *ptr
= enc
->ws
->buffer_map(fb
->res
->buf
, enc
->cs
, PIPE_TRANSFER_READ_WRITE
);
252 enc
->ws
->buffer_unmap(fb
->res
->buf
);
255 si_vid_destroy_buffer(fb
);
259 struct pipe_video_codec
*radeon_create_encoder(struct pipe_context
*context
,
260 const struct pipe_video_codec
*templ
,
261 struct radeon_winsys
* ws
,
262 radeon_enc_get_buffer get_buffer
)
264 struct si_screen
*sscreen
= (struct si_screen
*)context
->screen
;
265 struct r600_common_context
*rctx
= (struct r600_common_context
*)context
;
266 struct radeon_encoder
*enc
;
267 struct pipe_video_buffer
*tmp_buf
, templat
= {};
268 struct radeon_surf
*tmp_surf
;
271 enc
= CALLOC_STRUCT(radeon_encoder
);
276 enc
->alignment
= 256;
278 enc
->base
.context
= context
;
279 enc
->base
.destroy
= radeon_enc_destroy
;
280 enc
->base
.begin_frame
= radeon_enc_begin_frame
;
281 enc
->base
.encode_bitstream
= radeon_enc_encode_bitstream
;
282 enc
->base
.end_frame
= radeon_enc_end_frame
;
283 enc
->base
.flush
= radeon_enc_flush
;
284 enc
->base
.get_feedback
= radeon_enc_get_feedback
;
285 enc
->get_buffer
= get_buffer
;
286 enc
->bits_in_shifter
= 0;
287 enc
->screen
= context
->screen
;
289 enc
->cs
= ws
->cs_create(rctx
->ctx
, RING_VCN_ENC
, radeon_enc_cs_flush
, enc
);
292 RVID_ERR("Can't get command submission context.\n");
296 struct rvid_buffer si
;
297 si_vid_create_buffer(enc
->screen
, &si
, 128 * 1024, PIPE_USAGE_STAGING
);
300 templat
.buffer_format
= PIPE_FORMAT_NV12
;
301 templat
.chroma_format
= PIPE_VIDEO_CHROMA_FORMAT_420
;
302 templat
.width
= enc
->base
.width
;
303 templat
.height
= enc
->base
.height
;
304 templat
.interlaced
= false;
306 if (!(tmp_buf
= context
->create_video_buffer(context
, &templat
))) {
307 RVID_ERR("Can't create video buffer.\n");
311 enc
->cpb_num
= get_cpb_num(enc
);
316 get_buffer(((struct vl_video_buffer
*)tmp_buf
)->resources
[0], NULL
, &tmp_surf
);
318 cpb_size
= (sscreen
->info
.chip_class
< GFX9
) ?
319 align(tmp_surf
->u
.legacy
.level
[0].nblk_x
* tmp_surf
->bpe
, 128) *
320 align(tmp_surf
->u
.legacy
.level
[0].nblk_y
, 32) :
321 align(tmp_surf
->u
.gfx9
.surf_pitch
* tmp_surf
->bpe
, 256) *
322 align(tmp_surf
->u
.gfx9
.surf_height
, 32);
324 cpb_size
= cpb_size
* 3 / 2;
325 cpb_size
= cpb_size
* enc
->cpb_num
;
326 tmp_buf
->destroy(tmp_buf
);
328 if (!si_vid_create_buffer(enc
->screen
, &enc
->cpb
, cpb_size
, PIPE_USAGE_DEFAULT
)) {
329 RVID_ERR("Can't create CPB buffer.\n");
333 radeon_enc_1_2_init(enc
);
339 enc
->ws
->cs_destroy(enc
->cs
);
341 si_vid_destroy_buffer(&enc
->cpb
);