src/gallium/drivers/radeon/radeon_vcn_enc.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33 #include "util/u_memory.h"
  34
  35 #include "vl/vl_video_buffer.h"
  36
  37 #include "radeonsi/si_pipe.h"
  38 #include "radeon_video.h"
  39 #include "radeon_vcn_enc.h"
  40
  41 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
  42 {
  43    if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
  44       struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
  45       enc->enc_pic.picture_type = pic->picture_type;
  46       enc->enc_pic.frame_num = pic->frame_num;
  47       enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
  48       enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
  49       enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
  50       enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
  51       enc->enc_pic.not_referenced = pic->not_referenced;
  52       enc->enc_pic.is_idr = (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR);
  53       enc->enc_pic.crop_left = 0;
  54       enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
  55       enc->enc_pic.crop_top = 0;
  56       enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
  57    } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
  58       struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
  59       enc->enc_pic.picture_type = pic->picture_type;
  60       enc->enc_pic.frame_num = pic->frame_num;
  61       enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
  62       enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
  63       enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
  64       enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
  65       enc->enc_pic.not_referenced = pic->not_referenced;
  66       enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
  67                             (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
  68       enc->enc_pic.crop_left = 0;
  69       enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
  70       enc->enc_pic.crop_top = 0;
  71       enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
  72       enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
  73       enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
  74       enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
  75       enc->enc_pic.max_poc = pic->seq.intra_period;
  76       enc->enc_pic.log2_max_poc = 0;
  77       for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
  78          i = (i >> 1);
  79       enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
  80       enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
  81       enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
  82       enc->enc_pic.log2_diff_max_min_luma_coding_block_size = pic->seq.log2_diff_max_min_luma_coding_block_size;
  83       enc->enc_pic.log2_min_transform_block_size_minus2 = pic->seq.log2_min_transform_block_size_minus2;
  84       enc->enc_pic.log2_diff_max_min_transform_block_size = pic->seq.log2_diff_max_min_transform_block_size;
  85       enc->enc_pic.max_transform_hierarchy_depth_inter = pic->seq.max_transform_hierarchy_depth_inter;
  86       enc->enc_pic.max_transform_hierarchy_depth_intra = pic->seq.max_transform_hierarchy_depth_intra;
  87       enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
  88       enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
  89       enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
  90       enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
  91       enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
  92       enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
  93       enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
  94       enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
  95    }
  96 }
  97
  98 static void flush(struct radeon_encoder *enc)
  99 {
 100         enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
 101 }
 102
 103 static void radeon_enc_flush(struct pipe_video_codec *encoder)
 104 {
 105         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 106         flush(enc);
 107 }
 108
 109 static void radeon_enc_cs_flush(void *ctx, unsigned flags,
 110                                                                 struct pipe_fence_handle **fence)
 111 {
 112         // just ignored
 113 }
 114
 115 static unsigned get_cpb_num(struct radeon_encoder *enc)
 116 {
 117         unsigned w = align(enc->base.width, 16) / 16;
 118         unsigned h = align(enc->base.height, 16) / 16;
 119         unsigned dpb;
 120
 121         switch (enc->base.level) {
 122         case 10:
 123                 dpb = 396;
 124                 break;
 125         case 11:
 126                 dpb = 900;
 127                 break;
 128         case 12:
 129         case 13:
 130         case 20:
 131                 dpb = 2376;
 132                 break;
 133         case 21:
 134                 dpb = 4752;
 135                 break;
 136         case 22:
 137         case 30:
 138                 dpb = 8100;
 139                 break;
 140         case 31:
 141                 dpb = 18000;
 142                 break;
 143         case 32:
 144                 dpb = 20480;
 145                 break;
 146         case 40:
 147         case 41:
 148                 dpb = 32768;
 149                 break;
 150         case 42:
 151                 dpb = 34816;
 152                 break;
 153         case 50:
 154                 dpb = 110400;
 155                 break;
 156         default:
 157         case 51:
 158         case 52:
 159                 dpb = 184320;
 160                 break;
 161         }
 162
 163         return MIN2(dpb / (w * h), 16);
 164 }
 165
 166 static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
 167                                                          struct pipe_video_buffer *source,
 168                                                          struct pipe_picture_desc *picture)
 169 {
 170         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 171         struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
 172
 173         radeon_vcn_enc_get_param(enc, picture);
 174
 175         enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
 176         enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
 177
 178         enc->need_feedback = false;
 179
 180         if (!enc->stream_handle) {
 181                 struct rvid_buffer fb;
 182                 enc->stream_handle = si_vid_alloc_stream_handle();
 183                 enc->si = CALLOC_STRUCT(rvid_buffer);
 184                 si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
 185                 si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
 186                 enc->fb = &fb;
 187                 enc->begin(enc, picture);
 188                 flush(enc);
 189                 si_vid_destroy_buffer(&fb);
 190         }
 191 }
 192
 193 static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
 194                                                                   struct pipe_video_buffer *source,
 195                                                                   struct pipe_resource *destination,
 196                                                                   void **fb)
 197 {
 198         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 199         enc->get_buffer(destination, &enc->bs_handle, NULL);
 200         enc->bs_size = destination->width0;
 201
 202         *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
 203
 204         if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
 205                 RVID_ERR("Can't create feedback buffer.\n");
 206                 return;
 207         }
 208
 209         enc->need_feedback = true;
 210         enc->encode(enc);
 211 }
 212
 213 static void radeon_enc_end_frame(struct pipe_video_codec *encoder,
 214                                                    struct pipe_video_buffer *source,
 215                                                    struct pipe_picture_desc *picture)
 216 {
 217         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 218         flush(enc);
 219 }
 220
 221 static void radeon_enc_destroy(struct pipe_video_codec *encoder)
 222 {
 223         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 224
 225         if (enc->stream_handle) {
 226                 struct rvid_buffer fb;
 227                 enc->need_feedback = false;
 228                 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
 229                 enc->fb = &fb;
 230                 enc->destroy(enc);
 231                 flush(enc);
 232                 si_vid_destroy_buffer(&fb);
 233         }
 234
 235         si_vid_destroy_buffer(&enc->cpb);
 236         enc->ws->cs_destroy(enc->cs);
 237         FREE(enc);
 238 }
 239
 240 static void radeon_enc_get_feedback(struct pipe_video_codec *encoder,
 241                                                           void *feedback, unsigned *size)
 242 {
 243         struct radeon_encoder *enc = (struct radeon_encoder*)encoder;
 244         struct rvid_buffer *fb = feedback;
 245
 246         if (size) {
 247                 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
 248                 if (ptr[1])
 249                         *size = ptr[6];
 250                 else
 251                         *size = 0;
 252                 enc->ws->buffer_unmap(fb->res->buf);
 253         }
 254
 255         si_vid_destroy_buffer(fb);
 256         FREE(fb);
 257 }
 258
 259 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 260                 const struct pipe_video_codec *templ,
 261                 struct radeon_winsys* ws,
 262                 radeon_enc_get_buffer get_buffer)
 263 {
 264         struct si_screen *sscreen = (struct si_screen *)context->screen;
 265         struct si_context *sctx = (struct si_context*)context;
 266         struct radeon_encoder *enc;
 267         struct pipe_video_buffer *tmp_buf, templat = {};
 268         struct radeon_surf *tmp_surf;
 269         unsigned cpb_size;
 270
 271         enc = CALLOC_STRUCT(radeon_encoder);
 272
 273         if (!enc)
 274                 return NULL;
 275
 276         enc->alignment = 256;
 277         enc->base = *templ;
 278         enc->base.context = context;
 279         enc->base.destroy = radeon_enc_destroy;
 280         enc->base.begin_frame = radeon_enc_begin_frame;
 281         enc->base.encode_bitstream = radeon_enc_encode_bitstream;
 282         enc->base.end_frame = radeon_enc_end_frame;
 283         enc->base.flush = radeon_enc_flush;
 284         enc->base.get_feedback = radeon_enc_get_feedback;
 285         enc->get_buffer = get_buffer;
 286         enc->bits_in_shifter = 0;
 287         enc->screen = context->screen;
 288         enc->ws = ws;
 289         enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc);
 290
 291         if (!enc->cs) {
 292                 RVID_ERR("Can't get command submission context.\n");
 293                 goto error;
 294         }
 295
 296         struct rvid_buffer si;
 297         si_vid_create_buffer(enc->screen, &si, 128 * 1024, PIPE_USAGE_STAGING);
 298         enc->si = &si;
 299
 300         templat.buffer_format = PIPE_FORMAT_NV12;
 301         templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
 302         templat.width = enc->base.width;
 303         templat.height = enc->base.height;
 304         templat.interlaced = false;
 305
 306         if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
 307                 RVID_ERR("Can't create video buffer.\n");
 308                 goto error;
 309         }
 310
 311         enc->cpb_num = get_cpb_num(enc);
 312
 313         if (!enc->cpb_num)
 314                 goto error;
 315
 316         get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
 317
 318         cpb_size = (sscreen->info.chip_class < GFX9) ?
 319                            align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
 320                            align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
 321                            align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
 322                            align(tmp_surf->u.gfx9.surf_height, 32);
 323
 324         cpb_size = cpb_size * 3 / 2;
 325         cpb_size = cpb_size * enc->cpb_num;
 326         tmp_buf->destroy(tmp_buf);
 327
 328         if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
 329                 RVID_ERR("Can't create CPB buffer.\n");
 330                 goto error;
 331         }
 332
 333         radeon_enc_1_2_init(enc);
 334
 335         return &enc->base;
 336
 337 error:
 338         if (enc->cs)
 339                 enc->ws->cs_destroy(enc->cs);
 340
 341         si_vid_destroy_buffer(&enc->cpb);
 342
 343         FREE(enc);
 344         return NULL;
 345 }