1 /**************************************************************************
3 * Copyright 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef _RADEON_VCN_ENC_H
29 #define _RADEON_VCN_ENC_H
31 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
32 #define RENCODE_FW_INTERFACE_MINOR_VERSION 2
34 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
35 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
36 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
37 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
38 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
39 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
40 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
41 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
42 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
43 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
44 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
45 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
46 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
47 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
48 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
49 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
51 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
52 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
53 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
55 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
56 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
57 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
58 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
60 #define RENCODE_IB_OP_INITIALIZE 0x01000001
61 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002
62 #define RENCODE_IB_OP_ENCODE 0x01000003
63 #define RENCODE_IB_OP_INIT_RC 0x01000004
64 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005
65 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006
66 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007
67 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008
69 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000
70 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16
71 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF
72 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
74 #define RENCODE_ENCODE_STANDARD_HEVC 0
75 #define RENCODE_ENCODE_STANDARD_H264 1
77 #define RENCODE_PREENCODE_MODE_NONE 0x00000000
78 #define RENCODE_PREENCODE_MODE_1X 0x00000001
79 #define RENCODE_PREENCODE_MODE_2X 0x00000002
80 #define RENCODE_PREENCODE_MODE_4X 0x00000004
82 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
83 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
85 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
86 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
88 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
89 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
90 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
91 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003
93 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000
94 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001
95 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002
96 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003
97 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004
98 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005
100 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
101 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
103 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000
104 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001
106 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000
107 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001
108 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002
109 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
111 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000
112 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
114 #define RENCODE_PICTURE_TYPE_B 0
115 #define RENCODE_PICTURE_TYPE_P 1
116 #define RENCODE_PICTURE_TYPE_I 2
117 #define RENCODE_PICTURE_TYPE_P_SKIP 3
119 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0
120 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1
121 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5
122 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9
124 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0
125 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1
126 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2
128 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0
129 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1
130 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2
132 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
133 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
134 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
136 #define RENCODE_INTRA_REFRESH_MODE_NONE 0
137 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
138 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
140 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34
142 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0
143 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1
145 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
146 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
148 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0
149 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
151 typedef struct rvcn_enc_session_info_s
153 uint32_t interface_version
;
154 uint32_t sw_context_address_hi
;
155 uint32_t sw_context_address_lo
;
156 } rvcn_enc_session_info_t
;
158 typedef struct rvcn_enc_task_info_s
160 uint32_t total_size_of_all_packages
;
162 uint32_t allowed_max_num_feedbacks
;
163 } rvcn_enc_task_info_t
;
165 typedef struct rvcn_enc_session_init_s
167 uint32_t encode_standard
;
168 uint32_t aligned_picture_width
;
169 uint32_t aligned_picture_height
;
170 uint32_t padding_width
;
171 uint32_t padding_height
;
172 uint32_t pre_encode_mode
;
173 uint32_t pre_encode_chroma_enabled
;
174 } rvcn_enc_session_init_t
;
176 typedef struct rvcn_enc_layer_control_s
178 uint32_t max_num_temporal_layers
;
179 uint32_t num_temporal_layers
;
180 } rvcn_enc_layer_control_t
;
182 typedef struct rvcn_enc_layer_select_s
184 uint32_t temporal_layer_index
;
185 } rvcn_enc_layer_select_t
;
187 typedef struct rvcn_enc_h264_slice_control_s
189 uint32_t slice_control_mode
;
192 uint32_t num_mbs_per_slice
;
193 uint32_t num_bits_per_slice
;
195 } rvcn_enc_h264_slice_control_t
;
197 typedef struct rvcn_enc_hevc_slice_control_s
199 uint32_t slice_control_mode
;
204 uint32_t num_ctbs_per_slice
;
205 uint32_t num_ctbs_per_slice_segment
;
206 } fixed_ctbs_per_slice
;
210 uint32_t num_bits_per_slice
;
211 uint32_t num_bits_per_slice_segment
;
212 } fixed_bits_per_slice
;
214 } rvcn_enc_hevc_slice_control_t
;
216 typedef struct rvcn_enc_h264_spec_misc_s
218 uint32_t constrained_intra_pred_flag
;
219 uint32_t cabac_enable
;
220 uint32_t cabac_init_idc
;
221 uint32_t half_pel_enabled
;
222 uint32_t quarter_pel_enabled
;
223 uint32_t profile_idc
;
225 } rvcn_enc_h264_spec_misc_t
;
227 typedef struct rvcn_enc_hevc_spec_misc_s
229 uint32_t log2_min_luma_coding_block_size_minus3
;
230 uint32_t amp_disabled
;
231 uint32_t strong_intra_smoothing_enabled
;
232 uint32_t constrained_intra_pred_flag
;
233 uint32_t cabac_init_flag
;
234 uint32_t half_pel_enabled
;
235 uint32_t quarter_pel_enabled
;
236 } rvcn_enc_hevc_spec_misc_t
;
238 typedef struct rvcn_enc_rate_ctl_session_init_s
240 uint32_t rate_control_method
;
241 uint32_t vbv_buffer_level
;
242 } rvcn_enc_rate_ctl_session_init_t
;
244 typedef struct rvcn_enc_rate_ctl_layer_init_s
246 uint32_t target_bit_rate
;
247 uint32_t peak_bit_rate
;
248 uint32_t frame_rate_num
;
249 uint32_t frame_rate_den
;
250 uint32_t vbv_buffer_size
;
251 uint32_t avg_target_bits_per_picture
;
252 uint32_t peak_bits_per_picture_integer
;
253 uint32_t peak_bits_per_picture_fractional
;
254 } rvcn_enc_rate_ctl_layer_init_t
;
256 typedef struct rvcn_enc_rate_ctl_per_picture_s
261 uint32_t max_au_size
;
262 uint32_t enabled_filler_data
;
263 uint32_t skip_frame_enable
;
264 uint32_t enforce_hrd
;
265 } rvcn_enc_rate_ctl_per_picture_t
;
267 typedef struct rvcn_enc_quality_params_s
270 uint32_t scene_change_sensitivity
;
271 uint32_t scene_change_min_idr_interval
;
272 } rvcn_enc_quality_params_t
;
274 typedef struct rvcn_enc_direct_output_nalu_s
279 } rvcn_enc_direct_output_nalu_t
;
281 typedef struct rvcn_enc_slice_header_s
283 uint32_t bitstream_template
[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS
];
285 uint32_t instruction
;
287 } instructions
[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS
];
288 } rvcn_enc_slice_header_t
;
290 typedef struct rvcn_enc_encode_params_s
293 uint32_t allowed_max_bitstream_size
;
294 uint32_t input_picture_luma_address_hi
;
295 uint32_t input_picture_luma_address_lo
;
296 uint32_t input_picture_chroma_address_hi
;
297 uint32_t input_picture_chroma_address_lo
;
298 uint32_t input_pic_luma_pitch
;
299 uint32_t input_pic_chroma_pitch
;
300 uint8_t input_pic_swizzle_mode
;
301 uint32_t reference_picture_index
;
302 uint32_t reconstructed_picture_index
;
303 } rvcn_enc_encode_params_t
;
305 typedef struct rvcn_enc_h264_encode_params_s
307 uint32_t input_picture_structure
;
308 uint32_t interlaced_mode
;
309 uint32_t reference_picture_structure
;
310 uint32_t reference_picture1_index
;
311 } rvcn_enc_h264_encode_params_t
;
313 typedef struct rvcn_enc_h264_deblocking_filter_s
315 uint32_t disable_deblocking_filter_idc
;
316 int32_t alpha_c0_offset_div2
;
317 int32_t beta_offset_div2
;
318 int32_t cb_qp_offset
;
319 int32_t cr_qp_offset
;
320 } rvcn_enc_h264_deblocking_filter_t
;
322 typedef struct rvcn_enc_hevc_deblocking_filter_s
324 uint32_t loop_filter_across_slices_enabled
;
325 int32_t deblocking_filter_disabled
;
326 int32_t beta_offset_div2
;
327 int32_t tc_offset_div2
;
328 int32_t cb_qp_offset
;
329 int32_t cr_qp_offset
;
330 } rvcn_enc_hevc_deblocking_filter_t
;
332 typedef struct rvcn_enc_intra_refresh_s
334 uint32_t intra_refresh_mode
;
336 uint32_t region_size
;
337 } rvcn_enc_intra_refresh_t
;
339 typedef struct rvcn_enc_reconstructed_picture_s
341 uint32_t luma_offset
;
342 uint32_t chroma_offset
;
343 } rvcn_enc_reconstructed_picture_t
;
345 typedef struct rvcn_enc_encode_context_buffer_s
347 uint32_t encode_context_address_hi
;
348 uint32_t encode_context_address_lo
;
349 uint32_t swizzle_mode
;
350 uint32_t rec_luma_pitch
;
351 uint32_t rec_chroma_pitch
;
352 uint32_t num_reconstructed_pictures
;
353 rvcn_enc_reconstructed_picture_t reconstructed_pictures
[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES
];
354 uint32_t pre_encode_picture_luma_pitch
;
355 uint32_t pre_encode_picture_chroma_pitch
;
356 rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures
[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES
];
357 rvcn_enc_reconstructed_picture_t pre_encode_input_picture
;
358 } rvcn_enc_encode_context_buffer_t
;
360 typedef struct rvcn_enc_video_bitstream_buffer_s
363 uint32_t video_bitstream_buffer_address_hi
;
364 uint32_t video_bitstream_buffer_address_lo
;
365 uint32_t video_bitstream_buffer_size
;
366 uint32_t video_bitstream_data_offset
;
367 } rvcn_enc_video_bitstream_buffer_t
;
369 typedef struct rvcn_enc_feedback_buffer_s
372 uint32_t feedback_buffer_address_hi
;
373 uint32_t feedback_buffer_address_lo
;
374 uint32_t feedback_buffer_size
;
375 uint32_t feedback_data_size
;
376 } rvcn_enc_feedback_buffer_t
;
378 typedef void (*radeon_enc_get_buffer
)(struct pipe_resource
*resource
,
379 struct pb_buffer
**handle
,
380 struct radeon_surf
**surface
);
382 struct pipe_video_codec
*radeon_create_encoder(struct pipe_context
*context
,
383 const struct pipe_video_codec
*templat
,
384 struct radeon_winsys
* ws
,
385 radeon_enc_get_buffer get_buffer
);
387 struct radeon_enc_pic
{
388 enum pipe_h264_enc_picture_type picture_type
;
391 unsigned pic_order_cnt
;
392 unsigned pic_order_cnt_type
;
398 unsigned crop_bottom
;
399 unsigned general_tier_flag
;
400 unsigned general_profile_idc
;
401 unsigned general_level_idc
;
403 unsigned log2_max_poc
;
404 unsigned chroma_format_idc
;
405 unsigned pic_width_in_luma_samples
;
406 unsigned pic_height_in_luma_samples
;
407 unsigned log2_diff_max_min_luma_coding_block_size
;
408 unsigned log2_min_transform_block_size_minus2
;
409 unsigned log2_diff_max_min_transform_block_size
;
410 unsigned max_transform_hierarchy_depth_inter
;
411 unsigned max_transform_hierarchy_depth_intra
;
412 unsigned log2_parallel_merge_level_minus2
;
413 unsigned bit_depth_luma_minus8
;
414 unsigned bit_depth_chroma_minus8
;
415 unsigned nal_unit_type
;
416 unsigned max_num_merge_cand
;
421 bool sample_adaptive_offset_enabled_flag
;
422 bool pcm_enabled_flag
;
423 bool sps_temporal_mvp_enabled_flag
;
425 rvcn_enc_task_info_t task_info
;
426 rvcn_enc_session_init_t session_init
;
427 rvcn_enc_layer_control_t layer_ctrl
;
428 rvcn_enc_layer_select_t layer_sel
;
429 rvcn_enc_h264_slice_control_t slice_ctrl
;
430 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl
;
431 rvcn_enc_h264_spec_misc_t spec_misc
;
432 rvcn_enc_hevc_spec_misc_t hevc_spec_misc
;
433 rvcn_enc_rate_ctl_session_init_t rc_session_init
;
434 rvcn_enc_rate_ctl_layer_init_t rc_layer_init
;
435 rvcn_enc_h264_encode_params_t h264_enc_params
;
436 rvcn_enc_h264_deblocking_filter_t h264_deblock
;
437 rvcn_enc_hevc_deblocking_filter_t hevc_deblock
;
438 rvcn_enc_rate_ctl_per_picture_t rc_per_pic
;
439 rvcn_enc_quality_params_t quality_params
;
440 rvcn_enc_encode_context_buffer_t ctx_buf
;
441 rvcn_enc_video_bitstream_buffer_t bit_buf
;
442 rvcn_enc_feedback_buffer_t fb_buf
;
443 rvcn_enc_intra_refresh_t intra_ref
;
444 rvcn_enc_encode_params_t enc_params
;
447 struct radeon_encoder
{
448 struct pipe_video_codec base
;
450 void (*begin
)(struct radeon_encoder
*enc
, struct pipe_picture_desc
*pic
);
451 void (*encode
)(struct radeon_encoder
*enc
);
452 void (*destroy
)(struct radeon_encoder
*enc
);
454 unsigned stream_handle
;
456 struct pipe_screen
*screen
;
457 struct radeon_winsys
* ws
;
458 struct radeon_cmdbuf
* cs
;
460 radeon_enc_get_buffer get_buffer
;
462 struct pb_buffer
* handle
;
463 struct radeon_surf
* luma
;
464 struct radeon_surf
* chroma
;
466 struct pb_buffer
* bs_handle
;
471 struct rvid_buffer
*si
;
472 struct rvid_buffer
*fb
;
473 struct rvid_buffer cpb
;
474 struct radeon_enc_pic enc_pic
;
478 unsigned bits_in_shifter
;
481 unsigned bits_output
;
482 uint32_t total_task_size
;
483 uint32_t* p_task_size
;
485 bool emulation_prevention
;
489 void radeon_enc_1_2_init(struct radeon_encoder
*enc
);
491 #endif // _RADEON_VCN_ENC_H