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[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_enc.h
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef _RADEON_VCN_ENC_H
29 #define _RADEON_VCN_ENC_H
30
31 #define RENCODE_IB_OP_INITIALIZE 0x01000001
32 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002
33 #define RENCODE_IB_OP_ENCODE 0x01000003
34 #define RENCODE_IB_OP_INIT_RC 0x01000004
35 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005
36 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006
37 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007
38 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008
39
40 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000
41 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16
42 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF
43 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
44
45 #define RENCODE_ENGINE_TYPE_ENCODE 1
46
47 #define RENCODE_ENCODE_STANDARD_HEVC 0
48 #define RENCODE_ENCODE_STANDARD_H264 1
49
50 #define RENCODE_PREENCODE_MODE_NONE 0x00000000
51 #define RENCODE_PREENCODE_MODE_1X 0x00000001
52 #define RENCODE_PREENCODE_MODE_2X 0x00000002
53 #define RENCODE_PREENCODE_MODE_4X 0x00000004
54
55 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
56 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
57
58 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
59 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
60
61 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
62 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
63 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
64 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003
65
66 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000
67 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001
68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002
69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003
70 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004
71 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005
72
73 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
74 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
75
76 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000
77 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001
78
79 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000
80 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001
81 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002
82 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
83
84 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000
85 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
86
87 #define RENCODE_PICTURE_TYPE_B 0
88 #define RENCODE_PICTURE_TYPE_P 1
89 #define RENCODE_PICTURE_TYPE_I 2
90 #define RENCODE_PICTURE_TYPE_P_SKIP 3
91
92 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0
93 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1
94 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5
95 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9
96
97 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0
98 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1
99 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2
100
101 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0
102 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1
103 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2
104
105 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
106 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
107 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
108
109 #define RENCODE_INTRA_REFRESH_MODE_NONE 0
110 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
111 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
112
113 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34
114
115 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0
116 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1
117
118 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
119 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
120
121 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0
122 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
123
124 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
125 #define RADEON_ENC_BEGIN(cmd) { \
126 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
127 RADEON_ENC_CS(cmd)
128 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
129 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
130 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
131 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
132 enc->total_task_size += *begin;}
133
134 typedef struct rvcn_enc_session_info_s
135 {
136 uint32_t interface_version;
137 uint32_t sw_context_address_hi;
138 uint32_t sw_context_address_lo;
139 } rvcn_enc_session_info_t;
140
141 typedef struct rvcn_enc_task_info_s
142 {
143 uint32_t total_size_of_all_packages;
144 uint32_t task_id;
145 uint32_t allowed_max_num_feedbacks;
146 } rvcn_enc_task_info_t;
147
148 typedef struct rvcn_enc_session_init_s
149 {
150 uint32_t encode_standard;
151 uint32_t aligned_picture_width;
152 uint32_t aligned_picture_height;
153 uint32_t padding_width;
154 uint32_t padding_height;
155 uint32_t pre_encode_mode;
156 uint32_t pre_encode_chroma_enabled;
157 } rvcn_enc_session_init_t;
158
159 typedef struct rvcn_enc_layer_control_s
160 {
161 uint32_t max_num_temporal_layers;
162 uint32_t num_temporal_layers;
163 } rvcn_enc_layer_control_t;
164
165 typedef struct rvcn_enc_layer_select_s
166 {
167 uint32_t temporal_layer_index;
168 } rvcn_enc_layer_select_t;
169
170 typedef struct rvcn_enc_h264_slice_control_s
171 {
172 uint32_t slice_control_mode;
173 union
174 {
175 uint32_t num_mbs_per_slice;
176 uint32_t num_bits_per_slice;
177 };
178 } rvcn_enc_h264_slice_control_t;
179
180 typedef struct rvcn_enc_hevc_slice_control_s
181 {
182 uint32_t slice_control_mode;
183 union
184 {
185 struct
186 {
187 uint32_t num_ctbs_per_slice;
188 uint32_t num_ctbs_per_slice_segment;
189 } fixed_ctbs_per_slice;
190
191 struct
192 {
193 uint32_t num_bits_per_slice;
194 uint32_t num_bits_per_slice_segment;
195 } fixed_bits_per_slice;
196 };
197 } rvcn_enc_hevc_slice_control_t;
198
199 typedef struct rvcn_enc_h264_spec_misc_s
200 {
201 uint32_t constrained_intra_pred_flag;
202 uint32_t cabac_enable;
203 uint32_t cabac_init_idc;
204 uint32_t half_pel_enabled;
205 uint32_t quarter_pel_enabled;
206 uint32_t profile_idc;
207 uint32_t level_idc;
208 } rvcn_enc_h264_spec_misc_t;
209
210 typedef struct rvcn_enc_hevc_spec_misc_s
211 {
212 uint32_t log2_min_luma_coding_block_size_minus3;
213 uint32_t amp_disabled;
214 uint32_t strong_intra_smoothing_enabled;
215 uint32_t constrained_intra_pred_flag;
216 uint32_t cabac_init_flag;
217 uint32_t half_pel_enabled;
218 uint32_t quarter_pel_enabled;
219 } rvcn_enc_hevc_spec_misc_t;
220
221 typedef struct rvcn_enc_rate_ctl_session_init_s
222 {
223 uint32_t rate_control_method;
224 uint32_t vbv_buffer_level;
225 } rvcn_enc_rate_ctl_session_init_t;
226
227 typedef struct rvcn_enc_rate_ctl_layer_init_s
228 {
229 uint32_t target_bit_rate;
230 uint32_t peak_bit_rate;
231 uint32_t frame_rate_num;
232 uint32_t frame_rate_den;
233 uint32_t vbv_buffer_size;
234 uint32_t avg_target_bits_per_picture;
235 uint32_t peak_bits_per_picture_integer;
236 uint32_t peak_bits_per_picture_fractional;
237 } rvcn_enc_rate_ctl_layer_init_t;
238
239 typedef struct rvcn_enc_rate_ctl_per_picture_s
240 {
241 uint32_t qp;
242 uint32_t min_qp_app;
243 uint32_t max_qp_app;
244 uint32_t max_au_size;
245 uint32_t enabled_filler_data;
246 uint32_t skip_frame_enable;
247 uint32_t enforce_hrd;
248 } rvcn_enc_rate_ctl_per_picture_t;
249
250 typedef struct rvcn_enc_quality_params_s
251 {
252 uint32_t vbaq_mode;
253 uint32_t scene_change_sensitivity;
254 uint32_t scene_change_min_idr_interval;
255 uint32_t two_pass_search_center_map_mode;
256 } rvcn_enc_quality_params_t;
257
258 typedef struct rvcn_enc_direct_output_nalu_s
259 {
260 uint32_t type;
261 uint32_t size;
262 uint32_t data[1];
263 } rvcn_enc_direct_output_nalu_t;
264
265 typedef struct rvcn_enc_slice_header_s
266 {
267 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
268 struct {
269 uint32_t instruction;
270 uint32_t num_bits;
271 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
272 } rvcn_enc_slice_header_t;
273
274 typedef struct rvcn_enc_encode_params_s
275 {
276 uint32_t pic_type;
277 uint32_t allowed_max_bitstream_size;
278 uint32_t input_picture_luma_address_hi;
279 uint32_t input_picture_luma_address_lo;
280 uint32_t input_picture_chroma_address_hi;
281 uint32_t input_picture_chroma_address_lo;
282 uint32_t input_pic_luma_pitch;
283 uint32_t input_pic_chroma_pitch;
284 uint8_t input_pic_swizzle_mode;
285 uint32_t reference_picture_index;
286 uint32_t reconstructed_picture_index;
287 } rvcn_enc_encode_params_t;
288
289 typedef struct rvcn_enc_h264_encode_params_s
290 {
291 uint32_t input_picture_structure;
292 uint32_t interlaced_mode;
293 uint32_t reference_picture_structure;
294 uint32_t reference_picture1_index;
295 } rvcn_enc_h264_encode_params_t;
296
297 typedef struct rvcn_enc_h264_deblocking_filter_s
298 {
299 uint32_t disable_deblocking_filter_idc;
300 int32_t alpha_c0_offset_div2;
301 int32_t beta_offset_div2;
302 int32_t cb_qp_offset;
303 int32_t cr_qp_offset;
304 } rvcn_enc_h264_deblocking_filter_t;
305
306 typedef struct rvcn_enc_hevc_deblocking_filter_s
307 {
308 uint32_t loop_filter_across_slices_enabled;
309 int32_t deblocking_filter_disabled;
310 int32_t beta_offset_div2;
311 int32_t tc_offset_div2;
312 int32_t cb_qp_offset;
313 int32_t cr_qp_offset;
314 } rvcn_enc_hevc_deblocking_filter_t;
315
316 typedef struct rvcn_enc_intra_refresh_s
317 {
318 uint32_t intra_refresh_mode;
319 uint32_t offset;
320 uint32_t region_size;
321 } rvcn_enc_intra_refresh_t;
322
323 typedef struct rvcn_enc_reconstructed_picture_s
324 {
325 uint32_t luma_offset;
326 uint32_t chroma_offset;
327 } rvcn_enc_reconstructed_picture_t;
328
329 typedef struct rvcn_enc_encode_context_buffer_s
330 {
331 uint32_t encode_context_address_hi;
332 uint32_t encode_context_address_lo;
333 uint32_t swizzle_mode;
334 uint32_t rec_luma_pitch;
335 uint32_t rec_chroma_pitch;
336 uint32_t num_reconstructed_pictures;
337 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
338 uint32_t pre_encode_picture_luma_pitch;
339 uint32_t pre_encode_picture_chroma_pitch;
340 rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
341 rvcn_enc_reconstructed_picture_t pre_encode_input_picture;
342 } rvcn_enc_encode_context_buffer_t;
343
344 typedef struct rvcn_enc_video_bitstream_buffer_s
345 {
346 uint32_t mode;
347 uint32_t video_bitstream_buffer_address_hi;
348 uint32_t video_bitstream_buffer_address_lo;
349 uint32_t video_bitstream_buffer_size;
350 uint32_t video_bitstream_data_offset;
351 } rvcn_enc_video_bitstream_buffer_t;
352
353 typedef struct rvcn_enc_feedback_buffer_s
354 {
355 uint32_t mode;
356 uint32_t feedback_buffer_address_hi;
357 uint32_t feedback_buffer_address_lo;
358 uint32_t feedback_buffer_size;
359 uint32_t feedback_data_size;
360 } rvcn_enc_feedback_buffer_t;
361
362 typedef struct rvcn_enc_cmd_s
363 {
364 uint32_t session_info;
365 uint32_t task_info;
366 uint32_t session_init;
367 uint32_t layer_control;
368 uint32_t layer_select;
369 uint32_t rc_session_init;
370 uint32_t rc_layer_init;
371 uint32_t rc_per_pic;
372 uint32_t quality_params;
373 uint32_t slice_header;
374 uint32_t enc_params;
375 uint32_t intra_refresh;
376 uint32_t ctx;
377 uint32_t bitstream;
378 uint32_t feedback;
379 uint32_t nalu;
380 uint32_t slice_control_hevc;
381 uint32_t spec_misc_hevc;
382 uint32_t enc_params_hevc;
383 uint32_t deblocking_filter_hevc;
384 uint32_t slice_control_h264;
385 uint32_t spec_misc_h264;
386 uint32_t enc_params_h264;
387 uint32_t deblocking_filter_h264;
388 uint32_t input_format;
389 uint32_t output_format;
390 } rvcn_enc_cmd_t;
391
392 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource,
393 struct pb_buffer **handle,
394 struct radeon_surf **surface);
395
396 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
397 const struct pipe_video_codec *templat,
398 struct radeon_winsys* ws,
399 radeon_enc_get_buffer get_buffer);
400
401 struct radeon_enc_pic {
402 enum pipe_h264_enc_picture_type picture_type;
403
404 unsigned frame_num;
405 unsigned pic_order_cnt;
406 unsigned pic_order_cnt_type;
407 unsigned ref_idx_l0;
408 unsigned ref_idx_l1;
409 unsigned crop_left;
410 unsigned crop_right;
411 unsigned crop_top;
412 unsigned crop_bottom;
413 unsigned general_tier_flag;
414 unsigned general_profile_idc;
415 unsigned general_level_idc;
416 unsigned max_poc;
417 unsigned log2_max_poc;
418 unsigned chroma_format_idc;
419 unsigned pic_width_in_luma_samples;
420 unsigned pic_height_in_luma_samples;
421 unsigned log2_diff_max_min_luma_coding_block_size;
422 unsigned log2_min_transform_block_size_minus2;
423 unsigned log2_diff_max_min_transform_block_size;
424 unsigned max_transform_hierarchy_depth_inter;
425 unsigned max_transform_hierarchy_depth_intra;
426 unsigned log2_parallel_merge_level_minus2;
427 unsigned bit_depth_luma_minus8;
428 unsigned bit_depth_chroma_minus8;
429 unsigned nal_unit_type;
430 unsigned max_num_merge_cand;
431
432 bool not_referenced;
433 bool is_idr;
434 bool is_even_frame;
435 bool sample_adaptive_offset_enabled_flag;
436 bool pcm_enabled_flag;
437 bool sps_temporal_mvp_enabled_flag;
438
439 rvcn_enc_session_info_t session_info;
440 rvcn_enc_task_info_t task_info;
441 rvcn_enc_session_init_t session_init;
442 rvcn_enc_layer_control_t layer_ctrl;
443 rvcn_enc_layer_select_t layer_sel;
444 rvcn_enc_h264_slice_control_t slice_ctrl;
445 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl;
446 rvcn_enc_h264_spec_misc_t spec_misc;
447 rvcn_enc_hevc_spec_misc_t hevc_spec_misc;
448 rvcn_enc_rate_ctl_session_init_t rc_session_init;
449 rvcn_enc_rate_ctl_layer_init_t rc_layer_init;
450 rvcn_enc_h264_encode_params_t h264_enc_params;
451 rvcn_enc_h264_deblocking_filter_t h264_deblock;
452 rvcn_enc_hevc_deblocking_filter_t hevc_deblock;
453 rvcn_enc_rate_ctl_per_picture_t rc_per_pic;
454 rvcn_enc_quality_params_t quality_params;
455 rvcn_enc_encode_context_buffer_t ctx_buf;
456 rvcn_enc_video_bitstream_buffer_t bit_buf;
457 rvcn_enc_feedback_buffer_t fb_buf;
458 rvcn_enc_intra_refresh_t intra_ref;
459 rvcn_enc_encode_params_t enc_params;
460 };
461
462 struct radeon_encoder {
463 struct pipe_video_codec base;
464
465 void (*begin)(struct radeon_encoder *enc);
466 void (*encode)(struct radeon_encoder *enc);
467 void (*destroy)(struct radeon_encoder *enc);
468 void (*session_info)(struct radeon_encoder *enc);
469 void (*task_info)(struct radeon_encoder *enc, bool need_feedback);
470 void (*session_init)(struct radeon_encoder *enc);
471 void (*layer_control)(struct radeon_encoder *enc);
472 void (*layer_select)(struct radeon_encoder *enc);
473 void (*slice_control)(struct radeon_encoder *enc);
474 void (*spec_misc)(struct radeon_encoder *enc);
475 void (*rc_session_init)(struct radeon_encoder *enc);
476 void (*rc_layer_init)(struct radeon_encoder *enc);
477 void (*deblocking_filter)(struct radeon_encoder *enc);
478 void (*quality_params)(struct radeon_encoder *enc);
479 void (*nalu_sps)(struct radeon_encoder *enc);
480 void (*nalu_pps)(struct radeon_encoder *enc);
481 void (*nalu_vps)(struct radeon_encoder *enc);
482 void (*nalu_aud)(struct radeon_encoder *enc);
483 void (*slice_header)(struct radeon_encoder *enc);
484 void (*ctx)(struct radeon_encoder *enc);
485 void (*bitstream)(struct radeon_encoder *enc);
486 void (*feedback)(struct radeon_encoder *enc);
487 void (*intra_refresh)(struct radeon_encoder *enc);
488 void (*rc_per_pic)(struct radeon_encoder *enc);
489 void (*encode_params)(struct radeon_encoder *enc);
490 void (*encode_params_codec_spec)(struct radeon_encoder *enc);
491 void (*op_init)(struct radeon_encoder *enc);
492 void (*op_close)(struct radeon_encoder *enc);
493 void (*op_enc)(struct radeon_encoder *enc);
494 void (*op_init_rc)(struct radeon_encoder *enc);
495 void (*op_init_rc_vbv)(struct radeon_encoder *enc);
496 void (*op_speed)(struct radeon_encoder *enc);
497 void (*encode_headers)(struct radeon_encoder *enc);
498 void (*input_format)(struct radeon_encoder *enc);
499 void (*output_format)(struct radeon_encoder *enc);
500
501 unsigned stream_handle;
502
503 struct pipe_screen *screen;
504 struct radeon_winsys* ws;
505 struct radeon_cmdbuf* cs;
506
507 radeon_enc_get_buffer get_buffer;
508
509 struct pb_buffer* handle;
510 struct radeon_surf* luma;
511 struct radeon_surf* chroma;
512
513 struct pb_buffer* bs_handle;
514 unsigned bs_size;
515
516 unsigned cpb_num;
517
518 struct rvid_buffer *si;
519 struct rvid_buffer *fb;
520 struct rvid_buffer cpb;
521 struct radeon_enc_pic enc_pic;
522 rvcn_enc_cmd_t cmd;
523
524 unsigned alignment;
525 unsigned shifter;
526 unsigned bits_in_shifter;
527 unsigned num_zeros;
528 unsigned byte_index;
529 unsigned bits_output;
530 uint32_t total_task_size;
531 uint32_t* p_task_size;
532
533 bool emulation_prevention;
534 bool need_feedback;
535 };
536
537 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
538 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
539 signed offset);
540
541 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
542
543 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
544
545 void radeon_enc_emulation_prevention(struct radeon_encoder *enc,
546 unsigned char byte);
547
548 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
549 unsigned int num_bits);
550
551 void radeon_enc_reset(struct radeon_encoder *enc);
552
553 void radeon_enc_byte_align(struct radeon_encoder *enc);
554
555 void radeon_enc_flush_headers(struct radeon_encoder *enc);
556
557 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value);
558
559 void radeon_enc_code_se(struct radeon_encoder *enc, int value);
560
561 void radeon_enc_1_2_init(struct radeon_encoder *enc);
562
563 void radeon_enc_2_0_init(struct radeon_encoder *enc);
564
565 #endif // _RADEON_VCN_ENC_H