src/gallium/drivers/radeon/radeon_vcn_enc.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef _RADEON_VCN_ENC_H
  29 #define _RADEON_VCN_ENC_H
  30
  31 #include "radeon_video.h"
  32
  33 #define RENCODE_IB_OP_INITIALIZE                                                    0x01000001
  34 #define RENCODE_IB_OP_CLOSE_SESSION                                                 0x01000002
  35 #define RENCODE_IB_OP_ENCODE                                                        0x01000003
  36 #define RENCODE_IB_OP_INIT_RC                                                       0x01000004
  37 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL                                      0x01000005
  38 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE                                       0x01000006
  39 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE                                     0x01000007
  40 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE                                     0x01000008
  41
  42 #define RENCODE_IF_MAJOR_VERSION_MASK                                               0xFFFF0000
  43 #define RENCODE_IF_MAJOR_VERSION_SHIFT                                              16
  44 #define RENCODE_IF_MINOR_VERSION_MASK                                               0x0000FFFF
  45 #define RENCODE_IF_MINOR_VERSION_SHIFT                                              0
  46
  47 #define RENCODE_ENGINE_TYPE_ENCODE                                                  1
  48
  49 #define RENCODE_ENCODE_STANDARD_HEVC                                                0
  50 #define RENCODE_ENCODE_STANDARD_H264                                                1
  51
  52 #define RENCODE_PREENCODE_MODE_NONE                                                 0x00000000
  53 #define RENCODE_PREENCODE_MODE_1X                                                   0x00000001
  54 #define RENCODE_PREENCODE_MODE_2X                                                   0x00000002
  55 #define RENCODE_PREENCODE_MODE_4X                                                   0x00000004
  56
  57 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS                                   0x00000000
  58 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS                                  0x00000001
  59
  60 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS                                  0x00000000
  61 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS                                  0x00000001
  62
  63 #define RENCODE_RATE_CONTROL_METHOD_NONE                                            0x00000000
  64 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR                         0x00000001
  65 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR                            0x00000002
  66 #define RENCODE_RATE_CONTROL_METHOD_CBR                                             0x00000003
  67
  68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD                                         0x00000000
  69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS                                         0x00000001
  70 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS                                         0x00000002
  71 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS                                         0x00000003
  72 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX                                      0x00000004
  73 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE                             0x00000005
  74
  75 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS                   16
  76 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS                          16
  77
  78 #define RENCODE_HEADER_INSTRUCTION_END                                              0x00000000
  79 #define RENCODE_HEADER_INSTRUCTION_COPY                                             0x00000001
  80
  81 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END                         0x00010000
  82 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE                                 0x00010001
  83 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT                               0x00010002
  84 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA                              0x00010003
  85
  86 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB                                    0x00020000
  87 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA                              0x00020001
  88
  89 #define RENCODE_PICTURE_TYPE_B                                                      0
  90 #define RENCODE_PICTURE_TYPE_P                                                      1
  91 #define RENCODE_PICTURE_TYPE_I                                                      2
  92 #define RENCODE_PICTURE_TYPE_P_SKIP                                                 3
  93
  94 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR                                           0
  95 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S                                           1
  96 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S                                            5
  97 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S                                           9
  98
  99 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME                                        0
 100 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD                                    1
 101 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD                                 2
 102
 103 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE                                   0
 104 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED                            1
 105 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED                        2
 106
 107 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE                           0
 108 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE                          1
 109 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY    2
 110
 111 #define RENCODE_INTRA_REFRESH_MODE_NONE                                             0
 112 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS                                      1
 113 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS                                   2
 114
 115 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES                                      34
 116
 117 #define RENCODE_REC_SWIZZLE_MODE_LINEAR                                             0
 118 #define RENCODE_REC_SWIZZLE_MODE_256B_S                                             1
 119
 120 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR                                  0
 121 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR                                1
 122
 123 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR                                         0
 124 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR                                       1
 125
 126 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
 127 #define RADEON_ENC_BEGIN(cmd)                                                                      \
 128    {                                                                                               \
 129       uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++];                             \
 130       RADEON_ENC_CS(cmd)
 131 #define RADEON_ENC_READ(buf, domain, off)                                                          \
 132    radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
 133 #define RADEON_ENC_WRITE(buf, domain, off)                                                         \
 134    radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
 135 #define RADEON_ENC_READWRITE(buf, domain, off)                                                     \
 136    radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
 137 #define RADEON_ENC_END()                                                                           \
 138    *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4;                             \
 139    enc->total_task_size += *begin;                                                                 \
 140    }
 141
 142 typedef struct rvcn_enc_session_info_s {
 143    uint32_t interface_version;
 144    uint32_t sw_context_address_hi;
 145    uint32_t sw_context_address_lo;
 146 } rvcn_enc_session_info_t;
 147
 148 typedef struct rvcn_enc_task_info_s {
 149    uint32_t total_size_of_all_packages;
 150    uint32_t task_id;
 151    uint32_t allowed_max_num_feedbacks;
 152 } rvcn_enc_task_info_t;
 153
 154 typedef struct rvcn_enc_session_init_s {
 155    uint32_t encode_standard;
 156    uint32_t aligned_picture_width;
 157    uint32_t aligned_picture_height;
 158    uint32_t padding_width;
 159    uint32_t padding_height;
 160    uint32_t pre_encode_mode;
 161    uint32_t pre_encode_chroma_enabled;
 162 } rvcn_enc_session_init_t;
 163
 164 typedef struct rvcn_enc_layer_control_s {
 165    uint32_t max_num_temporal_layers;
 166    uint32_t num_temporal_layers;
 167 } rvcn_enc_layer_control_t;
 168
 169 typedef struct rvcn_enc_layer_select_s {
 170    uint32_t temporal_layer_index;
 171 } rvcn_enc_layer_select_t;
 172
 173 typedef struct rvcn_enc_h264_slice_control_s {
 174    uint32_t slice_control_mode;
 175    union {
 176       uint32_t num_mbs_per_slice;
 177       uint32_t num_bits_per_slice;
 178    };
 179 } rvcn_enc_h264_slice_control_t;
 180
 181 typedef struct rvcn_enc_hevc_slice_control_s {
 182    uint32_t slice_control_mode;
 183    union {
 184       struct {
 185          uint32_t num_ctbs_per_slice;
 186          uint32_t num_ctbs_per_slice_segment;
 187       } fixed_ctbs_per_slice;
 188
 189       struct {
 190          uint32_t num_bits_per_slice;
 191          uint32_t num_bits_per_slice_segment;
 192       } fixed_bits_per_slice;
 193    };
 194 } rvcn_enc_hevc_slice_control_t;
 195
 196 typedef struct rvcn_enc_h264_spec_misc_s {
 197    uint32_t constrained_intra_pred_flag;
 198    uint32_t cabac_enable;
 199    uint32_t cabac_init_idc;
 200    uint32_t half_pel_enabled;
 201    uint32_t quarter_pel_enabled;
 202    uint32_t profile_idc;
 203    uint32_t level_idc;
 204    uint32_t b_picture_enabled;
 205    uint32_t weighted_bipred_idc;
 206 } rvcn_enc_h264_spec_misc_t;
 207
 208 typedef struct rvcn_enc_hevc_spec_misc_s {
 209    uint32_t log2_min_luma_coding_block_size_minus3;
 210    uint32_t amp_disabled;
 211    uint32_t strong_intra_smoothing_enabled;
 212    uint32_t constrained_intra_pred_flag;
 213    uint32_t cabac_init_flag;
 214    uint32_t half_pel_enabled;
 215    uint32_t quarter_pel_enabled;
 216 } rvcn_enc_hevc_spec_misc_t;
 217
 218 typedef struct rvcn_enc_rate_ctl_session_init_s {
 219    uint32_t rate_control_method;
 220    uint32_t vbv_buffer_level;
 221 } rvcn_enc_rate_ctl_session_init_t;
 222
 223 typedef struct rvcn_enc_rate_ctl_layer_init_s {
 224    uint32_t target_bit_rate;
 225    uint32_t peak_bit_rate;
 226    uint32_t frame_rate_num;
 227    uint32_t frame_rate_den;
 228    uint32_t vbv_buffer_size;
 229    uint32_t avg_target_bits_per_picture;
 230    uint32_t peak_bits_per_picture_integer;
 231    uint32_t peak_bits_per_picture_fractional;
 232 } rvcn_enc_rate_ctl_layer_init_t;
 233
 234 typedef struct rvcn_enc_rate_ctl_per_picture_s {
 235    uint32_t qp;
 236    uint32_t min_qp_app;
 237    uint32_t max_qp_app;
 238    uint32_t max_au_size;
 239    uint32_t enabled_filler_data;
 240    uint32_t skip_frame_enable;
 241    uint32_t enforce_hrd;
 242 } rvcn_enc_rate_ctl_per_picture_t;
 243
 244 typedef struct rvcn_enc_quality_params_s {
 245    uint32_t vbaq_mode;
 246    uint32_t scene_change_sensitivity;
 247    uint32_t scene_change_min_idr_interval;
 248    uint32_t two_pass_search_center_map_mode;
 249 } rvcn_enc_quality_params_t;
 250
 251 typedef struct rvcn_enc_direct_output_nalu_s {
 252    uint32_t type;
 253    uint32_t size;
 254    uint32_t data[1];
 255 } rvcn_enc_direct_output_nalu_t;
 256
 257 typedef struct rvcn_enc_slice_header_s {
 258    uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS];
 259    struct {
 260       uint32_t instruction;
 261       uint32_t num_bits;
 262    } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
 263 } rvcn_enc_slice_header_t;
 264
 265 typedef struct rvcn_enc_h264_reference_picture_info_s {
 266    unsigned int pic_type;
 267    unsigned int is_long_term;
 268    unsigned int picture_structure;
 269    unsigned int pic_order_cnt;
 270 } rvcn_enc_h264_reference_picture_info_t;
 271
 272 typedef struct rvcn_enc_encode_params_s {
 273    uint32_t pic_type;
 274    uint32_t allowed_max_bitstream_size;
 275    uint32_t input_picture_luma_address_hi;
 276    uint32_t input_picture_luma_address_lo;
 277    uint32_t input_picture_chroma_address_hi;
 278    uint32_t input_picture_chroma_address_lo;
 279    uint32_t input_pic_luma_pitch;
 280    uint32_t input_pic_chroma_pitch;
 281    uint8_t input_pic_swizzle_mode;
 282    uint32_t reference_picture_index;
 283    uint32_t reconstructed_picture_index;
 284 } rvcn_enc_encode_params_t;
 285
 286 typedef struct rvcn_enc_h264_encode_params_s {
 287    uint32_t input_picture_structure;
 288    uint32_t input_pic_order_cnt;
 289    uint32_t interlaced_mode;
 290    uint32_t reference_picture_structure;
 291    uint32_t reference_picture1_index;
 292    rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture0;
 293    uint32_t l0_reference_picture1_index;
 294    rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture1;
 295    uint32_t l1_reference_picture0_index;
 296    rvcn_enc_h264_reference_picture_info_t picture_info_l1_reference_picture0;
 297 } rvcn_enc_h264_encode_params_t;
 298
 299 typedef struct rvcn_enc_h264_deblocking_filter_s {
 300    uint32_t disable_deblocking_filter_idc;
 301    int32_t alpha_c0_offset_div2;
 302    int32_t beta_offset_div2;
 303    int32_t cb_qp_offset;
 304    int32_t cr_qp_offset;
 305 } rvcn_enc_h264_deblocking_filter_t;
 306
 307 typedef struct rvcn_enc_hevc_deblocking_filter_s {
 308    uint32_t loop_filter_across_slices_enabled;
 309    int32_t deblocking_filter_disabled;
 310    int32_t beta_offset_div2;
 311    int32_t tc_offset_div2;
 312    int32_t cb_qp_offset;
 313    int32_t cr_qp_offset;
 314 } rvcn_enc_hevc_deblocking_filter_t;
 315
 316 typedef struct rvcn_enc_intra_refresh_s {
 317    uint32_t intra_refresh_mode;
 318    uint32_t offset;
 319    uint32_t region_size;
 320 } rvcn_enc_intra_refresh_t;
 321
 322 typedef struct rvcn_enc_reconstructed_picture_s {
 323    uint32_t luma_offset;
 324    uint32_t chroma_offset;
 325 } rvcn_enc_reconstructed_picture_t;
 326
 327 typedef struct rvcn_enc_pre_encode_input_picture_s {
 328    union {
 329       struct {
 330          uint32_t luma_offset;
 331          uint32_t chroma_offset;
 332       } yuv;
 333       struct {
 334          uint32_t red_offset;
 335          uint32_t green_offset;
 336          uint32_t blue_offset;
 337       } rgb;
 338    };
 339 } rvcn_enc_pre_encode_input_picture_t;
 340
 341 typedef struct rvcn_enc_encode_context_buffer_s {
 342    uint32_t encode_context_address_hi;
 343    uint32_t encode_context_address_lo;
 344    uint32_t swizzle_mode;
 345    uint32_t rec_luma_pitch;
 346    uint32_t rec_chroma_pitch;
 347    uint32_t num_reconstructed_pictures;
 348    rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
 349    uint32_t pre_encode_picture_luma_pitch;
 350    uint32_t pre_encode_picture_chroma_pitch;
 351    rvcn_enc_reconstructed_picture_t
 352       pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
 353    rvcn_enc_reconstructed_picture_t pre_encode_input_picture;
 354 } rvcn_enc_encode_context_buffer_t;
 355
 356 typedef struct rvcn_enc_video_bitstream_buffer_s {
 357    uint32_t mode;
 358    uint32_t video_bitstream_buffer_address_hi;
 359    uint32_t video_bitstream_buffer_address_lo;
 360    uint32_t video_bitstream_buffer_size;
 361    uint32_t video_bitstream_data_offset;
 362 } rvcn_enc_video_bitstream_buffer_t;
 363
 364 typedef struct rvcn_enc_feedback_buffer_s {
 365    uint32_t mode;
 366    uint32_t feedback_buffer_address_hi;
 367    uint32_t feedback_buffer_address_lo;
 368    uint32_t feedback_buffer_size;
 369    uint32_t feedback_data_size;
 370 } rvcn_enc_feedback_buffer_t;
 371
 372 typedef struct rvcn_enc_cmd_s {
 373    uint32_t session_info;
 374    uint32_t task_info;
 375    uint32_t session_init;
 376    uint32_t layer_control;
 377    uint32_t layer_select;
 378    uint32_t rc_session_init;
 379    uint32_t rc_layer_init;
 380    uint32_t rc_per_pic;
 381    uint32_t quality_params;
 382    uint32_t slice_header;
 383    uint32_t enc_params;
 384    uint32_t intra_refresh;
 385    uint32_t ctx;
 386    uint32_t bitstream;
 387    uint32_t feedback;
 388    uint32_t nalu;
 389    uint32_t slice_control_hevc;
 390    uint32_t spec_misc_hevc;
 391    uint32_t enc_params_hevc;
 392    uint32_t deblocking_filter_hevc;
 393    uint32_t slice_control_h264;
 394    uint32_t spec_misc_h264;
 395    uint32_t enc_params_h264;
 396    uint32_t deblocking_filter_h264;
 397    uint32_t input_format;
 398    uint32_t output_format;
 399 } rvcn_enc_cmd_t;
 400
 401 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
 402                                       struct radeon_surf **surface);
 403
 404 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 405                                                const struct pipe_video_codec *templat,
 406                                                struct radeon_winsys *ws,
 407                                                radeon_enc_get_buffer get_buffer);
 408
 409 struct radeon_enc_pic {
 410    enum pipe_h264_enc_picture_type picture_type;
 411
 412    unsigned frame_num;
 413    unsigned pic_order_cnt;
 414    unsigned pic_order_cnt_type;
 415    unsigned ref_idx_l0;
 416    unsigned ref_idx_l1;
 417    unsigned crop_left;
 418    unsigned crop_right;
 419    unsigned crop_top;
 420    unsigned crop_bottom;
 421    unsigned general_tier_flag;
 422    unsigned general_profile_idc;
 423    unsigned general_level_idc;
 424    unsigned max_poc;
 425    unsigned log2_max_poc;
 426    unsigned chroma_format_idc;
 427    unsigned pic_width_in_luma_samples;
 428    unsigned pic_height_in_luma_samples;
 429    unsigned log2_diff_max_min_luma_coding_block_size;
 430    unsigned log2_min_transform_block_size_minus2;
 431    unsigned log2_diff_max_min_transform_block_size;
 432    unsigned max_transform_hierarchy_depth_inter;
 433    unsigned max_transform_hierarchy_depth_intra;
 434    unsigned log2_parallel_merge_level_minus2;
 435    unsigned bit_depth_luma_minus8;
 436    unsigned bit_depth_chroma_minus8;
 437    unsigned nal_unit_type;
 438    unsigned max_num_merge_cand;
 439
 440    bool not_referenced;
 441    bool is_idr;
 442    bool is_even_frame;
 443    bool sample_adaptive_offset_enabled_flag;
 444    bool pcm_enabled_flag;
 445    bool sps_temporal_mvp_enabled_flag;
 446
 447    rvcn_enc_session_info_t session_info;
 448    rvcn_enc_task_info_t task_info;
 449    rvcn_enc_session_init_t session_init;
 450    rvcn_enc_layer_control_t layer_ctrl;
 451    rvcn_enc_layer_select_t layer_sel;
 452    rvcn_enc_h264_slice_control_t slice_ctrl;
 453    rvcn_enc_hevc_slice_control_t hevc_slice_ctrl;
 454    rvcn_enc_h264_spec_misc_t spec_misc;
 455    rvcn_enc_hevc_spec_misc_t hevc_spec_misc;
 456    rvcn_enc_rate_ctl_session_init_t rc_session_init;
 457    rvcn_enc_rate_ctl_layer_init_t rc_layer_init;
 458    rvcn_enc_h264_encode_params_t h264_enc_params;
 459    rvcn_enc_h264_deblocking_filter_t h264_deblock;
 460    rvcn_enc_hevc_deblocking_filter_t hevc_deblock;
 461    rvcn_enc_rate_ctl_per_picture_t rc_per_pic;
 462    rvcn_enc_quality_params_t quality_params;
 463    rvcn_enc_encode_context_buffer_t ctx_buf;
 464    rvcn_enc_video_bitstream_buffer_t bit_buf;
 465    rvcn_enc_feedback_buffer_t fb_buf;
 466    rvcn_enc_intra_refresh_t intra_ref;
 467    rvcn_enc_encode_params_t enc_params;
 468 };
 469
 470 struct radeon_encoder {
 471    struct pipe_video_codec base;
 472
 473    void (*begin)(struct radeon_encoder *enc);
 474    void (*encode)(struct radeon_encoder *enc);
 475    void (*destroy)(struct radeon_encoder *enc);
 476    void (*session_info)(struct radeon_encoder *enc);
 477    void (*task_info)(struct radeon_encoder *enc, bool need_feedback);
 478    void (*session_init)(struct radeon_encoder *enc);
 479    void (*layer_control)(struct radeon_encoder *enc);
 480    void (*layer_select)(struct radeon_encoder *enc);
 481    void (*slice_control)(struct radeon_encoder *enc);
 482    void (*spec_misc)(struct radeon_encoder *enc);
 483    void (*rc_session_init)(struct radeon_encoder *enc);
 484    void (*rc_layer_init)(struct radeon_encoder *enc);
 485    void (*deblocking_filter)(struct radeon_encoder *enc);
 486    void (*quality_params)(struct radeon_encoder *enc);
 487    void (*nalu_sps)(struct radeon_encoder *enc);
 488    void (*nalu_pps)(struct radeon_encoder *enc);
 489    void (*nalu_vps)(struct radeon_encoder *enc);
 490    void (*nalu_aud)(struct radeon_encoder *enc);
 491    void (*slice_header)(struct radeon_encoder *enc);
 492    void (*ctx)(struct radeon_encoder *enc);
 493    void (*bitstream)(struct radeon_encoder *enc);
 494    void (*feedback)(struct radeon_encoder *enc);
 495    void (*intra_refresh)(struct radeon_encoder *enc);
 496    void (*rc_per_pic)(struct radeon_encoder *enc);
 497    void (*encode_params)(struct radeon_encoder *enc);
 498    void (*encode_params_codec_spec)(struct radeon_encoder *enc);
 499    void (*op_init)(struct radeon_encoder *enc);
 500    void (*op_close)(struct radeon_encoder *enc);
 501    void (*op_enc)(struct radeon_encoder *enc);
 502    void (*op_init_rc)(struct radeon_encoder *enc);
 503    void (*op_init_rc_vbv)(struct radeon_encoder *enc);
 504    void (*op_speed)(struct radeon_encoder *enc);
 505    void (*encode_headers)(struct radeon_encoder *enc);
 506    void (*input_format)(struct radeon_encoder *enc);
 507    void (*output_format)(struct radeon_encoder *enc);
 508
 509    unsigned stream_handle;
 510
 511    struct pipe_screen *screen;
 512    struct radeon_winsys *ws;
 513    struct radeon_cmdbuf *cs;
 514
 515    radeon_enc_get_buffer get_buffer;
 516
 517    struct pb_buffer *handle;
 518    struct radeon_surf *luma;
 519    struct radeon_surf *chroma;
 520
 521    struct pb_buffer *bs_handle;
 522    unsigned bs_size;
 523
 524    unsigned cpb_num;
 525
 526    struct rvid_buffer *si;
 527    struct rvid_buffer *fb;
 528    struct rvid_buffer cpb;
 529    struct radeon_enc_pic enc_pic;
 530    rvcn_enc_cmd_t cmd;
 531
 532    unsigned alignment;
 533    unsigned shifter;
 534    unsigned bits_in_shifter;
 535    unsigned num_zeros;
 536    unsigned byte_index;
 537    unsigned bits_output;
 538    uint32_t total_task_size;
 539    uint32_t *p_task_size;
 540
 541    bool emulation_prevention;
 542    bool need_feedback;
 543 };
 544
 545 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
 546                            enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset);
 547
 548 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set);
 549
 550 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte);
 551
 552 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte);
 553
 554 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
 555                                 unsigned int num_bits);
 556
 557 void radeon_enc_reset(struct radeon_encoder *enc);
 558
 559 void radeon_enc_byte_align(struct radeon_encoder *enc);
 560
 561 void radeon_enc_flush_headers(struct radeon_encoder *enc);
 562
 563 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value);
 564
 565 void radeon_enc_code_se(struct radeon_encoder *enc, int value);
 566
 567 void radeon_enc_1_2_init(struct radeon_encoder *enc);
 568
 569 void radeon_enc_2_0_init(struct radeon_encoder *enc);
 570
 571 void radeon_enc_3_0_init(struct radeon_encoder *enc);
 572
 573 #endif // _RADEON_VCN_ENC_H