1 /**************************************************************************
3 * Copyright 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #ifndef _RADEON_VCN_ENC_H
29 #define _RADEON_VCN_ENC_H
31 #define RENCODE_IB_OP_INITIALIZE 0x01000001
32 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002
33 #define RENCODE_IB_OP_ENCODE 0x01000003
34 #define RENCODE_IB_OP_INIT_RC 0x01000004
35 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005
36 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006
37 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007
38 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008
40 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000
41 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16
42 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF
43 #define RENCODE_IF_MINOR_VERSION_SHIFT 0
45 #define RENCODE_ENCODE_STANDARD_HEVC 0
46 #define RENCODE_ENCODE_STANDARD_H264 1
48 #define RENCODE_PREENCODE_MODE_NONE 0x00000000
49 #define RENCODE_PREENCODE_MODE_1X 0x00000001
50 #define RENCODE_PREENCODE_MODE_2X 0x00000002
51 #define RENCODE_PREENCODE_MODE_4X 0x00000004
53 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
54 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
56 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
57 #define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
59 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
60 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
61 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002
62 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003
64 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000
65 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001
66 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002
67 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003
68 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004
69 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005
71 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16
72 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16
74 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000
75 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001
77 #define RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END 0x00010000
78 #define RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE 0x00010001
79 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT 0x00010002
80 #define RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00010003
82 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000
83 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001
85 #define RENCODE_PICTURE_TYPE_B 0
86 #define RENCODE_PICTURE_TYPE_P 1
87 #define RENCODE_PICTURE_TYPE_I 2
88 #define RENCODE_PICTURE_TYPE_P_SKIP 3
90 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0
91 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1
92 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5
93 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9
95 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0
96 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1
97 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2
99 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0
100 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1
101 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2
103 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0
104 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1
105 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2
107 #define RENCODE_INTRA_REFRESH_MODE_NONE 0
108 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1
109 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2
111 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34
113 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0
114 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1
116 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0
117 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1
119 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0
120 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1
122 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
123 #define RADEON_ENC_BEGIN(cmd) { \
124 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
126 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
127 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
128 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
129 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
130 enc->total_task_size += *begin;}
132 typedef struct rvcn_enc_session_info_s
134 uint32_t interface_version
;
135 uint32_t sw_context_address_hi
;
136 uint32_t sw_context_address_lo
;
137 } rvcn_enc_session_info_t
;
139 typedef struct rvcn_enc_task_info_s
141 uint32_t total_size_of_all_packages
;
143 uint32_t allowed_max_num_feedbacks
;
144 } rvcn_enc_task_info_t
;
146 typedef struct rvcn_enc_session_init_s
148 uint32_t encode_standard
;
149 uint32_t aligned_picture_width
;
150 uint32_t aligned_picture_height
;
151 uint32_t padding_width
;
152 uint32_t padding_height
;
153 uint32_t pre_encode_mode
;
154 uint32_t pre_encode_chroma_enabled
;
155 } rvcn_enc_session_init_t
;
157 typedef struct rvcn_enc_layer_control_s
159 uint32_t max_num_temporal_layers
;
160 uint32_t num_temporal_layers
;
161 } rvcn_enc_layer_control_t
;
163 typedef struct rvcn_enc_layer_select_s
165 uint32_t temporal_layer_index
;
166 } rvcn_enc_layer_select_t
;
168 typedef struct rvcn_enc_h264_slice_control_s
170 uint32_t slice_control_mode
;
173 uint32_t num_mbs_per_slice
;
174 uint32_t num_bits_per_slice
;
176 } rvcn_enc_h264_slice_control_t
;
178 typedef struct rvcn_enc_hevc_slice_control_s
180 uint32_t slice_control_mode
;
185 uint32_t num_ctbs_per_slice
;
186 uint32_t num_ctbs_per_slice_segment
;
187 } fixed_ctbs_per_slice
;
191 uint32_t num_bits_per_slice
;
192 uint32_t num_bits_per_slice_segment
;
193 } fixed_bits_per_slice
;
195 } rvcn_enc_hevc_slice_control_t
;
197 typedef struct rvcn_enc_h264_spec_misc_s
199 uint32_t constrained_intra_pred_flag
;
200 uint32_t cabac_enable
;
201 uint32_t cabac_init_idc
;
202 uint32_t half_pel_enabled
;
203 uint32_t quarter_pel_enabled
;
204 uint32_t profile_idc
;
206 } rvcn_enc_h264_spec_misc_t
;
208 typedef struct rvcn_enc_hevc_spec_misc_s
210 uint32_t log2_min_luma_coding_block_size_minus3
;
211 uint32_t amp_disabled
;
212 uint32_t strong_intra_smoothing_enabled
;
213 uint32_t constrained_intra_pred_flag
;
214 uint32_t cabac_init_flag
;
215 uint32_t half_pel_enabled
;
216 uint32_t quarter_pel_enabled
;
217 } rvcn_enc_hevc_spec_misc_t
;
219 typedef struct rvcn_enc_rate_ctl_session_init_s
221 uint32_t rate_control_method
;
222 uint32_t vbv_buffer_level
;
223 } rvcn_enc_rate_ctl_session_init_t
;
225 typedef struct rvcn_enc_rate_ctl_layer_init_s
227 uint32_t target_bit_rate
;
228 uint32_t peak_bit_rate
;
229 uint32_t frame_rate_num
;
230 uint32_t frame_rate_den
;
231 uint32_t vbv_buffer_size
;
232 uint32_t avg_target_bits_per_picture
;
233 uint32_t peak_bits_per_picture_integer
;
234 uint32_t peak_bits_per_picture_fractional
;
235 } rvcn_enc_rate_ctl_layer_init_t
;
237 typedef struct rvcn_enc_rate_ctl_per_picture_s
242 uint32_t max_au_size
;
243 uint32_t enabled_filler_data
;
244 uint32_t skip_frame_enable
;
245 uint32_t enforce_hrd
;
246 } rvcn_enc_rate_ctl_per_picture_t
;
248 typedef struct rvcn_enc_quality_params_s
251 uint32_t scene_change_sensitivity
;
252 uint32_t scene_change_min_idr_interval
;
253 } rvcn_enc_quality_params_t
;
255 typedef struct rvcn_enc_direct_output_nalu_s
260 } rvcn_enc_direct_output_nalu_t
;
262 typedef struct rvcn_enc_slice_header_s
264 uint32_t bitstream_template
[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS
];
266 uint32_t instruction
;
268 } instructions
[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS
];
269 } rvcn_enc_slice_header_t
;
271 typedef struct rvcn_enc_encode_params_s
274 uint32_t allowed_max_bitstream_size
;
275 uint32_t input_picture_luma_address_hi
;
276 uint32_t input_picture_luma_address_lo
;
277 uint32_t input_picture_chroma_address_hi
;
278 uint32_t input_picture_chroma_address_lo
;
279 uint32_t input_pic_luma_pitch
;
280 uint32_t input_pic_chroma_pitch
;
281 uint8_t input_pic_swizzle_mode
;
282 uint32_t reference_picture_index
;
283 uint32_t reconstructed_picture_index
;
284 } rvcn_enc_encode_params_t
;
286 typedef struct rvcn_enc_h264_encode_params_s
288 uint32_t input_picture_structure
;
289 uint32_t interlaced_mode
;
290 uint32_t reference_picture_structure
;
291 uint32_t reference_picture1_index
;
292 } rvcn_enc_h264_encode_params_t
;
294 typedef struct rvcn_enc_h264_deblocking_filter_s
296 uint32_t disable_deblocking_filter_idc
;
297 int32_t alpha_c0_offset_div2
;
298 int32_t beta_offset_div2
;
299 int32_t cb_qp_offset
;
300 int32_t cr_qp_offset
;
301 } rvcn_enc_h264_deblocking_filter_t
;
303 typedef struct rvcn_enc_hevc_deblocking_filter_s
305 uint32_t loop_filter_across_slices_enabled
;
306 int32_t deblocking_filter_disabled
;
307 int32_t beta_offset_div2
;
308 int32_t tc_offset_div2
;
309 int32_t cb_qp_offset
;
310 int32_t cr_qp_offset
;
311 } rvcn_enc_hevc_deblocking_filter_t
;
313 typedef struct rvcn_enc_intra_refresh_s
315 uint32_t intra_refresh_mode
;
317 uint32_t region_size
;
318 } rvcn_enc_intra_refresh_t
;
320 typedef struct rvcn_enc_reconstructed_picture_s
322 uint32_t luma_offset
;
323 uint32_t chroma_offset
;
324 } rvcn_enc_reconstructed_picture_t
;
326 typedef struct rvcn_enc_encode_context_buffer_s
328 uint32_t encode_context_address_hi
;
329 uint32_t encode_context_address_lo
;
330 uint32_t swizzle_mode
;
331 uint32_t rec_luma_pitch
;
332 uint32_t rec_chroma_pitch
;
333 uint32_t num_reconstructed_pictures
;
334 rvcn_enc_reconstructed_picture_t reconstructed_pictures
[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES
];
335 uint32_t pre_encode_picture_luma_pitch
;
336 uint32_t pre_encode_picture_chroma_pitch
;
337 rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures
[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES
];
338 rvcn_enc_reconstructed_picture_t pre_encode_input_picture
;
339 } rvcn_enc_encode_context_buffer_t
;
341 typedef struct rvcn_enc_video_bitstream_buffer_s
344 uint32_t video_bitstream_buffer_address_hi
;
345 uint32_t video_bitstream_buffer_address_lo
;
346 uint32_t video_bitstream_buffer_size
;
347 uint32_t video_bitstream_data_offset
;
348 } rvcn_enc_video_bitstream_buffer_t
;
350 typedef struct rvcn_enc_feedback_buffer_s
353 uint32_t feedback_buffer_address_hi
;
354 uint32_t feedback_buffer_address_lo
;
355 uint32_t feedback_buffer_size
;
356 uint32_t feedback_data_size
;
357 } rvcn_enc_feedback_buffer_t
;
359 typedef void (*radeon_enc_get_buffer
)(struct pipe_resource
*resource
,
360 struct pb_buffer
**handle
,
361 struct radeon_surf
**surface
);
363 struct pipe_video_codec
*radeon_create_encoder(struct pipe_context
*context
,
364 const struct pipe_video_codec
*templat
,
365 struct radeon_winsys
* ws
,
366 radeon_enc_get_buffer get_buffer
);
368 struct radeon_enc_pic
{
369 enum pipe_h264_enc_picture_type picture_type
;
372 unsigned pic_order_cnt
;
373 unsigned pic_order_cnt_type
;
379 unsigned crop_bottom
;
380 unsigned general_tier_flag
;
381 unsigned general_profile_idc
;
382 unsigned general_level_idc
;
384 unsigned log2_max_poc
;
385 unsigned chroma_format_idc
;
386 unsigned pic_width_in_luma_samples
;
387 unsigned pic_height_in_luma_samples
;
388 unsigned log2_diff_max_min_luma_coding_block_size
;
389 unsigned log2_min_transform_block_size_minus2
;
390 unsigned log2_diff_max_min_transform_block_size
;
391 unsigned max_transform_hierarchy_depth_inter
;
392 unsigned max_transform_hierarchy_depth_intra
;
393 unsigned log2_parallel_merge_level_minus2
;
394 unsigned bit_depth_luma_minus8
;
395 unsigned bit_depth_chroma_minus8
;
396 unsigned nal_unit_type
;
397 unsigned max_num_merge_cand
;
402 bool sample_adaptive_offset_enabled_flag
;
403 bool pcm_enabled_flag
;
404 bool sps_temporal_mvp_enabled_flag
;
406 rvcn_enc_task_info_t task_info
;
407 rvcn_enc_session_init_t session_init
;
408 rvcn_enc_layer_control_t layer_ctrl
;
409 rvcn_enc_layer_select_t layer_sel
;
410 rvcn_enc_h264_slice_control_t slice_ctrl
;
411 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl
;
412 rvcn_enc_h264_spec_misc_t spec_misc
;
413 rvcn_enc_hevc_spec_misc_t hevc_spec_misc
;
414 rvcn_enc_rate_ctl_session_init_t rc_session_init
;
415 rvcn_enc_rate_ctl_layer_init_t rc_layer_init
;
416 rvcn_enc_h264_encode_params_t h264_enc_params
;
417 rvcn_enc_h264_deblocking_filter_t h264_deblock
;
418 rvcn_enc_hevc_deblocking_filter_t hevc_deblock
;
419 rvcn_enc_rate_ctl_per_picture_t rc_per_pic
;
420 rvcn_enc_quality_params_t quality_params
;
421 rvcn_enc_encode_context_buffer_t ctx_buf
;
422 rvcn_enc_video_bitstream_buffer_t bit_buf
;
423 rvcn_enc_feedback_buffer_t fb_buf
;
424 rvcn_enc_intra_refresh_t intra_ref
;
425 rvcn_enc_encode_params_t enc_params
;
428 struct radeon_encoder
{
429 struct pipe_video_codec base
;
431 void (*begin
)(struct radeon_encoder
*enc
);
432 void (*encode
)(struct radeon_encoder
*enc
);
433 void (*destroy
)(struct radeon_encoder
*enc
);
434 void (*session_info
)(struct radeon_encoder
*enc
);
435 void (*task_info
)(struct radeon_encoder
*enc
, bool need_feedback
);
436 void (*session_init
)(struct radeon_encoder
*enc
);
437 void (*layer_control
)(struct radeon_encoder
*enc
);
438 void (*layer_select
)(struct radeon_encoder
*enc
);
439 void (*slice_control
)(struct radeon_encoder
*enc
);
440 void (*spec_misc
)(struct radeon_encoder
*enc
);
441 void (*rc_session_init
)(struct radeon_encoder
*enc
);
442 void (*rc_layer_init
)(struct radeon_encoder
*enc
);
443 void (*deblocking_filter
)(struct radeon_encoder
*enc
);
444 void (*quality_params
)(struct radeon_encoder
*enc
);
445 void (*nalu_sps
)(struct radeon_encoder
*enc
);
446 void (*nalu_pps
)(struct radeon_encoder
*enc
);
447 void (*nalu_vps
)(struct radeon_encoder
*enc
);
448 void (*nalu_aud
)(struct radeon_encoder
*enc
);
449 void (*slice_header
)(struct radeon_encoder
*enc
);
450 void (*ctx
)(struct radeon_encoder
*enc
);
451 void (*bitstream
)(struct radeon_encoder
*enc
);
452 void (*feedback
)(struct radeon_encoder
*enc
);
453 void (*intra_refresh
)(struct radeon_encoder
*enc
);
454 void (*rc_per_pic
)(struct radeon_encoder
*enc
);
455 void (*encode_params
)(struct radeon_encoder
*enc
);
456 void (*encode_params_codec_spec
)(struct radeon_encoder
*enc
);
457 void (*op_init
)(struct radeon_encoder
*enc
);
458 void (*op_close
)(struct radeon_encoder
*enc
);
459 void (*op_enc
)(struct radeon_encoder
*enc
);
460 void (*op_init_rc
)(struct radeon_encoder
*enc
);
461 void (*op_init_rc_vbv
)(struct radeon_encoder
*enc
);
462 void (*op_speed
)(struct radeon_encoder
*enc
);
463 void (*encode_headers
)(struct radeon_encoder
*enc
);
465 unsigned stream_handle
;
467 struct pipe_screen
*screen
;
468 struct radeon_winsys
* ws
;
469 struct radeon_cmdbuf
* cs
;
471 radeon_enc_get_buffer get_buffer
;
473 struct pb_buffer
* handle
;
474 struct radeon_surf
* luma
;
475 struct radeon_surf
* chroma
;
477 struct pb_buffer
* bs_handle
;
482 struct rvid_buffer
*si
;
483 struct rvid_buffer
*fb
;
484 struct rvid_buffer cpb
;
485 struct radeon_enc_pic enc_pic
;
489 unsigned bits_in_shifter
;
492 unsigned bits_output
;
493 uint32_t total_task_size
;
494 uint32_t* p_task_size
;
496 bool emulation_prevention
;
500 void radeon_enc_add_buffer(struct radeon_encoder
*enc
, struct pb_buffer
*buf
,
501 enum radeon_bo_usage usage
, enum radeon_bo_domain domain
,
504 void radeon_enc_set_emulation_prevention(struct radeon_encoder
*enc
, bool set
);
506 void radeon_enc_output_one_byte(struct radeon_encoder
*enc
, unsigned char byte
);
508 void radeon_enc_emulation_prevention(struct radeon_encoder
*enc
,
511 void radeon_enc_code_fixed_bits(struct radeon_encoder
*enc
, unsigned int value
,
512 unsigned int num_bits
);
514 void radeon_enc_reset(struct radeon_encoder
*enc
);
516 void radeon_enc_byte_align(struct radeon_encoder
*enc
);
518 void radeon_enc_flush_headers(struct radeon_encoder
*enc
);
520 void radeon_enc_code_ue(struct radeon_encoder
*enc
, unsigned int value
);
522 void radeon_enc_code_se(struct radeon_encoder
*enc
, int value
);
524 void radeon_enc_1_2_init(struct radeon_encoder
*enc
);
526 #endif // _RADEON_VCN_ENC_H