src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33 #include "util/u_memory.h"
  34
  35 #include "vl/vl_video_buffer.h"
  36
  37 #include "si_pipe.h"
  38 #include "radeon_video.h"
  39 #include "radeon_vcn_enc.h"
  40
  41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
  42 #define RADEON_ENC_BEGIN(cmd) { \
  43         uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
  44 RADEON_ENC_CS(cmd)
  45 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
  46 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
  47 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
  48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
  49         enc->total_task_size += *begin;}
  50
  51 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
  52
  53 static void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
  54                                                                   enum radeon_bo_usage usage, enum radeon_bo_domain domain,
  55                                                                   signed offset)
  56 {
  57         enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
  58                                domain, 0);
  59         uint64_t addr;
  60         addr = enc->ws->buffer_get_virtual_address(buf);
  61         addr = addr + offset;
  62         RADEON_ENC_CS(addr >> 32);
  63         RADEON_ENC_CS(addr);
  64 }
  65
  66 static void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
  67 {
  68         if (set != enc->emulation_prevention) {
  69                 enc->emulation_prevention = set;
  70                 enc->num_zeros = 0;
  71         }
  72 }
  73
  74 static void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
  75 {
  76         if (enc->byte_index == 0)
  77                 enc->cs->current.buf[enc->cs->current.cdw] = 0;
  78         enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
  79         enc->byte_index++;
  80
  81         if (enc->byte_index >= 4) {
  82                 enc->byte_index = 0;
  83                 enc->cs->current.cdw++;
  84         }
  85 }
  86
  87 static void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
  88 {
  89         if(enc->emulation_prevention) {
  90                 if((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
  91             radeon_enc_output_one_byte(enc, 0x03);
  92             enc->bits_output += 8;
  93             enc->num_zeros = 0;
  94         }
  95         enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
  96     }
  97 }
  98
  99 static void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, unsigned int num_bits)
 100 {
 101         unsigned int bits_to_pack = 0;
 102
 103         while(num_bits > 0) {
 104                 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
 105                 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
 106
 107                 if (bits_to_pack < num_bits)
 108                         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
 109
 110                 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
 111                 num_bits -= bits_to_pack;
 112                 enc->bits_in_shifter += bits_to_pack;
 113
 114                 while(enc->bits_in_shifter >= 8) {
 115                         unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 116                         enc->shifter <<= 8;
 117                         radeon_enc_emulation_prevention(enc, output_byte);
 118                         radeon_enc_output_one_byte(enc, output_byte);
 119                         enc->bits_in_shifter -= 8;
 120                         enc->bits_output += 8;
 121                 }
 122         }
 123 }
 124
 125 static void radeon_enc_reset(struct radeon_encoder *enc)
 126 {
 127         enc->emulation_prevention = false;
 128         enc->shifter = 0;
 129         enc->bits_in_shifter = 0;
 130         enc->bits_output = 0;
 131         enc->num_zeros = 0;
 132         enc->byte_index = 0;
 133 }
 134
 135 static void radeon_enc_byte_align(struct radeon_encoder *enc)
 136 {
 137         unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
 138
 139         if (num_padding_zeros > 0)
 140                 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
 141 }
 142
 143 static void radeon_enc_flush_headers(struct radeon_encoder *enc)
 144 {
 145         if (enc->bits_in_shifter != 0) {
 146                 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
 147                 radeon_enc_emulation_prevention(enc, output_byte);
 148                 radeon_enc_output_one_byte(enc, output_byte);
 149                 enc->bits_output += enc->bits_in_shifter;
 150                 enc->shifter = 0;
 151                 enc->bits_in_shifter = 0;
 152                 enc->num_zeros = 0;
 153         }
 154
 155         if (enc->byte_index > 0) {
 156                 enc->cs->current.cdw++;
 157                 enc->byte_index = 0;
 158         }
 159 }
 160
 161 static void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
 162 {
 163         int x = -1;
 164         unsigned int ue_code = value + 1;
 165         value += 1;
 166
 167         while (value) {
 168                 value = (value >> 1);
 169                 x += 1;
 170         }
 171
 172         unsigned int ue_length = (x << 1) + 1;
 173         radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
 174 }
 175
 176 static void radeon_enc_code_se(struct radeon_encoder *enc, int value)
 177 {
 178         unsigned int v = 0;
 179
 180         if (value != 0)
 181                 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
 182
 183         radeon_enc_code_ue(enc, v);
 184 }
 185
 186 static void radeon_enc_session_info(struct radeon_encoder *enc)
 187 {
 188         unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 189                                                                           (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 190         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
 191         RADEON_ENC_CS(interface_version);
 192         RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
 193         RADEON_ENC_END();
 194 }
 195
 196 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
 197 {
 198         enc->enc_pic.task_info.task_id++;
 199
 200         if (need_feedback)
 201                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
 202         else
 203                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
 204
 205         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
 206         enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
 207         RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
 208         RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
 209         RADEON_ENC_END();
 210 }
 211
 212 static void radeon_enc_session_init(struct radeon_encoder *enc)
 213 {
 214         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
 215         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
 216         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 217         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 218         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 219         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 220         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 221
 222         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 223         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 224         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 225         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 226         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 227         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 228         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 229         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 230         RADEON_ENC_END();
 231 }
 232
 233 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
 234 {
 235         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
 236         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
 237         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
 238         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
 239         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
 240         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
 241         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
 242
 243         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
 244         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
 245         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
 246         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
 247         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 248         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 249         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 250         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 251         RADEON_ENC_END();
 252 }
 253
 254 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 255 {
 256         enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 257         enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 258
 259         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
 260         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 261         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 262         RADEON_ENC_END();
 263 }
 264
 265 static void radeon_enc_layer_select(struct radeon_encoder *enc)
 266 {
 267         enc->enc_pic.layer_sel.temporal_layer_index = 0;
 268
 269         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
 270         RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 271         RADEON_ENC_END();
 272 }
 273
 274 static void radeon_enc_slice_control(struct radeon_encoder *enc)
 275 {
 276         enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 277         enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
 278
 279         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
 280         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
 281         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
 282         RADEON_ENC_END();
 283 }
 284
 285 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
 286 {
 287         enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
 288         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 289         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 290
 291         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
 292         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 293         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
 294         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 295         RADEON_ENC_END();
 296 }
 297
 298 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 299 {
 300         enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
 301         enc->enc_pic.spec_misc.cabac_enable = 0;
 302         enc->enc_pic.spec_misc.cabac_init_idc = 0;
 303         enc->enc_pic.spec_misc.half_pel_enabled = 1;
 304         enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
 305         enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
 306         enc->enc_pic.spec_misc.level_idc = enc->base.level;
 307
 308         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
 309         RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
 310         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
 311         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
 312         RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
 313         RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
 314         RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
 315         RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
 316         RADEON_ENC_END();
 317 }
 318
 319 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 320 {
 321         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 322         enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = pic->seq.log2_min_luma_coding_block_size_minus3;
 323         enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
 324         enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag;
 325         enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
 326         enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
 327         enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
 328         enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
 329
 330         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
 331         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 332         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 333         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 334         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 335         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 336         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 337         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 338         RADEON_ENC_END();
 339 }
 340
 341 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 342 {
 343         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 344                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 345                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
 346                 switch(pic->rate_ctrl.rate_ctrl_method) {
 347                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE:
 348                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 349                                 break;
 350                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 351                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT:
 352                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 353                                 break;
 354                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 355                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
 356                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 357                                 break;
 358                         default:
 359                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 360                 }
 361         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 362                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 363                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
 364                 switch(pic->rc.rate_ctrl_method) {
 365                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
 366                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 367                                 break;
 368                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 369                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
 370                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 371                                 break;
 372                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 373                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
 374                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 375                                 break;
 376                         default:
 377                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 378                 }
 379         }
 380
 381         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT);
 382         RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 383         RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 384         RADEON_ENC_END();
 385 }
 386
 387 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 388 {
 389         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 390                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 391                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate;
 392                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
 393                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num;
 394                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
 395                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
 396                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
 397                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer;
 398                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction;
 399         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 400                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 401                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
 402                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
 403                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
 404                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
 405                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
 406                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
 407                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
 408                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
 409         }
 410
 411         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT);
 412         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 413         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 414         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 415         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 416         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 417         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 418         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 419         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 420         RADEON_ENC_END();
 421 }
 422
 423 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
 424 {
 425         enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
 426         enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
 427         enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
 428         enc->enc_pic.h264_deblock.cb_qp_offset = 0;
 429         enc->enc_pic.h264_deblock.cr_qp_offset = 0;
 430
 431         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER);
 432         RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
 433         RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 434         RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
 435         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
 436         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
 437         RADEON_ENC_END();
 438 }
 439
 440 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 441 {
 442         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 443         enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
 444         enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
 445         enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
 446         enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
 447         enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
 448         enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
 449
 450         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER);
 451         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 452         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 453         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 454         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 455         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 456         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 457         RADEON_ENC_END();
 458 }
 459
 460 static void radeon_enc_quality_params(struct radeon_encoder *enc)
 461 {
 462         enc->enc_pic.quality_params.vbaq_mode = 0;
 463         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 464         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 465
 466         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS);
 467         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 468         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 469         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 470         RADEON_ENC_END();
 471 }
 472
 473 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
 474 {
 475         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 476         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 477         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 478         radeon_enc_reset(enc);
 479         radeon_enc_set_emulation_prevention(enc, false);
 480         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 481         radeon_enc_code_fixed_bits(enc, 0x67, 8);
 482         radeon_enc_byte_align(enc);
 483         radeon_enc_set_emulation_prevention(enc, true);
 484         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
 485         radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
 486         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
 487         radeon_enc_code_ue(enc, 0x0);
 488
 489         if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
 490                         enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
 491                         enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
 492                         enc->enc_pic.spec_misc.profile_idc == 138) {
 493                 radeon_enc_code_ue(enc, 0x1);
 494                 radeon_enc_code_ue(enc, 0x0);
 495                 radeon_enc_code_ue(enc, 0x0);
 496                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 497         }
 498
 499         radeon_enc_code_ue(enc, 1);
 500         radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
 501
 502         if (enc->enc_pic.pic_order_cnt_type == 0)
 503                 radeon_enc_code_ue(enc, 1);
 504
 505         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 506         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
 507         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
 508         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
 509         bool progressive_only = true;
 510         radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
 511
 512         if (!progressive_only)
 513                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 514
 515         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 516
 517         if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
 518                         (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
 519                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 520                 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
 521                 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
 522                 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
 523                 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 524         } else
 525                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 526
 527         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 528         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 529         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 530         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 531         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 532         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 533         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 534         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 535         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 536         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 537         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 538         radeon_enc_code_ue(enc, 0x0);
 539         radeon_enc_code_ue(enc, 0x0);
 540         radeon_enc_code_ue(enc, 16);
 541         radeon_enc_code_ue(enc, 16);
 542         radeon_enc_code_ue(enc, 0x0);
 543         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 544
 545         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 546
 547         radeon_enc_byte_align(enc);
 548         radeon_enc_flush_headers(enc);
 549         *size_in_bytes = (enc->bits_output + 7) / 8;
 550         RADEON_ENC_END();
 551 }
 552
 553 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 554 {
 555         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 556         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 557         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 558         int i;
 559
 560         radeon_enc_reset(enc);
 561         radeon_enc_set_emulation_prevention(enc, false);
 562         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 563         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 564         radeon_enc_byte_align(enc);
 565         radeon_enc_set_emulation_prevention(enc, true);
 566         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 567         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 568         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 569         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 570         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 571         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 572         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 573         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 574         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 575         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 576
 577         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 578                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 579
 580         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 581                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 582                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 583         }
 584
 585         radeon_enc_code_ue(enc, 0x0);
 586         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 587         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 588         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 589         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 590         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 591         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 592         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 593         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 594         radeon_enc_code_ue(enc, 1);
 595         radeon_enc_code_ue(enc, 0x0);
 596         radeon_enc_code_ue(enc, 0x0);
 597         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 598         //Only support CTBSize 64
 599         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 600         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 601         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 602         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 603         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 604
 605         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 606         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 607         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 608         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 609
 610         radeon_enc_code_ue(enc, 1);
 611         radeon_enc_code_ue(enc, 1);
 612         radeon_enc_code_ue(enc, 0);
 613         radeon_enc_code_ue(enc, 0);
 614         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 615
 616         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 617
 618         radeon_enc_code_fixed_bits(enc, 0, 1);
 619         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 620
 621         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 622
 623         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 624
 625         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 626
 627         radeon_enc_byte_align(enc);
 628         radeon_enc_flush_headers(enc);
 629         *size_in_bytes = (enc->bits_output + 7) / 8;
 630         RADEON_ENC_END();
 631 }
 632
 633 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 634 {
 635         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 636         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 637         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 638         radeon_enc_reset(enc);
 639         radeon_enc_set_emulation_prevention(enc, false);
 640         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 641         radeon_enc_code_fixed_bits(enc, 0x68, 8);
 642         radeon_enc_byte_align(enc);
 643         radeon_enc_set_emulation_prevention(enc, true);
 644         radeon_enc_code_ue(enc, 0x0);
 645         radeon_enc_code_ue(enc, 0x0);
 646         radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
 647         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 648         radeon_enc_code_ue(enc, 0x0);
 649         radeon_enc_code_ue(enc, 0x0);
 650         radeon_enc_code_ue(enc, 0x0);
 651         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 652         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 653         radeon_enc_code_se(enc, 0x0);
 654         radeon_enc_code_se(enc, 0x0);
 655         radeon_enc_code_se(enc, 0x0);
 656         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 657         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 658         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 659
 660         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 661
 662         radeon_enc_byte_align(enc);
 663         radeon_enc_flush_headers(enc);
 664         *size_in_bytes = (enc->bits_output + 7) / 8;
 665         RADEON_ENC_END();
 666 }
 667
 668 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 669 {
 670         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 671         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 672         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 673         radeon_enc_reset(enc);
 674         radeon_enc_set_emulation_prevention(enc, false);
 675         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 676         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 677         radeon_enc_byte_align(enc);
 678         radeon_enc_set_emulation_prevention(enc, true);
 679         radeon_enc_code_ue(enc, 0x0);
 680         radeon_enc_code_ue(enc, 0x0);
 681         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 682         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 683         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 684         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 685         radeon_enc_code_ue(enc, 0x0);
 686         radeon_enc_code_ue(enc, 0x0);
 687         radeon_enc_code_se(enc, 0x0);
 688         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 689         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 690         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 691         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 692         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 693         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 694         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 695         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 696         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 697         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 698         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 699         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 700         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 701         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 702
 703         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 704                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 705                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 706         }
 707
 708         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 709         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 710         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 711         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 712
 713         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 714
 715         radeon_enc_byte_align(enc);
 716         radeon_enc_flush_headers(enc);
 717         *size_in_bytes = (enc->bits_output + 7) / 8;
 718         RADEON_ENC_END();
 719 }
 720
 721 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
 722 {
 723         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 724         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
 725         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 726         int i;
 727
 728         radeon_enc_reset(enc);
 729         radeon_enc_set_emulation_prevention(enc, false);
 730         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 731         radeon_enc_code_fixed_bits(enc, 0x4001, 16);
 732         radeon_enc_byte_align(enc);
 733         radeon_enc_set_emulation_prevention(enc, true);
 734
 735         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 736         radeon_enc_code_fixed_bits(enc, 0x3, 2);
 737         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 738         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 739         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 740         radeon_enc_code_fixed_bits(enc, 0xffff, 16);
 741         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 742         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 743         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 744         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 745         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 746         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 747         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 748
 749         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 750                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 751
 752         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 753                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 754                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 755         }
 756
 757         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 758         radeon_enc_code_ue(enc, 0x1);
 759         radeon_enc_code_ue(enc, 0x0);
 760         radeon_enc_code_ue(enc, 0x0);
 761
 762         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 763         radeon_enc_code_ue(enc, 0x0);
 764         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 765         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 766
 767         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 768
 769         radeon_enc_byte_align(enc);
 770         radeon_enc_flush_headers(enc);
 771         *size_in_bytes = (enc->bits_output + 7) / 8;
 772         RADEON_ENC_END();
 773 }
 774
 775 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
 776 {
 777         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 778         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
 779         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 780         radeon_enc_reset(enc);
 781         radeon_enc_set_emulation_prevention(enc, false);
 782         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 783         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 784         radeon_enc_code_fixed_bits(enc, 35, 6);
 785         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 786         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 787         radeon_enc_byte_align(enc);
 788         radeon_enc_set_emulation_prevention(enc, true);
 789         switch(enc->enc_pic.picture_type) {
 790                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 791                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 792                         radeon_enc_code_fixed_bits(enc, 0x00, 3);
 793                         break;
 794                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 795                         radeon_enc_code_fixed_bits(enc, 0x01, 3);
 796                         break;
 797                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 798                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 799                         break;
 800                 default:
 801                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 802         }
 803
 804     radeon_enc_code_fixed_bits(enc, 0x1, 1);
 805
 806         radeon_enc_byte_align(enc);
 807         radeon_enc_flush_headers(enc);
 808         *size_in_bytes = (enc->bits_output + 7) / 8;
 809         RADEON_ENC_END();
 810 }
 811
 812 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 813 {
 814         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 815         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 816         unsigned int inst_index = 0;
 817         unsigned int bit_index = 0;
 818         unsigned int bits_copied = 0;
 819         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 820         radeon_enc_reset(enc);
 821         radeon_enc_set_emulation_prevention(enc, false);
 822
 823         if (enc->enc_pic.is_idr)
 824                 radeon_enc_code_fixed_bits(enc, 0x65, 8);
 825         else if (enc->enc_pic.not_referenced)
 826                 radeon_enc_code_fixed_bits(enc, 0x01, 8);
 827         else
 828                 radeon_enc_code_fixed_bits(enc, 0x41, 8);
 829
 830         radeon_enc_flush_headers(enc);
 831         bit_index ++;
 832         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 833         num_bits[inst_index] = enc->bits_output - bits_copied;
 834         bits_copied = enc->bits_output;
 835         inst_index++;
 836
 837         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
 838         inst_index++;
 839
 840         switch(enc->enc_pic.picture_type) {
 841                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 842                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 843                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 844                         break;
 845                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 846                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 847                         radeon_enc_code_fixed_bits(enc, 0x06, 5);
 848                         break;
 849                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 850                         radeon_enc_code_fixed_bits(enc, 0x07, 5);
 851                         break;
 852                 default:
 853                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 854         }
 855
 856         radeon_enc_code_ue(enc, 0x0);
 857         radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
 858
 859         if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
 860                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 861                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
 862         }
 863
 864         if (enc->enc_pic.is_idr)
 865                 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
 866
 867         enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
 868
 869         if (enc->enc_pic.pic_order_cnt_type == 0)
 870                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
 871
 872         if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
 873                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 874
 875                 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
 876                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 877                         radeon_enc_code_ue(enc, 0x0);
 878                         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
 879                         radeon_enc_code_ue(enc, 0x3);
 880                 } else
 881                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 882         }
 883
 884         if (enc->enc_pic.is_idr) {
 885                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 886                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 887         } else
 888                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 889
 890         if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
 891                 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
 892
 893         radeon_enc_flush_headers(enc);
 894         bit_index ++;
 895         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 896         num_bits[inst_index] = enc->bits_output - bits_copied;
 897         bits_copied = enc->bits_output;
 898         inst_index++;
 899
 900         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 901         inst_index++;
 902
 903         radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
 904
 905         if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
 906                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 907                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
 908         }
 909
 910         radeon_enc_flush_headers(enc);
 911         bit_index ++;
 912         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 913         num_bits[inst_index] = enc->bits_output - bits_copied;
 914         bits_copied = enc->bits_output;
 915         inst_index++;
 916
 917         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 918
 919         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 920                 RADEON_ENC_CS(0x00000000);
 921
 922         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 923                 RADEON_ENC_CS(instruction[j]);
 924                 RADEON_ENC_CS(num_bits[j]);
 925         }
 926
 927         RADEON_ENC_END();
 928 }
 929
 930 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 931 {
 932         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 933         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 934         unsigned int inst_index = 0;
 935         unsigned int bit_index = 0;
 936         unsigned int bits_copied = 0;
 937         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 938         radeon_enc_reset(enc);
 939         radeon_enc_set_emulation_prevention(enc, false);
 940
 941         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 942         radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
 943         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 944         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 945
 946         radeon_enc_flush_headers(enc);
 947         bit_index ++;
 948         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 949         num_bits[inst_index] = enc->bits_output - bits_copied;
 950         bits_copied = enc->bits_output;
 951         inst_index++;
 952
 953         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
 954         inst_index++;
 955
 956         if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
 957                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 958
 959         radeon_enc_code_ue(enc, 0x0);
 960
 961         radeon_enc_flush_headers(enc);
 962         bit_index ++;
 963         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 964         num_bits[inst_index] = enc->bits_output - bits_copied;
 965         bits_copied = enc->bits_output;
 966         inst_index++;
 967
 968         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
 969         inst_index++;
 970
 971         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
 972         inst_index++;
 973
 974         switch(enc->enc_pic.picture_type) {
 975                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 976                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 977                         radeon_enc_code_ue(enc, 0x2);
 978                         break;
 979                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 980                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 981                         radeon_enc_code_ue(enc, 0x1);
 982                         break;
 983                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 984                         radeon_enc_code_ue(enc, 0x0);
 985                         break;
 986                 default:
 987                         radeon_enc_code_ue(enc, 0x1);
 988         }
 989
 990         if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
 991                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
 992                 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
 993                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 994                 else {
 995                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 996                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 997                         radeon_enc_code_ue(enc, 0x0);
 998                         radeon_enc_code_ue(enc, 0x0);
 999                 }
1000         }
1001
1002         if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
1003                 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
1004                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1005                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
1006                 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
1007         }
1008
1009         radeon_enc_flush_headers(enc);
1010         bit_index ++;
1011         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1012         num_bits[inst_index] = enc->bits_output - bits_copied;
1013         bits_copied = enc->bits_output;
1014         inst_index++;
1015
1016         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1017         inst_index++;
1018
1019         if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
1020                 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)){
1021                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
1022
1023                 radeon_enc_flush_headers(enc);
1024                 bit_index ++;
1025                 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1026                 num_bits[inst_index] = enc->bits_output - bits_copied;
1027                 bits_copied = enc->bits_output;
1028                 inst_index++;
1029         }
1030
1031         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1032
1033         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
1034                 RADEON_ENC_CS(0x00000000);
1035
1036         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1037                 RADEON_ENC_CS(instruction[j]);
1038                 RADEON_ENC_CS(num_bits[j]);
1039         }
1040
1041         RADEON_ENC_END();
1042 }
1043
1044 static void radeon_enc_ctx(struct radeon_encoder *enc)
1045 {
1046         enc->enc_pic.ctx_buf.swizzle_mode = 0;
1047         enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
1048         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
1049         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
1050
1051         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER);
1052         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
1053         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1054         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1055         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1056         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1057         /* reconstructed_picture_1_luma_offset */
1058         RADEON_ENC_CS(0x00000000);
1059         /* reconstructed_picture_1_chroma_offset */
1060         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
1061         /* reconstructed_picture_2_luma_offset */
1062         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
1063         /* reconstructed_picture_2_chroma_offset */
1064         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
1065
1066         for (int i = 0; i < 136 ; i++)
1067                 RADEON_ENC_CS(0x00000000);
1068
1069         RADEON_ENC_END();
1070 }
1071
1072 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1073 {
1074         enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1075         enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1076         enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
1077
1078         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
1079         RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1080         RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1081         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1082         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1083         RADEON_ENC_END();
1084 }
1085
1086 static void radeon_enc_feedback(struct radeon_encoder *enc)
1087 {
1088         enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1089         enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1090         enc->enc_pic.fb_buf.feedback_data_size = 40;
1091
1092         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER);
1093         RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1094         RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1095         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1096         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1097         RADEON_ENC_END();
1098 }
1099
1100 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1101 {
1102         enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
1103         enc->enc_pic.intra_ref.offset = 0;
1104         enc->enc_pic.intra_ref.region_size = 0;
1105
1106         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH);
1107         RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
1108         RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
1109         RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
1110         RADEON_ENC_END();
1111 }
1112
1113 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
1114 {
1115         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1116                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
1117                 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
1118                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
1119                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
1120                 enc->enc_pic.rc_per_pic.max_au_size = 0;
1121                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable;
1122                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
1123                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd;
1124         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1125                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
1126                 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
1127                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
1128                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
1129                 enc->enc_pic.rc_per_pic.max_au_size = 0;
1130                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
1131                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
1132                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
1133         }
1134
1135         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE);
1136         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
1137         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
1138         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
1139         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
1140         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1141         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1142         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1143         RADEON_ENC_END();
1144 }
1145
1146 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1147 {
1148         switch(enc->enc_pic.picture_type) {
1149                 case PIPE_H264_ENC_PICTURE_TYPE_I:
1150                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
1151                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1152                         break;
1153                 case PIPE_H264_ENC_PICTURE_TYPE_P:
1154                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1155                         break;
1156                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
1157                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1158                         break;
1159                 case PIPE_H264_ENC_PICTURE_TYPE_B:
1160                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1161                         break;
1162                 default:
1163                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1164         }
1165
1166         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1167         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1168         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1169         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1170
1171         if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
1172                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1173         else
1174                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1175
1176         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1177
1178         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1179         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1180         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1181         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1182         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1183         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1184         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1185         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1186         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1187         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1188         RADEON_ENC_END();
1189 }
1190
1191 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1192 {
1193         switch(enc->enc_pic.picture_type) {
1194                 case PIPE_H265_ENC_PICTURE_TYPE_I:
1195                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
1196                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1197                         break;
1198                 case PIPE_H265_ENC_PICTURE_TYPE_P:
1199                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1200                         break;
1201                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
1202                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1203                         break;
1204                 case PIPE_H265_ENC_PICTURE_TYPE_B:
1205                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1206                         break;
1207                 default:
1208                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1209         }
1210
1211         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1212         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1213         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1214         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1215
1216         if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1217                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1218         else
1219                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1220
1221         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1222
1223         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1224         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1225         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1226         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1227         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1228         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1229         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1230         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1231         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1232         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1233         RADEON_ENC_END();
1234 }
1235
1236 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1237 {
1238         enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1239         enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1240         enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1241         enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1242
1243         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS);
1244         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1245         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1246         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1247         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1248         RADEON_ENC_END();
1249 }
1250
1251 static void radeon_enc_op_init(struct radeon_encoder *enc)
1252 {
1253         RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1254         RADEON_ENC_END();
1255 }
1256
1257 static void radeon_enc_op_close(struct radeon_encoder *enc)
1258 {
1259         RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1260         RADEON_ENC_END();
1261 }
1262
1263 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1264 {
1265         RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1266         RADEON_ENC_END();
1267 }
1268
1269 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1270 {
1271         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1272         RADEON_ENC_END();
1273 }
1274
1275 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1276 {
1277         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1278         RADEON_ENC_END();
1279 }
1280
1281 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1282 {
1283         RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1284         RADEON_ENC_END();
1285 }
1286
1287 static void begin(struct radeon_encoder *enc, struct pipe_picture_desc *pic)
1288 {
1289         radeon_enc_session_info(enc);
1290         enc->total_task_size = 0;
1291         radeon_enc_task_info(enc, enc->need_feedback);
1292         radeon_enc_op_init(enc);
1293
1294         if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1295                 radeon_enc_session_init(enc);
1296                 radeon_enc_slice_control(enc);
1297                 radeon_enc_spec_misc(enc);
1298                 radeon_enc_deblocking_filter_h264(enc);
1299         } else if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1300                 radeon_enc_session_init_hevc(enc);
1301                 radeon_enc_slice_control_hevc(enc);
1302                 radeon_enc_spec_misc_hevc(enc, pic);
1303                 radeon_enc_deblocking_filter_hevc(enc, pic);
1304         }
1305
1306         radeon_enc_layer_control(enc);
1307         radeon_enc_rc_session_init(enc, pic);
1308         radeon_enc_quality_params(enc);
1309         radeon_enc_layer_select(enc);
1310         radeon_enc_rc_layer_init(enc, pic);
1311         radeon_enc_layer_select(enc);
1312         radeon_enc_rc_per_pic(enc, pic);
1313         radeon_enc_op_init_rc(enc);
1314         radeon_enc_op_init_rc_vbv(enc);
1315         *enc->p_task_size = (enc->total_task_size);
1316 }
1317
1318 static void encode(struct radeon_encoder *enc)
1319 {
1320         radeon_enc_session_info(enc);
1321         enc->total_task_size = 0;
1322         radeon_enc_task_info(enc, enc->need_feedback);
1323
1324         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1325                 if (enc->enc_pic.is_idr) {
1326                         radeon_enc_nalu_sps(enc);
1327                         radeon_enc_nalu_pps(enc);
1328                 }
1329                 radeon_enc_slice_header(enc);
1330                 radeon_enc_encode_params(enc);
1331                 radeon_enc_encode_params_h264(enc);
1332         } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1333                 radeon_enc_nalu_aud_hevc(enc);
1334                 if (enc->enc_pic.is_idr) {
1335                         radeon_enc_nalu_vps(enc);
1336                         radeon_enc_nalu_pps_hevc(enc);
1337                         radeon_enc_nalu_sps_hevc(enc);
1338                 }
1339                 radeon_enc_slice_header_hevc(enc);
1340                 radeon_enc_encode_params_hevc(enc);
1341         }
1342
1343         radeon_enc_ctx(enc);
1344         radeon_enc_bitstream(enc);
1345         radeon_enc_feedback(enc);
1346         radeon_enc_intra_refresh(enc);
1347
1348         radeon_enc_op_speed(enc);
1349         radeon_enc_op_enc(enc);
1350         *enc->p_task_size = (enc->total_task_size);
1351 }
1352
1353 static void destroy(struct radeon_encoder *enc)
1354 {
1355         radeon_enc_session_info(enc);
1356         enc->total_task_size = 0;
1357         radeon_enc_task_info(enc, enc->need_feedback);
1358         radeon_enc_op_close(enc);
1359         *enc->p_task_size = (enc->total_task_size);
1360 }
1361
1362 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1363 {
1364         enc->begin = begin;
1365         enc->encode = encode;
1366         enc->destroy = destroy;
1367 }