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[mesa.git] / src / gallium / drivers / radeon / radeon_vcn_enc_1_2.c
1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdio.h>
29
30 #include "pipe/p_video_codec.h"
31
32 #include "util/u_video.h"
33
34 #include "si_pipe.h"
35 #include "radeon_video.h"
36 #include "radeon_vcn_enc.h"
37
38 static void radeon_enc_session_info(struct radeon_encoder *enc)
39 {
40 unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
41 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
42 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
43 RADEON_ENC_CS(interface_version);
44 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
45 RADEON_ENC_END();
46 }
47
48 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
49 {
50 enc->enc_pic.task_info.task_id++;
51
52 if (need_feedback)
53 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
54 else
55 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
56
57 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
58 enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
59 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
60 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
61 RADEON_ENC_END();
62 }
63
64 static void radeon_enc_session_init(struct radeon_encoder *enc)
65 {
66 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
67 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
68 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
69 enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
70 enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
71 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
72 enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
73
74 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
75 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
76 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
77 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
78 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
79 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
80 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
81 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
82 RADEON_ENC_END();
83 }
84
85 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
86 {
87 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
88 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
89 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
90 enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
91 enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
92 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
93 enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
94
95 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
96 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
97 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
98 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
99 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
100 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
101 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
102 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
103 RADEON_ENC_END();
104 }
105
106 static void radeon_enc_layer_control(struct radeon_encoder *enc)
107 {
108 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
109 enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
110
111 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
112 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
113 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
114 RADEON_ENC_END();
115 }
116
117 static void radeon_enc_layer_select(struct radeon_encoder *enc)
118 {
119 enc->enc_pic.layer_sel.temporal_layer_index = 0;
120
121 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
122 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
123 RADEON_ENC_END();
124 }
125
126 static void radeon_enc_slice_control(struct radeon_encoder *enc)
127 {
128 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
129 enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
130
131 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
132 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
133 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
134 RADEON_ENC_END();
135 }
136
137 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
138 {
139 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
140 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
141 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
142
143 RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
144 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
145 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
146 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
147 RADEON_ENC_END();
148 }
149
150 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
151 {
152 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
153 enc->enc_pic.spec_misc.cabac_enable = 0;
154 enc->enc_pic.spec_misc.cabac_init_idc = 0;
155 enc->enc_pic.spec_misc.half_pel_enabled = 1;
156 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
157 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
158 enc->enc_pic.spec_misc.level_idc = enc->base.level;
159
160 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
161 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
162 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
163 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
164 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
165 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
166 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
167 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
168 RADEON_ENC_END();
169 }
170
171 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
172 {
173 RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
174 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
175 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
176 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
177 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
178 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
179 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
180 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
181 RADEON_ENC_END();
182 }
183
184 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
185 {
186 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT);
187 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
188 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
189 RADEON_ENC_END();
190 }
191
192 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
193 {
194 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT);
195 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
196 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
197 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
198 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
199 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
200 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
201 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
202 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
203 RADEON_ENC_END();
204 }
205
206 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
207 {
208 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
209 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
210 enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
211 enc->enc_pic.h264_deblock.cb_qp_offset = 0;
212 enc->enc_pic.h264_deblock.cr_qp_offset = 0;
213
214 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER);
215 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
216 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
217 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
218 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
219 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
220 RADEON_ENC_END();
221 }
222
223 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
224 {
225 RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER);
226 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
227 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
228 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
229 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
230 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
231 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
232 RADEON_ENC_END();
233 }
234
235 static void radeon_enc_quality_params(struct radeon_encoder *enc)
236 {
237 enc->enc_pic.quality_params.vbaq_mode = 0;
238 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
239 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
240
241 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS);
242 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
243 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
244 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
245 RADEON_ENC_END();
246 }
247
248 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
249 {
250 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
251 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
252 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
253 radeon_enc_reset(enc);
254 radeon_enc_set_emulation_prevention(enc, false);
255 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
256 radeon_enc_code_fixed_bits(enc, 0x67, 8);
257 radeon_enc_byte_align(enc);
258 radeon_enc_set_emulation_prevention(enc, true);
259 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
260 radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
261 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
262 radeon_enc_code_ue(enc, 0x0);
263
264 if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
265 enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
266 enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
267 enc->enc_pic.spec_misc.profile_idc == 138) {
268 radeon_enc_code_ue(enc, 0x1);
269 radeon_enc_code_ue(enc, 0x0);
270 radeon_enc_code_ue(enc, 0x0);
271 radeon_enc_code_fixed_bits(enc, 0x0, 2);
272 }
273
274 radeon_enc_code_ue(enc, 1);
275 radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
276
277 if (enc->enc_pic.pic_order_cnt_type == 0)
278 radeon_enc_code_ue(enc, 1);
279
280 radeon_enc_code_ue(enc, (enc->base.max_references + 1));
281 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
282 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
283 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
284 bool progressive_only = true;
285 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
286
287 if (!progressive_only)
288 radeon_enc_code_fixed_bits(enc, 0x0, 1);
289
290 radeon_enc_code_fixed_bits(enc, 0x1, 1);
291
292 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
293 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
294 radeon_enc_code_fixed_bits(enc, 0x1, 1);
295 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
296 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
297 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
298 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
299 } else
300 radeon_enc_code_fixed_bits(enc, 0x0, 1);
301
302 radeon_enc_code_fixed_bits(enc, 0x1, 1);
303 radeon_enc_code_fixed_bits(enc, 0x0, 1);
304 radeon_enc_code_fixed_bits(enc, 0x0, 1);
305 radeon_enc_code_fixed_bits(enc, 0x0, 1);
306 radeon_enc_code_fixed_bits(enc, 0x0, 1);
307 radeon_enc_code_fixed_bits(enc, 0x0, 1);
308 radeon_enc_code_fixed_bits(enc, 0x0, 1);
309 radeon_enc_code_fixed_bits(enc, 0x0, 1);
310 radeon_enc_code_fixed_bits(enc, 0x0, 1);
311 radeon_enc_code_fixed_bits(enc, 0x1, 1);
312 radeon_enc_code_fixed_bits(enc, 0x1, 1);
313 radeon_enc_code_ue(enc, 0x0);
314 radeon_enc_code_ue(enc, 0x0);
315 radeon_enc_code_ue(enc, 16);
316 radeon_enc_code_ue(enc, 16);
317 radeon_enc_code_ue(enc, 0x0);
318 radeon_enc_code_ue(enc, (enc->base.max_references + 1));
319
320 radeon_enc_code_fixed_bits(enc, 0x1, 1);
321
322 radeon_enc_byte_align(enc);
323 radeon_enc_flush_headers(enc);
324 *size_in_bytes = (enc->bits_output + 7) / 8;
325 RADEON_ENC_END();
326 }
327
328 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
329 {
330 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
331 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
332 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
333 int i;
334
335 radeon_enc_reset(enc);
336 radeon_enc_set_emulation_prevention(enc, false);
337 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
338 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
339 radeon_enc_byte_align(enc);
340 radeon_enc_set_emulation_prevention(enc, true);
341 radeon_enc_code_fixed_bits(enc, 0x0, 4);
342 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
343 radeon_enc_code_fixed_bits(enc, 0x1, 1);
344 radeon_enc_code_fixed_bits(enc, 0x0, 2);
345 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
346 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
347 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
348 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
349 radeon_enc_code_fixed_bits(enc, 0x0, 16);
350 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
351
352 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
353 radeon_enc_code_fixed_bits(enc, 0x0, 2);
354
355 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
356 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
357 radeon_enc_code_fixed_bits(enc, 0x0, 2);
358 }
359
360 radeon_enc_code_ue(enc, 0x0);
361 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
362 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
363 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
364 radeon_enc_code_fixed_bits(enc, 0x0, 1);
365 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
366 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
367 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
368 radeon_enc_code_fixed_bits(enc, 0x0, 1);
369 radeon_enc_code_ue(enc, 1);
370 radeon_enc_code_ue(enc, 0x0);
371 radeon_enc_code_ue(enc, 0x0);
372 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
373 //Only support CTBSize 64
374 radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
375 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
376 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
377 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
378 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
379
380 radeon_enc_code_fixed_bits(enc, 0x0, 1);
381 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
382 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
383 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
384
385 radeon_enc_code_ue(enc, 1);
386 radeon_enc_code_ue(enc, 1);
387 radeon_enc_code_ue(enc, 0);
388 radeon_enc_code_ue(enc, 0);
389 radeon_enc_code_fixed_bits(enc, 0x1, 1);
390
391 radeon_enc_code_fixed_bits(enc, 0x0, 1);
392
393 radeon_enc_code_fixed_bits(enc, 0, 1);
394 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
395
396 radeon_enc_code_fixed_bits(enc, 0x0, 1);
397
398 radeon_enc_code_fixed_bits(enc, 0x0, 1);
399
400 radeon_enc_code_fixed_bits(enc, 0x1, 1);
401
402 radeon_enc_byte_align(enc);
403 radeon_enc_flush_headers(enc);
404 *size_in_bytes = (enc->bits_output + 7) / 8;
405 RADEON_ENC_END();
406 }
407
408 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
409 {
410 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
411 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
412 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
413 radeon_enc_reset(enc);
414 radeon_enc_set_emulation_prevention(enc, false);
415 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
416 radeon_enc_code_fixed_bits(enc, 0x68, 8);
417 radeon_enc_byte_align(enc);
418 radeon_enc_set_emulation_prevention(enc, true);
419 radeon_enc_code_ue(enc, 0x0);
420 radeon_enc_code_ue(enc, 0x0);
421 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
422 radeon_enc_code_fixed_bits(enc, 0x0, 1);
423 radeon_enc_code_ue(enc, 0x0);
424 radeon_enc_code_ue(enc, 0x0);
425 radeon_enc_code_ue(enc, 0x0);
426 radeon_enc_code_fixed_bits(enc, 0x0, 1);
427 radeon_enc_code_fixed_bits(enc, 0x0, 2);
428 radeon_enc_code_se(enc, 0x0);
429 radeon_enc_code_se(enc, 0x0);
430 radeon_enc_code_se(enc, 0x0);
431 radeon_enc_code_fixed_bits(enc, 0x1, 1);
432 radeon_enc_code_fixed_bits(enc, 0x0, 1);
433 radeon_enc_code_fixed_bits(enc, 0x0, 1);
434
435 radeon_enc_code_fixed_bits(enc, 0x1, 1);
436
437 radeon_enc_byte_align(enc);
438 radeon_enc_flush_headers(enc);
439 *size_in_bytes = (enc->bits_output + 7) / 8;
440 RADEON_ENC_END();
441 }
442
443 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
444 {
445 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
446 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
447 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
448 radeon_enc_reset(enc);
449 radeon_enc_set_emulation_prevention(enc, false);
450 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
451 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
452 radeon_enc_byte_align(enc);
453 radeon_enc_set_emulation_prevention(enc, true);
454 radeon_enc_code_ue(enc, 0x0);
455 radeon_enc_code_ue(enc, 0x0);
456 radeon_enc_code_fixed_bits(enc, 0x1, 1);
457 radeon_enc_code_fixed_bits(enc, 0x0, 4);
458 radeon_enc_code_fixed_bits(enc, 0x0, 1);
459 radeon_enc_code_fixed_bits(enc, 0x1, 1);
460 radeon_enc_code_ue(enc, 0x0);
461 radeon_enc_code_ue(enc, 0x0);
462 radeon_enc_code_se(enc, 0x0);
463 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
464 radeon_enc_code_fixed_bits(enc, 0x0, 1);
465 radeon_enc_code_fixed_bits(enc, 0x0, 1);
466 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
467 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
468 radeon_enc_code_fixed_bits(enc, 0x0, 1);
469 radeon_enc_code_fixed_bits(enc, 0x0, 2);
470 radeon_enc_code_fixed_bits(enc, 0x0, 1);
471 radeon_enc_code_fixed_bits(enc, 0x0, 1);
472 radeon_enc_code_fixed_bits(enc, 0x0, 1);
473 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
474 radeon_enc_code_fixed_bits(enc, 0x1, 1);
475 radeon_enc_code_fixed_bits(enc, 0x0, 1);
476 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
477
478 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
479 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
480 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
481 }
482
483 radeon_enc_code_fixed_bits(enc, 0x0, 1);
484 radeon_enc_code_fixed_bits(enc, 0x0, 1);
485 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
486 radeon_enc_code_fixed_bits(enc, 0x0, 2);
487
488 radeon_enc_code_fixed_bits(enc, 0x1, 1);
489
490 radeon_enc_byte_align(enc);
491 radeon_enc_flush_headers(enc);
492 *size_in_bytes = (enc->bits_output + 7) / 8;
493 RADEON_ENC_END();
494 }
495
496 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
497 {
498 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
499 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
500 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
501 int i;
502
503 radeon_enc_reset(enc);
504 radeon_enc_set_emulation_prevention(enc, false);
505 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
506 radeon_enc_code_fixed_bits(enc, 0x4001, 16);
507 radeon_enc_byte_align(enc);
508 radeon_enc_set_emulation_prevention(enc, true);
509
510 radeon_enc_code_fixed_bits(enc, 0x0, 4);
511 radeon_enc_code_fixed_bits(enc, 0x3, 2);
512 radeon_enc_code_fixed_bits(enc, 0x0, 6);
513 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
514 radeon_enc_code_fixed_bits(enc, 0x1, 1);
515 radeon_enc_code_fixed_bits(enc, 0xffff, 16);
516 radeon_enc_code_fixed_bits(enc, 0x0, 2);
517 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
518 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
519 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
520 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
521 radeon_enc_code_fixed_bits(enc, 0x0, 16);
522 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
523
524 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
525 radeon_enc_code_fixed_bits(enc, 0x0, 2);
526
527 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
528 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
529 radeon_enc_code_fixed_bits(enc, 0x0, 2);
530 }
531
532 radeon_enc_code_fixed_bits(enc, 0x0, 1);
533 radeon_enc_code_ue(enc, 0x1);
534 radeon_enc_code_ue(enc, 0x0);
535 radeon_enc_code_ue(enc, 0x0);
536
537 radeon_enc_code_fixed_bits(enc, 0x0, 6);
538 radeon_enc_code_ue(enc, 0x0);
539 radeon_enc_code_fixed_bits(enc, 0x0, 1);
540 radeon_enc_code_fixed_bits(enc, 0x0, 1);
541
542 radeon_enc_code_fixed_bits(enc, 0x1, 1);
543
544 radeon_enc_byte_align(enc);
545 radeon_enc_flush_headers(enc);
546 *size_in_bytes = (enc->bits_output + 7) / 8;
547 RADEON_ENC_END();
548 }
549
550 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
551 {
552 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
553 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
554 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
555 radeon_enc_reset(enc);
556 radeon_enc_set_emulation_prevention(enc, false);
557 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
558 radeon_enc_code_fixed_bits(enc, 0x0, 1);
559 radeon_enc_code_fixed_bits(enc, 35, 6);
560 radeon_enc_code_fixed_bits(enc, 0x0, 6);
561 radeon_enc_code_fixed_bits(enc, 0x1, 3);
562 radeon_enc_byte_align(enc);
563 radeon_enc_set_emulation_prevention(enc, true);
564 switch(enc->enc_pic.picture_type) {
565 case PIPE_H265_ENC_PICTURE_TYPE_I:
566 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
567 radeon_enc_code_fixed_bits(enc, 0x00, 3);
568 break;
569 case PIPE_H265_ENC_PICTURE_TYPE_P:
570 radeon_enc_code_fixed_bits(enc, 0x01, 3);
571 break;
572 case PIPE_H265_ENC_PICTURE_TYPE_B:
573 radeon_enc_code_fixed_bits(enc, 0x02, 3);
574 break;
575 default:
576 radeon_enc_code_fixed_bits(enc, 0x02, 3);
577 }
578
579 radeon_enc_code_fixed_bits(enc, 0x1, 1);
580
581 radeon_enc_byte_align(enc);
582 radeon_enc_flush_headers(enc);
583 *size_in_bytes = (enc->bits_output + 7) / 8;
584 RADEON_ENC_END();
585 }
586
587 static void radeon_enc_slice_header(struct radeon_encoder *enc)
588 {
589 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
590 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
591 unsigned int inst_index = 0;
592 unsigned int bit_index = 0;
593 unsigned int bits_copied = 0;
594 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
595 radeon_enc_reset(enc);
596 radeon_enc_set_emulation_prevention(enc, false);
597
598 if (enc->enc_pic.is_idr)
599 radeon_enc_code_fixed_bits(enc, 0x65, 8);
600 else if (enc->enc_pic.not_referenced)
601 radeon_enc_code_fixed_bits(enc, 0x01, 8);
602 else
603 radeon_enc_code_fixed_bits(enc, 0x41, 8);
604
605 radeon_enc_flush_headers(enc);
606 bit_index ++;
607 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
608 num_bits[inst_index] = enc->bits_output - bits_copied;
609 bits_copied = enc->bits_output;
610 inst_index++;
611
612 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
613 inst_index++;
614
615 switch(enc->enc_pic.picture_type) {
616 case PIPE_H264_ENC_PICTURE_TYPE_I:
617 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
618 radeon_enc_code_fixed_bits(enc, 0x08, 7);
619 break;
620 case PIPE_H264_ENC_PICTURE_TYPE_P:
621 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
622 radeon_enc_code_fixed_bits(enc, 0x06, 5);
623 break;
624 case PIPE_H264_ENC_PICTURE_TYPE_B:
625 radeon_enc_code_fixed_bits(enc, 0x07, 5);
626 break;
627 default:
628 radeon_enc_code_fixed_bits(enc, 0x08, 7);
629 }
630
631 radeon_enc_code_ue(enc, 0x0);
632 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
633
634 if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
635 radeon_enc_code_fixed_bits(enc, 0x1, 1);
636 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
637 }
638
639 if (enc->enc_pic.is_idr)
640 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
641
642 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
643
644 if (enc->enc_pic.pic_order_cnt_type == 0)
645 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
646
647 if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
648 radeon_enc_code_fixed_bits(enc, 0x0, 1);
649
650 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
651 radeon_enc_code_fixed_bits(enc, 0x1, 1);
652 radeon_enc_code_ue(enc, 0x0);
653 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
654 radeon_enc_code_ue(enc, 0x3);
655 } else
656 radeon_enc_code_fixed_bits(enc, 0x0, 1);
657 }
658
659 if (enc->enc_pic.is_idr) {
660 radeon_enc_code_fixed_bits(enc, 0x0, 1);
661 radeon_enc_code_fixed_bits(enc, 0x0, 1);
662 } else
663 radeon_enc_code_fixed_bits(enc, 0x0, 1);
664
665 if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
666 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
667
668 radeon_enc_flush_headers(enc);
669 bit_index ++;
670 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
671 num_bits[inst_index] = enc->bits_output - bits_copied;
672 bits_copied = enc->bits_output;
673 inst_index++;
674
675 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
676 inst_index++;
677
678 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
679
680 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
681 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
682 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
683 }
684
685 radeon_enc_flush_headers(enc);
686 bit_index ++;
687 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
688 num_bits[inst_index] = enc->bits_output - bits_copied;
689 bits_copied = enc->bits_output;
690 inst_index++;
691
692 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
693
694 for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
695 RADEON_ENC_CS(0x00000000);
696
697 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
698 RADEON_ENC_CS(instruction[j]);
699 RADEON_ENC_CS(num_bits[j]);
700 }
701
702 RADEON_ENC_END();
703 }
704
705 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
706 {
707 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
708 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
709 unsigned int inst_index = 0;
710 unsigned int bit_index = 0;
711 unsigned int bits_copied = 0;
712 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
713 radeon_enc_reset(enc);
714 radeon_enc_set_emulation_prevention(enc, false);
715
716 radeon_enc_code_fixed_bits(enc, 0x0, 1);
717 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
718 radeon_enc_code_fixed_bits(enc, 0x0, 6);
719 radeon_enc_code_fixed_bits(enc, 0x1, 3);
720
721 radeon_enc_flush_headers(enc);
722 bit_index ++;
723 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
724 num_bits[inst_index] = enc->bits_output - bits_copied;
725 bits_copied = enc->bits_output;
726 inst_index++;
727
728 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
729 inst_index++;
730
731 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
732 radeon_enc_code_fixed_bits(enc, 0x0, 1);
733
734 radeon_enc_code_ue(enc, 0x0);
735
736 radeon_enc_flush_headers(enc);
737 bit_index ++;
738 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
739 num_bits[inst_index] = enc->bits_output - bits_copied;
740 bits_copied = enc->bits_output;
741 inst_index++;
742
743 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
744 inst_index++;
745
746 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
747 inst_index++;
748
749 switch(enc->enc_pic.picture_type) {
750 case PIPE_H265_ENC_PICTURE_TYPE_I:
751 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
752 radeon_enc_code_ue(enc, 0x2);
753 break;
754 case PIPE_H265_ENC_PICTURE_TYPE_P:
755 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
756 radeon_enc_code_ue(enc, 0x1);
757 break;
758 case PIPE_H265_ENC_PICTURE_TYPE_B:
759 radeon_enc_code_ue(enc, 0x0);
760 break;
761 default:
762 radeon_enc_code_ue(enc, 0x1);
763 }
764
765 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
766 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
767 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
768 radeon_enc_code_fixed_bits(enc, 0x1, 1);
769 else {
770 radeon_enc_code_fixed_bits(enc, 0x0, 1);
771 radeon_enc_code_fixed_bits(enc, 0x0, 1);
772 radeon_enc_code_ue(enc, 0x0);
773 radeon_enc_code_ue(enc, 0x0);
774 }
775 }
776
777 if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
778 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
779 radeon_enc_code_fixed_bits(enc, 0x0, 1);
780 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
781 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
782 }
783
784 radeon_enc_flush_headers(enc);
785 bit_index ++;
786 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
787 num_bits[inst_index] = enc->bits_output - bits_copied;
788 bits_copied = enc->bits_output;
789 inst_index++;
790
791 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
792 inst_index++;
793
794 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
795 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)){
796 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
797
798 radeon_enc_flush_headers(enc);
799 bit_index ++;
800 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
801 num_bits[inst_index] = enc->bits_output - bits_copied;
802 bits_copied = enc->bits_output;
803 inst_index++;
804 }
805
806 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
807
808 for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
809 RADEON_ENC_CS(0x00000000);
810
811 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
812 RADEON_ENC_CS(instruction[j]);
813 RADEON_ENC_CS(num_bits[j]);
814 }
815
816 RADEON_ENC_END();
817 }
818
819 static void radeon_enc_ctx(struct radeon_encoder *enc)
820 {
821 enc->enc_pic.ctx_buf.swizzle_mode = 0;
822 enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
823 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
824 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
825
826 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER);
827 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
828 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
829 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
830 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
831 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
832 /* reconstructed_picture_1_luma_offset */
833 RADEON_ENC_CS(0x00000000);
834 /* reconstructed_picture_1_chroma_offset */
835 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
836 /* reconstructed_picture_2_luma_offset */
837 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
838 /* reconstructed_picture_2_chroma_offset */
839 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
840
841 for (int i = 0; i < 136 ; i++)
842 RADEON_ENC_CS(0x00000000);
843
844 RADEON_ENC_END();
845 }
846
847 static void radeon_enc_bitstream(struct radeon_encoder *enc)
848 {
849 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
850 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
851 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
852
853 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
854 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
855 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
856 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
857 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
858 RADEON_ENC_END();
859 }
860
861 static void radeon_enc_feedback(struct radeon_encoder *enc)
862 {
863 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
864 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
865 enc->enc_pic.fb_buf.feedback_data_size = 40;
866
867 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER);
868 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
869 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
870 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
871 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
872 RADEON_ENC_END();
873 }
874
875 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
876 {
877 enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
878 enc->enc_pic.intra_ref.offset = 0;
879 enc->enc_pic.intra_ref.region_size = 0;
880
881 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH);
882 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
883 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
884 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
885 RADEON_ENC_END();
886 }
887
888 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
889 {
890 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE);
891 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
892 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
893 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
894 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
895 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
896 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
897 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
898 RADEON_ENC_END();
899 }
900
901 static void radeon_enc_encode_params(struct radeon_encoder *enc)
902 {
903 switch(enc->enc_pic.picture_type) {
904 case PIPE_H264_ENC_PICTURE_TYPE_I:
905 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
906 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
907 break;
908 case PIPE_H264_ENC_PICTURE_TYPE_P:
909 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
910 break;
911 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
912 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
913 break;
914 case PIPE_H264_ENC_PICTURE_TYPE_B:
915 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
916 break;
917 default:
918 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
919 }
920
921 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
922 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
923 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
924 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
925
926 if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
927 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
928 else
929 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
930
931 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
932
933 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
934 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
935 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
936 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
937 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
938 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
939 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
940 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
941 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
942 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
943 RADEON_ENC_END();
944 }
945
946 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
947 {
948 switch(enc->enc_pic.picture_type) {
949 case PIPE_H265_ENC_PICTURE_TYPE_I:
950 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
951 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
952 break;
953 case PIPE_H265_ENC_PICTURE_TYPE_P:
954 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
955 break;
956 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
957 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
958 break;
959 case PIPE_H265_ENC_PICTURE_TYPE_B:
960 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
961 break;
962 default:
963 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
964 }
965
966 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
967 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
968 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
969 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
970
971 if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
972 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
973 else
974 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
975
976 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
977
978 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
979 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
980 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
981 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
982 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
983 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
984 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
985 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
986 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
987 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
988 RADEON_ENC_END();
989 }
990
991 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
992 {
993 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
994 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
995 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
996 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
997
998 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS);
999 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1000 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1001 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1002 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1003 RADEON_ENC_END();
1004 }
1005
1006 static void radeon_enc_op_init(struct radeon_encoder *enc)
1007 {
1008 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1009 RADEON_ENC_END();
1010 }
1011
1012 static void radeon_enc_op_close(struct radeon_encoder *enc)
1013 {
1014 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1015 RADEON_ENC_END();
1016 }
1017
1018 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1019 {
1020 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1021 RADEON_ENC_END();
1022 }
1023
1024 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1025 {
1026 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1027 RADEON_ENC_END();
1028 }
1029
1030 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1031 {
1032 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1033 RADEON_ENC_END();
1034 }
1035
1036 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1037 {
1038 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1039 RADEON_ENC_END();
1040 }
1041
1042 static void begin(struct radeon_encoder *enc)
1043 {
1044 enc->session_info(enc);
1045 enc->total_task_size = 0;
1046 enc->task_info(enc, enc->need_feedback);
1047 enc->op_init(enc);
1048
1049 enc->session_init(enc);
1050 enc->slice_control(enc);
1051 enc->spec_misc(enc);
1052 enc->deblocking_filter(enc);
1053
1054 enc->layer_control(enc);
1055 enc->rc_session_init(enc);
1056 enc->quality_params(enc);
1057 enc->layer_select(enc);
1058 enc->rc_layer_init(enc);
1059 enc->layer_select(enc);
1060 enc->rc_per_pic(enc);
1061 enc->op_init_rc(enc);
1062 enc->op_init_rc_vbv(enc);
1063 *enc->p_task_size = (enc->total_task_size);
1064 }
1065
1066 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1067 {
1068 if (enc->enc_pic.is_idr) {
1069 enc->nalu_sps(enc);
1070 enc->nalu_pps(enc);
1071 }
1072 enc->slice_header(enc);
1073 enc->encode_params(enc);
1074 enc->encode_params_codec_spec(enc);
1075 }
1076
1077 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1078 {
1079 enc->nalu_aud(enc);
1080 if (enc->enc_pic.is_idr) {
1081 enc->nalu_vps(enc);
1082 enc->nalu_pps(enc);
1083 enc->nalu_sps(enc);
1084 }
1085 enc->slice_header(enc);
1086 enc->encode_params_codec_spec(enc);
1087 }
1088
1089 static void encode(struct radeon_encoder *enc)
1090 {
1091 enc->session_info(enc);
1092 enc->total_task_size = 0;
1093 enc->task_info(enc, enc->need_feedback);
1094
1095 enc->encode_headers(enc);
1096 enc->ctx(enc);
1097 enc->bitstream(enc);
1098 enc->feedback(enc);
1099 enc->intra_refresh(enc);
1100
1101 enc->op_speed(enc);
1102 enc->op_enc(enc);
1103 *enc->p_task_size = (enc->total_task_size);
1104 }
1105
1106 static void destroy(struct radeon_encoder *enc)
1107 {
1108 enc->session_info(enc);
1109 enc->total_task_size = 0;
1110 enc->task_info(enc, enc->need_feedback);
1111 enc->op_close(enc);
1112 *enc->p_task_size = (enc->total_task_size);
1113 }
1114
1115 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1116 {
1117 enc->begin = begin;
1118 enc->encode = encode;
1119 enc->destroy = destroy;
1120 enc->session_info = radeon_enc_session_info;
1121 enc->task_info = radeon_enc_task_info;
1122 enc->layer_control = radeon_enc_layer_control;
1123 enc->layer_select = radeon_enc_layer_select;
1124 enc->rc_session_init = radeon_enc_rc_session_init;
1125 enc->rc_layer_init = radeon_enc_rc_layer_init;
1126 enc->quality_params = radeon_enc_quality_params;
1127 enc->ctx = radeon_enc_ctx;
1128 enc->bitstream = radeon_enc_bitstream;
1129 enc->feedback = radeon_enc_feedback;
1130 enc->intra_refresh = radeon_enc_intra_refresh;
1131 enc->rc_per_pic = radeon_enc_rc_per_pic;
1132 enc->encode_params = radeon_enc_encode_params;
1133 enc->op_init = radeon_enc_op_init;
1134 enc->op_close = radeon_enc_op_close;
1135 enc->op_enc = radeon_enc_op_enc;
1136 enc->op_init_rc = radeon_enc_op_init_rc;
1137 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1138 enc->op_speed = radeon_enc_op_speed;
1139
1140 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1141 enc->session_init = radeon_enc_session_init;
1142 enc->slice_control = radeon_enc_slice_control;
1143 enc->spec_misc = radeon_enc_spec_misc;
1144 enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1145 enc->nalu_sps = radeon_enc_nalu_sps;
1146 enc->nalu_pps = radeon_enc_nalu_pps;
1147 enc->slice_header = radeon_enc_slice_header;
1148 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1149 enc->encode_headers = radeon_enc_headers_h264;
1150 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1151 enc->session_init = radeon_enc_session_init_hevc;
1152 enc->slice_control = radeon_enc_slice_control_hevc;
1153 enc->spec_misc = radeon_enc_spec_misc_hevc;
1154 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1155 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1156 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1157 enc->nalu_vps = radeon_enc_nalu_vps;
1158 enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1159 enc->slice_header = radeon_enc_slice_header_hevc;
1160 enc->encode_params_codec_spec = radeon_enc_encode_params_hevc;
1161 enc->encode_headers = radeon_enc_headers_hevc;
1162 }
1163 }