1 /**************************************************************************
3 * Copyright 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "pipe/p_video_codec.h"
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
35 #include "vl/vl_video_buffer.h"
37 #include "r600_pipe_common.h"
38 #include "radeon_video.h"
39 #include "radeon_vcn_enc.h"
41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
42 #define RADEON_ENC_BEGIN(cmd) { \
43 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
45 #define RADEON_ENC_READ(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
46 #define RADEON_ENC_WRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
47 #define RADEON_ENC_READWRITE(buf, domain, off) radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
49 enc->total_task_size += *begin;}
51 static const unsigned profiles
[7] = { 66, 77, 88, 100, 110, 122, 244 };
53 static void radeon_enc_add_buffer(struct radeon_encoder
*enc
, struct pb_buffer
*buf
,
54 enum radeon_bo_usage usage
, enum radeon_bo_domain domain
,
57 enc
->ws
->cs_add_buffer(enc
->cs
, buf
, usage
| RADEON_USAGE_SYNCHRONIZED
,
58 domain
, RADEON_PRIO_VCE
);
60 addr
= enc
->ws
->buffer_get_virtual_address(buf
);
62 RADEON_ENC_CS(addr
>> 32);
66 static void radeon_enc_session_info(struct radeon_encoder
*enc
)
68 unsigned int interface_version
= ((RENCODE_FW_INTERFACE_MAJOR_VERSION
<< RENCODE_IF_MAJOR_VERSION_SHIFT
) |
69 (RENCODE_FW_INTERFACE_MINOR_VERSION
<< RENCODE_IF_MINOR_VERSION_SHIFT
));
70 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO
);
71 RADEON_ENC_CS(interface_version
);
72 RADEON_ENC_READWRITE(enc
->si
->res
->buf
, enc
->si
->res
->domains
, 0x0);
76 static void radeon_enc_task_info(struct radeon_encoder
*enc
, bool need_feedback
)
78 enc
->enc_pic
.task_info
.task_id
++;
81 enc
->enc_pic
.task_info
.allowed_max_num_feedbacks
= 1;
83 enc
->enc_pic
.task_info
.allowed_max_num_feedbacks
= 0;
85 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO
);
86 enc
->p_task_size
= &enc
->cs
->current
.buf
[enc
->cs
->current
.cdw
++];
87 RADEON_ENC_CS(enc
->enc_pic
.task_info
.task_id
);
88 RADEON_ENC_CS(enc
->enc_pic
.task_info
.allowed_max_num_feedbacks
);
92 static void radeon_enc_session_init(struct radeon_encoder
*enc
)
94 enc
->enc_pic
.session_init
.encode_standard
= RENCODE_ENCODE_STANDARD_H264
;
95 enc
->enc_pic
.session_init
.aligned_picture_width
= align(enc
->base
.width
, 16);
96 enc
->enc_pic
.session_init
.aligned_picture_height
= align(enc
->base
.height
, 16);
97 enc
->enc_pic
.session_init
.padding_width
= enc
->enc_pic
.session_init
.aligned_picture_width
- enc
->base
.width
;
98 enc
->enc_pic
.session_init
.padding_height
= enc
->enc_pic
.session_init
.aligned_picture_height
- enc
->base
.height
;
99 enc
->enc_pic
.session_init
.pre_encode_mode
= RENCODE_PREENCODE_MODE_NONE
;
100 enc
->enc_pic
.session_init
.pre_encode_chroma_enabled
= false;
102 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT
);
103 RADEON_ENC_CS(enc
->enc_pic
.session_init
.encode_standard
);
104 RADEON_ENC_CS(enc
->enc_pic
.session_init
.aligned_picture_width
);
105 RADEON_ENC_CS(enc
->enc_pic
.session_init
.aligned_picture_height
);
106 RADEON_ENC_CS(enc
->enc_pic
.session_init
.padding_width
);
107 RADEON_ENC_CS(enc
->enc_pic
.session_init
.padding_height
);
108 RADEON_ENC_CS(enc
->enc_pic
.session_init
.pre_encode_mode
);
109 RADEON_ENC_CS(enc
->enc_pic
.session_init
.pre_encode_chroma_enabled
);
113 static void radeon_enc_layer_control(struct radeon_encoder
*enc
)
115 enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
= 1;
116 enc
->enc_pic
.layer_ctrl
.num_temporal_layers
= 1;
118 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL
);
119 RADEON_ENC_CS(enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
);
120 RADEON_ENC_CS(enc
->enc_pic
.layer_ctrl
.num_temporal_layers
);
124 static void radeon_enc_layer_select(struct radeon_encoder
*enc
)
126 enc
->enc_pic
.layer_sel
.temporal_layer_index
= 0;
128 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT
);
129 RADEON_ENC_CS(enc
->enc_pic
.layer_sel
.temporal_layer_index
);
133 static void radeon_enc_slice_control(struct radeon_encoder
*enc
)
135 enc
->enc_pic
.slice_ctrl
.slice_control_mode
= RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS
;
136 enc
->enc_pic
.slice_ctrl
.num_mbs_per_slice
= align(enc
->base
.width
, 16) / 16 * align(enc
->base
.height
, 16) / 16;
138 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL
);
139 RADEON_ENC_CS(enc
->enc_pic
.slice_ctrl
.slice_control_mode
);
140 RADEON_ENC_CS(enc
->enc_pic
.slice_ctrl
.num_mbs_per_slice
);
144 static void radeon_enc_spec_misc(struct radeon_encoder
*enc
)
146 enc
->enc_pic
.spec_misc
.constrained_intra_pred_flag
= 0;
147 enc
->enc_pic
.spec_misc
.cabac_enable
= 0;
148 enc
->enc_pic
.spec_misc
.cabac_init_idc
= 0;
149 enc
->enc_pic
.spec_misc
.half_pel_enabled
= 1;
150 enc
->enc_pic
.spec_misc
.quarter_pel_enabled
= 1;
151 enc
->enc_pic
.spec_misc
.profile_idc
= profiles
[enc
->base
.profile
- PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
];
152 enc
->enc_pic
.spec_misc
.level_idc
= enc
->base
.level
;
154 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC
);
155 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.constrained_intra_pred_flag
);
156 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.cabac_enable
);
157 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.cabac_init_idc
);
158 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.half_pel_enabled
);
159 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.quarter_pel_enabled
);
160 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.profile_idc
);
161 RADEON_ENC_CS(enc
->enc_pic
.spec_misc
.level_idc
);
165 static void radeon_enc_rc_session_init(struct radeon_encoder
*enc
, struct pipe_h264_enc_picture_desc
*pic
)
167 switch(pic
->rate_ctrl
.rate_ctrl_method
) {
168 case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE
:
169 enc
->enc_pic
.rc_session_init
.rate_control_method
= RENCODE_RATE_CONTROL_METHOD_NONE
;
171 case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP
:
172 case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT
:
173 enc
->enc_pic
.rc_session_init
.rate_control_method
= RENCODE_RATE_CONTROL_METHOD_CBR
;
175 case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP
:
176 case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE
:
177 enc
->enc_pic
.rc_session_init
.rate_control_method
= RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR
;
180 enc
->enc_pic
.rc_session_init
.rate_control_method
= RENCODE_RATE_CONTROL_METHOD_NONE
;
183 enc
->enc_pic
.rc_session_init
.vbv_buffer_level
= pic
->rate_ctrl
.vbv_buf_lv
;
185 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT
);
186 RADEON_ENC_CS(enc
->enc_pic
.rc_session_init
.rate_control_method
);
187 RADEON_ENC_CS(enc
->enc_pic
.rc_session_init
.vbv_buffer_level
);
191 static void radeon_enc_rc_layer_init(struct radeon_encoder
*enc
, struct pipe_h264_enc_picture_desc
*pic
)
193 enc
->enc_pic
.rc_layer_init
.target_bit_rate
= pic
->rate_ctrl
.target_bitrate
;
194 enc
->enc_pic
.rc_layer_init
.peak_bit_rate
= pic
->rate_ctrl
.peak_bitrate
;
195 enc
->enc_pic
.rc_layer_init
.frame_rate_num
= pic
->rate_ctrl
.frame_rate_num
;
196 enc
->enc_pic
.rc_layer_init
.frame_rate_den
= pic
->rate_ctrl
.frame_rate_den
;
197 enc
->enc_pic
.rc_layer_init
.vbv_buffer_size
= pic
->rate_ctrl
.vbv_buffer_size
;
198 enc
->enc_pic
.rc_layer_init
.avg_target_bits_per_picture
= pic
->rate_ctrl
.target_bits_picture
;
199 enc
->enc_pic
.rc_layer_init
.peak_bits_per_picture_integer
= pic
->rate_ctrl
.peak_bits_picture_integer
;
200 enc
->enc_pic
.rc_layer_init
.peak_bits_per_picture_fractional
= pic
->rate_ctrl
.peak_bits_picture_fraction
;
202 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT
);
203 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.target_bit_rate
);
204 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.peak_bit_rate
);
205 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.frame_rate_num
);
206 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.frame_rate_den
);
207 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.vbv_buffer_size
);
208 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.avg_target_bits_per_picture
);
209 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.peak_bits_per_picture_integer
);
210 RADEON_ENC_CS(enc
->enc_pic
.rc_layer_init
.peak_bits_per_picture_fractional
);
214 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder
*enc
)
216 enc
->enc_pic
.h264_deblock
.disable_deblocking_filter_idc
= 0;
217 enc
->enc_pic
.h264_deblock
.alpha_c0_offset_div2
= 0;
218 enc
->enc_pic
.h264_deblock
.beta_offset_div2
= 0;
219 enc
->enc_pic
.h264_deblock
.cb_qp_offset
= 0;
220 enc
->enc_pic
.h264_deblock
.cr_qp_offset
= 0;
222 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER
);
223 RADEON_ENC_CS(enc
->enc_pic
.h264_deblock
.disable_deblocking_filter_idc
);
224 RADEON_ENC_CS(enc
->enc_pic
.h264_deblock
.alpha_c0_offset_div2
);
225 RADEON_ENC_CS(enc
->enc_pic
.h264_deblock
.beta_offset_div2
);
226 RADEON_ENC_CS(enc
->enc_pic
.h264_deblock
.cb_qp_offset
);
227 RADEON_ENC_CS(enc
->enc_pic
.h264_deblock
.cr_qp_offset
);
231 static void radeon_enc_quality_params(struct radeon_encoder
*enc
)
233 enc
->enc_pic
.quality_params
.vbaq_mode
= 0;
234 enc
->enc_pic
.quality_params
.scene_change_sensitivity
= 0;
235 enc
->enc_pic
.quality_params
.scene_change_min_idr_interval
= 0;
237 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS
);
238 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.vbaq_mode
);
239 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.scene_change_sensitivity
);
240 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.scene_change_min_idr_interval
);
244 static void radeon_enc_ctx(struct radeon_encoder
*enc
)
246 enc
->enc_pic
.ctx_buf
.swizzle_mode
= 0;
247 enc
->enc_pic
.ctx_buf
.rec_luma_pitch
= align(enc
->base
.width
, enc
->alignment
);
248 enc
->enc_pic
.ctx_buf
.rec_chroma_pitch
= align(enc
->base
.width
, enc
->alignment
);
249 enc
->enc_pic
.ctx_buf
.num_reconstructed_pictures
= 2;
251 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER
);
252 RADEON_ENC_READWRITE(enc
->cpb
.res
->buf
, enc
->cpb
.res
->domains
, 0);
253 RADEON_ENC_CS(enc
->enc_pic
.ctx_buf
.swizzle_mode
);
254 RADEON_ENC_CS(enc
->enc_pic
.ctx_buf
.rec_luma_pitch
);
255 RADEON_ENC_CS(enc
->enc_pic
.ctx_buf
.rec_chroma_pitch
);
256 RADEON_ENC_CS(enc
->enc_pic
.ctx_buf
.num_reconstructed_pictures
);
257 /* reconstructed_picture_1_luma_offset */
258 RADEON_ENC_CS(0x00000000);
259 /* reconstructed_picture_1_chroma_offset */
260 RADEON_ENC_CS(align(enc
->base
.width
, enc
->alignment
) * align(enc
->base
.height
, 16));
261 /* reconstructed_picture_2_luma_offset */
262 RADEON_ENC_CS(align(enc
->base
.width
, enc
->alignment
) * align(enc
->base
.height
, 16) * 3 / 2);
263 /* reconstructed_picture_2_chroma_offset */
264 RADEON_ENC_CS(align(enc
->base
.width
, enc
->alignment
) * align(enc
->base
.height
, 16) * 5 / 2);
266 for (int i
= 0; i
< 136 ; i
++)
267 RADEON_ENC_CS(0x00000000);
272 static void radeon_enc_bitstream(struct radeon_encoder
*enc
)
274 enc
->enc_pic
.bit_buf
.mode
= RENCODE_REC_SWIZZLE_MODE_LINEAR
;
275 enc
->enc_pic
.bit_buf
.video_bitstream_buffer_size
= enc
->bs_size
;
276 enc
->enc_pic
.bit_buf
.video_bitstream_data_offset
= 0;
278 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER
);
279 RADEON_ENC_CS(enc
->enc_pic
.bit_buf
.mode
);
280 RADEON_ENC_WRITE(enc
->bs_handle
, RADEON_DOMAIN_GTT
, 0);
281 RADEON_ENC_CS(enc
->enc_pic
.bit_buf
.video_bitstream_buffer_size
);
282 RADEON_ENC_CS(enc
->enc_pic
.bit_buf
.video_bitstream_data_offset
);
286 static void radeon_enc_feedback(struct radeon_encoder
*enc
)
288 enc
->enc_pic
.fb_buf
.mode
= RENCODE_FEEDBACK_BUFFER_MODE_LINEAR
;
289 enc
->enc_pic
.fb_buf
.feedback_buffer_size
= 16;
290 enc
->enc_pic
.fb_buf
.feedback_data_size
= 40;
292 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER
);
293 RADEON_ENC_CS(enc
->enc_pic
.fb_buf
.mode
);
294 RADEON_ENC_WRITE(enc
->fb
->res
->buf
, enc
->fb
->res
->domains
, 0x0);
295 RADEON_ENC_CS(enc
->enc_pic
.fb_buf
.feedback_buffer_size
);
296 RADEON_ENC_CS(enc
->enc_pic
.fb_buf
.feedback_data_size
);
300 static void radeon_enc_intra_refresh(struct radeon_encoder
*enc
)
302 enc
->enc_pic
.intra_ref
.intra_refresh_mode
= RENCODE_INTRA_REFRESH_MODE_NONE
;
303 enc
->enc_pic
.intra_ref
.offset
= 0;
304 enc
->enc_pic
.intra_ref
.region_size
= 0;
306 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH
);
307 RADEON_ENC_CS(enc
->enc_pic
.intra_ref
.intra_refresh_mode
);
308 RADEON_ENC_CS(enc
->enc_pic
.intra_ref
.offset
);
309 RADEON_ENC_CS(enc
->enc_pic
.intra_ref
.region_size
);
313 static void radeon_enc_rc_per_pic(struct radeon_encoder
*enc
, struct pipe_h264_enc_picture_desc
*pic
)
315 enc
->enc_pic
.rc_per_pic
.qp
= pic
->quant_i_frames
;
316 enc
->enc_pic
.rc_per_pic
.min_qp_app
= 0;
317 enc
->enc_pic
.rc_per_pic
.max_qp_app
= 51;
318 enc
->enc_pic
.rc_per_pic
.max_au_size
= 0;
319 enc
->enc_pic
.rc_per_pic
.enabled_filler_data
= pic
->rate_ctrl
.fill_data_enable
;
320 enc
->enc_pic
.rc_per_pic
.skip_frame_enable
= false;
321 enc
->enc_pic
.rc_per_pic
.enforce_hrd
= pic
->rate_ctrl
.enforce_hrd
;
323 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE
);
324 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.qp
);
325 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.min_qp_app
);
326 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.max_qp_app
);
327 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.max_au_size
);
328 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.enabled_filler_data
);
329 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.skip_frame_enable
);
330 RADEON_ENC_CS(enc
->enc_pic
.rc_per_pic
.enforce_hrd
);
334 static void radeon_enc_encode_params(struct radeon_encoder
*enc
)
336 switch(enc
->enc_pic
.picture_type
) {
337 case PIPE_H264_ENC_PICTURE_TYPE_I
:
338 case PIPE_H264_ENC_PICTURE_TYPE_IDR
:
339 enc
->enc_pic
.enc_params
.pic_type
= RENCODE_PICTURE_TYPE_I
;
341 case PIPE_H264_ENC_PICTURE_TYPE_P
:
342 enc
->enc_pic
.enc_params
.pic_type
= RENCODE_PICTURE_TYPE_P
;
344 case PIPE_H264_ENC_PICTURE_TYPE_SKIP
:
345 enc
->enc_pic
.enc_params
.pic_type
= RENCODE_PICTURE_TYPE_P_SKIP
;
347 case PIPE_H264_ENC_PICTURE_TYPE_B
:
348 enc
->enc_pic
.enc_params
.pic_type
= RENCODE_PICTURE_TYPE_B
;
351 enc
->enc_pic
.enc_params
.pic_type
= RENCODE_PICTURE_TYPE_I
;
354 enc
->enc_pic
.enc_params
.allowed_max_bitstream_size
= enc
->bs_size
;
355 enc
->enc_pic
.enc_params
.input_pic_luma_pitch
= enc
->luma
->u
.gfx9
.surf_pitch
;
356 enc
->enc_pic
.enc_params
.input_pic_chroma_pitch
= enc
->chroma
->u
.gfx9
.surf_pitch
;
357 enc
->enc_pic
.enc_params
.input_pic_swizzle_mode
= RENCODE_INPUT_SWIZZLE_MODE_LINEAR
;
359 if(enc
->enc_pic
.picture_type
== PIPE_H264_ENC_PICTURE_TYPE_IDR
)
360 enc
->enc_pic
.enc_params
.reference_picture_index
= 0xFFFFFFFF;
362 enc
->enc_pic
.enc_params
.reference_picture_index
= (enc
->enc_pic
.frame_num
- 1) % 2;
364 enc
->enc_pic
.enc_params
.reconstructed_picture_index
= enc
->enc_pic
.frame_num
% 2;
366 RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS
);
367 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.pic_type
);
368 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.allowed_max_bitstream_size
);
369 RADEON_ENC_READ(enc
->handle
, RADEON_DOMAIN_VRAM
, enc
->luma
->u
.gfx9
.surf_offset
);
370 RADEON_ENC_READ(enc
->handle
, RADEON_DOMAIN_VRAM
, enc
->chroma
->u
.gfx9
.surf_offset
);
371 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.input_pic_luma_pitch
);
372 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.input_pic_chroma_pitch
);
373 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.input_pic_swizzle_mode
);
374 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.reference_picture_index
);
375 RADEON_ENC_CS(enc
->enc_pic
.enc_params
.reconstructed_picture_index
);
378 static void radeon_enc_encode_params_h264(struct radeon_encoder
*enc
)
380 enc
->enc_pic
.h264_enc_params
.input_picture_structure
= RENCODE_H264_PICTURE_STRUCTURE_FRAME
;
381 enc
->enc_pic
.h264_enc_params
.interlaced_mode
= RENCODE_H264_INTERLACING_MODE_PROGRESSIVE
;
382 enc
->enc_pic
.h264_enc_params
.reference_picture_structure
= RENCODE_H264_PICTURE_STRUCTURE_FRAME
;
383 enc
->enc_pic
.h264_enc_params
.reference_picture1_index
= 0xFFFFFFFF;
385 RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS
);
386 RADEON_ENC_CS(enc
->enc_pic
.h264_enc_params
.input_picture_structure
);
387 RADEON_ENC_CS(enc
->enc_pic
.h264_enc_params
.interlaced_mode
);
388 RADEON_ENC_CS(enc
->enc_pic
.h264_enc_params
.reference_picture_structure
);
389 RADEON_ENC_CS(enc
->enc_pic
.h264_enc_params
.reference_picture1_index
);
393 static void radeon_enc_op_init(struct radeon_encoder
*enc
)
395 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE
);
399 static void radeon_enc_op_close(struct radeon_encoder
*enc
)
401 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION
);
405 static void radeon_enc_op_enc(struct radeon_encoder
*enc
)
407 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE
);
411 static void radeon_enc_op_init_rc(struct radeon_encoder
*enc
)
413 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC
);
417 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder
*enc
)
419 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL
);
423 static void radeon_enc_op_speed(struct radeon_encoder
*enc
)
425 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE
);
429 static void begin(struct radeon_encoder
*enc
, struct pipe_h264_enc_picture_desc
*pic
)
431 radeon_enc_session_info(enc
);
432 enc
->total_task_size
= 0;
433 radeon_enc_task_info(enc
, enc
->need_feedback
);
434 radeon_enc_op_init(enc
);
435 radeon_enc_session_init(enc
);
436 radeon_enc_layer_control(enc
);
437 radeon_enc_slice_control(enc
);
438 radeon_enc_spec_misc(enc
);
439 radeon_enc_rc_session_init(enc
, pic
);
440 radeon_enc_deblocking_filter_h264(enc
);
441 radeon_enc_quality_params(enc
);
442 radeon_enc_layer_select(enc
);
443 radeon_enc_rc_layer_init(enc
, pic
);
444 radeon_enc_layer_select(enc
);
445 radeon_enc_rc_per_pic(enc
, pic
);
446 radeon_enc_op_init_rc(enc
);
447 radeon_enc_op_init_rc_vbv(enc
);
448 *enc
->p_task_size
= (enc
->total_task_size
);
451 static void encode(struct radeon_encoder
*enc
)
453 radeon_enc_session_info(enc
);
454 enc
->total_task_size
= 0;
455 radeon_enc_task_info(enc
, enc
->need_feedback
);
457 radeon_enc_bitstream(enc
);
458 radeon_enc_feedback(enc
);
459 radeon_enc_intra_refresh(enc
);
460 radeon_enc_encode_params(enc
);
461 radeon_enc_encode_params_h264(enc
);
462 radeon_enc_op_speed(enc
);
463 radeon_enc_op_enc(enc
);
464 *enc
->p_task_size
= (enc
->total_task_size
);
467 static void destroy(struct radeon_encoder
*enc
)
469 radeon_enc_session_info(enc
);
470 enc
->total_task_size
= 0;
471 radeon_enc_task_info(enc
, enc
->need_feedback
);
472 radeon_enc_op_close(enc
);
473 *enc
->p_task_size
= (enc
->total_task_size
);
476 void radeon_enc_1_2_init(struct radeon_encoder
*enc
)
479 enc
->encode
= encode
;
480 enc
->destroy
= destroy
;