src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33
  34 #include "si_pipe.h"
  35 #include "radeon_video.h"
  36 #include "radeon_vcn_enc.h"
  37
  38 static void radeon_enc_session_info(struct radeon_encoder *enc)
  39 {
  40         unsigned int interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
  41                                                                           (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
  42         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INFO);
  43         RADEON_ENC_CS(interface_version);
  44         RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
  45         RADEON_ENC_END();
  46 }
  47
  48 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
  49 {
  50         enc->enc_pic.task_info.task_id++;
  51
  52         if (need_feedback)
  53                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
  54         else
  55                 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
  56
  57         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_TASK_INFO);
  58         enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++];
  59         RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
  60         RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
  61         RADEON_ENC_END();
  62 }
  63
  64 static void radeon_enc_session_init(struct radeon_encoder *enc)
  65 {
  66         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
  67         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
  68         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
  69         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
  70         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
  71         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
  72         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
  73
  74         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
  75         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
  76         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
  77         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
  78         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
  79         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
  80         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
  81         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
  82         RADEON_ENC_END();
  83 }
  84
  85 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
  86 {
  87         enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
  88         enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
  89         enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
  90         enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
  91         enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
  92         enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
  93         enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
  94
  95         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
  96         RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
  97         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
  98         RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
  99         RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
 100         RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
 101         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
 102         RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
 103         RADEON_ENC_END();
 104 }
 105
 106 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 107 {
 108         enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
 109         enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
 110
 111         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_CONTROL);
 112         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
 113         RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
 114         RADEON_ENC_END();
 115 }
 116
 117 static void radeon_enc_layer_select(struct radeon_encoder *enc)
 118 {
 119         enc->enc_pic.layer_sel.temporal_layer_index = 0;
 120
 121         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_LAYER_SELECT);
 122         RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
 123         RADEON_ENC_END();
 124 }
 125
 126 static void radeon_enc_slice_control(struct radeon_encoder *enc)
 127 {
 128         enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 129         enc->enc_pic.slice_ctrl.num_mbs_per_slice = align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
 130
 131         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SLICE_CONTROL);
 132         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
 133         RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
 134         RADEON_ENC_END();
 135 }
 136
 137 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
 138 {
 139         enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
 140         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
 141         enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
 142
 143         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
 144         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
 145         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
 146         RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
 147         RADEON_ENC_END();
 148 }
 149
 150 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 151 {
 152         enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
 153         enc->enc_pic.spec_misc.cabac_enable = 0;
 154         enc->enc_pic.spec_misc.cabac_init_idc = 0;
 155         enc->enc_pic.spec_misc.half_pel_enabled = 1;
 156         enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
 157         enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
 158         enc->enc_pic.spec_misc.level_idc = enc->base.level;
 159
 160         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_SPEC_MISC);
 161         RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
 162         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
 163         RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
 164         RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
 165         RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
 166         RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
 167         RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
 168         RADEON_ENC_END();
 169 }
 170
 171 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 172 {
 173         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 174         enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = pic->seq.log2_min_luma_coding_block_size_minus3;
 175         enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
 176         enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = pic->seq.strong_intra_smoothing_enabled_flag;
 177         enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
 178         enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
 179         enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
 180         enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
 181
 182         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
 183         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 184         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
 185         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
 186         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
 187         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
 188         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
 189         RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
 190         RADEON_ENC_END();
 191 }
 192
 193 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 194 {
 195         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 196                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 197                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl.vbv_buf_lv;
 198                 switch(pic->rate_ctrl.rate_ctrl_method) {
 199                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_DISABLE:
 200                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 201                                 break;
 202                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 203                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT:
 204                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 205                                 break;
 206                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 207                         case PIPE_H264_ENC_RATE_CONTROL_METHOD_VARIABLE:
 208                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 209                                 break;
 210                         default:
 211                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 212                 }
 213         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 214                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 215                 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
 216                 switch(pic->rc.rate_ctrl_method) {
 217                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_DISABLE:
 218                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 219                                 break;
 220                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
 221                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_CONSTANT:
 222                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
 223                                 break;
 224                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
 225                         case PIPE_H265_ENC_RATE_CONTROL_METHOD_VARIABLE:
 226                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
 227                                 break;
 228                         default:
 229                                 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
 230                 }
 231         }
 232
 233         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT);
 234         RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
 235         RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
 236         RADEON_ENC_END();
 237 }
 238
 239 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 240 {
 241         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 242                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 243                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rate_ctrl.target_bitrate;
 244                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rate_ctrl.peak_bitrate;
 245                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rate_ctrl.frame_rate_num;
 246                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rate_ctrl.frame_rate_den;
 247                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
 248                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rate_ctrl.target_bits_picture;
 249                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rate_ctrl.peak_bits_picture_integer;
 250                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rate_ctrl.peak_bits_picture_fraction;
 251         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 252                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 253                 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
 254                 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
 255                 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
 256                 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
 257                 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
 258                 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
 259                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
 260                 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
 261         }
 262
 263         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT);
 264         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
 265         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
 266         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
 267         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
 268         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
 269         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
 270         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
 271         RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
 272         RADEON_ENC_END();
 273 }
 274
 275 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
 276 {
 277         enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
 278         enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
 279         enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
 280         enc->enc_pic.h264_deblock.cb_qp_offset = 0;
 281         enc->enc_pic.h264_deblock.cr_qp_offset = 0;
 282
 283         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER);
 284         RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
 285         RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 286         RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
 287         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
 288         RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
 289         RADEON_ENC_END();
 290 }
 291
 292 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 293 {
 294         struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 295         enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
 296         enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
 297         enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
 298         enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
 299         enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
 300         enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
 301
 302         RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER);
 303         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
 304         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
 305         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 306         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 307         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 308         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 309         RADEON_ENC_END();
 310 }
 311
 312 static void radeon_enc_quality_params(struct radeon_encoder *enc)
 313 {
 314         enc->enc_pic.quality_params.vbaq_mode = 0;
 315         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
 316         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
 317
 318         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_QUALITY_PARAMS);
 319         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
 320         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
 321         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
 322         RADEON_ENC_END();
 323 }
 324
 325 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
 326 {
 327         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 328         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 329         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 330         radeon_enc_reset(enc);
 331         radeon_enc_set_emulation_prevention(enc, false);
 332         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 333         radeon_enc_code_fixed_bits(enc, 0x67, 8);
 334         radeon_enc_byte_align(enc);
 335         radeon_enc_set_emulation_prevention(enc, true);
 336         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
 337         radeon_enc_code_fixed_bits(enc, 0x44, 8); //hardcode to constrained baseline
 338         radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
 339         radeon_enc_code_ue(enc, 0x0);
 340
 341         if(enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || enc->enc_pic.spec_misc.profile_idc == 122 ||
 342                         enc->enc_pic.spec_misc.profile_idc == 244 || enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
 343                         enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || enc->enc_pic.spec_misc.profile_idc == 128 ||
 344                         enc->enc_pic.spec_misc.profile_idc == 138) {
 345                 radeon_enc_code_ue(enc, 0x1);
 346                 radeon_enc_code_ue(enc, 0x0);
 347                 radeon_enc_code_ue(enc, 0x0);
 348                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 349         }
 350
 351         radeon_enc_code_ue(enc, 1);
 352         radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
 353
 354         if (enc->enc_pic.pic_order_cnt_type == 0)
 355                 radeon_enc_code_ue(enc, 1);
 356
 357         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 358         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, 1);
 359         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
 360         radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
 361         bool progressive_only = true;
 362         radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
 363
 364         if (!progressive_only)
 365                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 366
 367         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 368
 369         if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
 370                         (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
 371                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 372                 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
 373                 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
 374                 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
 375                 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
 376         } else
 377                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 378
 379         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 380         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 381         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 382         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 383         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 384         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 385         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 386         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 387         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 388         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 389         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 390         radeon_enc_code_ue(enc, 0x0);
 391         radeon_enc_code_ue(enc, 0x0);
 392         radeon_enc_code_ue(enc, 16);
 393         radeon_enc_code_ue(enc, 16);
 394         radeon_enc_code_ue(enc, 0x0);
 395         radeon_enc_code_ue(enc, (enc->base.max_references + 1));
 396
 397         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 398
 399         radeon_enc_byte_align(enc);
 400         radeon_enc_flush_headers(enc);
 401         *size_in_bytes = (enc->bits_output + 7) / 8;
 402         RADEON_ENC_END();
 403 }
 404
 405 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 406 {
 407         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 408         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 409         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 410         int i;
 411
 412         radeon_enc_reset(enc);
 413         radeon_enc_set_emulation_prevention(enc, false);
 414         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 415         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 416         radeon_enc_byte_align(enc);
 417         radeon_enc_set_emulation_prevention(enc, true);
 418         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 419         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 420         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 421         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 422         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 423         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 424         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 425         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 426         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 427         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 428
 429         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 430                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 431
 432         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 433                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 434                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 435         }
 436
 437         radeon_enc_code_ue(enc, 0x0);
 438         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 439         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 440         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 441         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 442         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 443         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 444         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 445         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 446         radeon_enc_code_ue(enc, 1);
 447         radeon_enc_code_ue(enc, 0x0);
 448         radeon_enc_code_ue(enc, 0x0);
 449         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 450         //Only support CTBSize 64
 451         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 452         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 453         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 454         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 455         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 456
 457         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 458         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 459         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 460         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 461
 462         radeon_enc_code_ue(enc, 1);
 463         radeon_enc_code_ue(enc, 1);
 464         radeon_enc_code_ue(enc, 0);
 465         radeon_enc_code_ue(enc, 0);
 466         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 467
 468         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 469
 470         radeon_enc_code_fixed_bits(enc, 0, 1);
 471         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 472
 473         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 474
 475         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 476
 477         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 478
 479         radeon_enc_byte_align(enc);
 480         radeon_enc_flush_headers(enc);
 481         *size_in_bytes = (enc->bits_output + 7) / 8;
 482         RADEON_ENC_END();
 483 }
 484
 485 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
 486 {
 487         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 488         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 489         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 490         radeon_enc_reset(enc);
 491         radeon_enc_set_emulation_prevention(enc, false);
 492         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 493         radeon_enc_code_fixed_bits(enc, 0x68, 8);
 494         radeon_enc_byte_align(enc);
 495         radeon_enc_set_emulation_prevention(enc, true);
 496         radeon_enc_code_ue(enc, 0x0);
 497         radeon_enc_code_ue(enc, 0x0);
 498         radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
 499         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 500         radeon_enc_code_ue(enc, 0x0);
 501         radeon_enc_code_ue(enc, 0x0);
 502         radeon_enc_code_ue(enc, 0x0);
 503         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 504         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 505         radeon_enc_code_se(enc, 0x0);
 506         radeon_enc_code_se(enc, 0x0);
 507         radeon_enc_code_se(enc, 0x0);
 508         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 509         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 510         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 511
 512         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 513
 514         radeon_enc_byte_align(enc);
 515         radeon_enc_flush_headers(enc);
 516         *size_in_bytes = (enc->bits_output + 7) / 8;
 517         RADEON_ENC_END();
 518 }
 519
 520 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 521 {
 522         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 523         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 524         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 525         radeon_enc_reset(enc);
 526         radeon_enc_set_emulation_prevention(enc, false);
 527         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 528         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 529         radeon_enc_byte_align(enc);
 530         radeon_enc_set_emulation_prevention(enc, true);
 531         radeon_enc_code_ue(enc, 0x0);
 532         radeon_enc_code_ue(enc, 0x0);
 533         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 534         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 535         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 536         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 537         radeon_enc_code_ue(enc, 0x0);
 538         radeon_enc_code_ue(enc, 0x0);
 539         radeon_enc_code_se(enc, 0x0);
 540         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 541         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 542         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 543         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 544         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 545         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 546         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 547         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 548         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 549         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 550         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 551         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 552         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 553         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 554
 555         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 556                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 557                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 558         }
 559
 560         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 561         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 562         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 563         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 564
 565         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 566
 567         radeon_enc_byte_align(enc);
 568         radeon_enc_flush_headers(enc);
 569         *size_in_bytes = (enc->bits_output + 7) / 8;
 570         RADEON_ENC_END();
 571 }
 572
 573 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
 574 {
 575         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 576         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
 577         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 578         int i;
 579
 580         radeon_enc_reset(enc);
 581         radeon_enc_set_emulation_prevention(enc, false);
 582         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 583         radeon_enc_code_fixed_bits(enc, 0x4001, 16);
 584         radeon_enc_byte_align(enc);
 585         radeon_enc_set_emulation_prevention(enc, true);
 586
 587         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 588         radeon_enc_code_fixed_bits(enc, 0x3, 2);
 589         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 590         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 591         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 592         radeon_enc_code_fixed_bits(enc, 0xffff, 16);
 593         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 594         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 595         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 596         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 597         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 598         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 599         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 600
 601         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 602                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 603
 604         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 605                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 606                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 607         }
 608
 609         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 610         radeon_enc_code_ue(enc, 0x1);
 611         radeon_enc_code_ue(enc, 0x0);
 612         radeon_enc_code_ue(enc, 0x0);
 613
 614         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 615         radeon_enc_code_ue(enc, 0x0);
 616         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 617         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 618
 619         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 620
 621         radeon_enc_byte_align(enc);
 622         radeon_enc_flush_headers(enc);
 623         *size_in_bytes = (enc->bits_output + 7) / 8;
 624         RADEON_ENC_END();
 625 }
 626
 627 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
 628 {
 629         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
 630         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
 631         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 632         radeon_enc_reset(enc);
 633         radeon_enc_set_emulation_prevention(enc, false);
 634         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 635         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 636         radeon_enc_code_fixed_bits(enc, 35, 6);
 637         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 638         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 639         radeon_enc_byte_align(enc);
 640         radeon_enc_set_emulation_prevention(enc, true);
 641         switch(enc->enc_pic.picture_type) {
 642                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 643                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 644                         radeon_enc_code_fixed_bits(enc, 0x00, 3);
 645                         break;
 646                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 647                         radeon_enc_code_fixed_bits(enc, 0x01, 3);
 648                         break;
 649                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 650                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 651                         break;
 652                 default:
 653                         radeon_enc_code_fixed_bits(enc, 0x02, 3);
 654         }
 655
 656     radeon_enc_code_fixed_bits(enc, 0x1, 1);
 657
 658         radeon_enc_byte_align(enc);
 659         radeon_enc_flush_headers(enc);
 660         *size_in_bytes = (enc->bits_output + 7) / 8;
 661         RADEON_ENC_END();
 662 }
 663
 664 static void radeon_enc_slice_header(struct radeon_encoder *enc)
 665 {
 666         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 667         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 668         unsigned int inst_index = 0;
 669         unsigned int bit_index = 0;
 670         unsigned int bits_copied = 0;
 671         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 672         radeon_enc_reset(enc);
 673         radeon_enc_set_emulation_prevention(enc, false);
 674
 675         if (enc->enc_pic.is_idr)
 676                 radeon_enc_code_fixed_bits(enc, 0x65, 8);
 677         else if (enc->enc_pic.not_referenced)
 678                 radeon_enc_code_fixed_bits(enc, 0x01, 8);
 679         else
 680                 radeon_enc_code_fixed_bits(enc, 0x41, 8);
 681
 682         radeon_enc_flush_headers(enc);
 683         bit_index ++;
 684         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 685         num_bits[inst_index] = enc->bits_output - bits_copied;
 686         bits_copied = enc->bits_output;
 687         inst_index++;
 688
 689         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
 690         inst_index++;
 691
 692         switch(enc->enc_pic.picture_type) {
 693                 case PIPE_H264_ENC_PICTURE_TYPE_I:
 694                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
 695                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 696                         break;
 697                 case PIPE_H264_ENC_PICTURE_TYPE_P:
 698                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
 699                         radeon_enc_code_fixed_bits(enc, 0x06, 5);
 700                         break;
 701                 case PIPE_H264_ENC_PICTURE_TYPE_B:
 702                         radeon_enc_code_fixed_bits(enc, 0x07, 5);
 703                         break;
 704                 default:
 705                         radeon_enc_code_fixed_bits(enc, 0x08, 7);
 706         }
 707
 708         radeon_enc_code_ue(enc, 0x0);
 709         radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
 710
 711         if (enc->enc_pic.h264_enc_params.input_picture_structure != RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
 712                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 713                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.h264_enc_params.input_picture_structure == RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD ? 1 : 0, 1);
 714         }
 715
 716         if (enc->enc_pic.is_idr)
 717                 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
 718
 719         enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
 720
 721         if (enc->enc_pic.pic_order_cnt_type == 0)
 722                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
 723
 724         if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) {
 725                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 726
 727                 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
 728                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 729                         radeon_enc_code_ue(enc, 0x0);
 730                         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
 731                         radeon_enc_code_ue(enc, 0x3);
 732                 } else
 733                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 734         }
 735
 736         if (enc->enc_pic.is_idr) {
 737                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 738                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 739         } else
 740                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 741
 742         if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && (enc->enc_pic.spec_misc.cabac_enable))
 743                 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
 744
 745         radeon_enc_flush_headers(enc);
 746         bit_index ++;
 747         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 748         num_bits[inst_index] = enc->bits_output - bits_copied;
 749         bits_copied = enc->bits_output;
 750         inst_index++;
 751
 752         instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 753         inst_index++;
 754
 755         radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1: 0);
 756
 757         if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
 758                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
 759                 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
 760         }
 761
 762         radeon_enc_flush_headers(enc);
 763         bit_index ++;
 764         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 765         num_bits[inst_index] = enc->bits_output - bits_copied;
 766         bits_copied = enc->bits_output;
 767         inst_index++;
 768
 769         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 770
 771         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 772                 RADEON_ENC_CS(0x00000000);
 773
 774         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 775                 RADEON_ENC_CS(instruction[j]);
 776                 RADEON_ENC_CS(num_bits[j]);
 777         }
 778
 779         RADEON_ENC_END();
 780 }
 781
 782 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
 783 {
 784         uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 785         uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
 786         unsigned int inst_index = 0;
 787         unsigned int bit_index = 0;
 788         unsigned int bits_copied = 0;
 789         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SLICE_HEADER);
 790         radeon_enc_reset(enc);
 791         radeon_enc_set_emulation_prevention(enc, false);
 792
 793         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 794         radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
 795         radeon_enc_code_fixed_bits(enc, 0x0, 6);
 796         radeon_enc_code_fixed_bits(enc, 0x1, 3);
 797
 798         radeon_enc_flush_headers(enc);
 799         bit_index ++;
 800         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 801         num_bits[inst_index] = enc->bits_output - bits_copied;
 802         bits_copied = enc->bits_output;
 803         inst_index++;
 804
 805         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
 806         inst_index++;
 807
 808         if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
 809                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 810
 811         radeon_enc_code_ue(enc, 0x0);
 812
 813         radeon_enc_flush_headers(enc);
 814         bit_index ++;
 815         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 816         num_bits[inst_index] = enc->bits_output - bits_copied;
 817         bits_copied = enc->bits_output;
 818         inst_index++;
 819
 820         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
 821         inst_index++;
 822
 823         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
 824         inst_index++;
 825
 826         switch(enc->enc_pic.picture_type) {
 827                 case PIPE_H265_ENC_PICTURE_TYPE_I:
 828                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
 829                         radeon_enc_code_ue(enc, 0x2);
 830                         break;
 831                 case PIPE_H265_ENC_PICTURE_TYPE_P:
 832                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
 833                         radeon_enc_code_ue(enc, 0x1);
 834                         break;
 835                 case PIPE_H265_ENC_PICTURE_TYPE_B:
 836                         radeon_enc_code_ue(enc, 0x0);
 837                         break;
 838                 default:
 839                         radeon_enc_code_ue(enc, 0x1);
 840         }
 841
 842         if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
 843                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % enc->enc_pic.max_poc, enc->enc_pic.log2_max_poc);
 844                 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P)
 845                         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 846                 else {
 847                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 848                         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 849                         radeon_enc_code_ue(enc, 0x0);
 850                         radeon_enc_code_ue(enc, 0x0);
 851                 }
 852         }
 853
 854         if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) ||
 855                 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) {
 856                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 857                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
 858                 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
 859         }
 860
 861         radeon_enc_flush_headers(enc);
 862         bit_index ++;
 863         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 864         num_bits[inst_index] = enc->bits_output - bits_copied;
 865         bits_copied = enc->bits_output;
 866         inst_index++;
 867
 868         instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
 869         inst_index++;
 870
 871         if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
 872                 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)){
 873                 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 874
 875                 radeon_enc_flush_headers(enc);
 876                 bit_index ++;
 877                 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
 878                 num_bits[inst_index] = enc->bits_output - bits_copied;
 879                 bits_copied = enc->bits_output;
 880                 inst_index++;
 881         }
 882
 883         instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
 884
 885         for (int i = bit_index; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
 886                 RADEON_ENC_CS(0x00000000);
 887
 888         for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
 889                 RADEON_ENC_CS(instruction[j]);
 890                 RADEON_ENC_CS(num_bits[j]);
 891         }
 892
 893         RADEON_ENC_END();
 894 }
 895
 896 static void radeon_enc_ctx(struct radeon_encoder *enc)
 897 {
 898         enc->enc_pic.ctx_buf.swizzle_mode = 0;
 899         enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
 900         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
 901         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 902
 903         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER);
 904         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 905         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 906         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 907         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 908         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 909         /* reconstructed_picture_1_luma_offset */
 910         RADEON_ENC_CS(0x00000000);
 911         /* reconstructed_picture_1_chroma_offset */
 912         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
 913         /* reconstructed_picture_2_luma_offset */
 914         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
 915         /* reconstructed_picture_2_chroma_offset */
 916         RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
 917
 918         for (int i = 0; i < 136 ; i++)
 919                 RADEON_ENC_CS(0x00000000);
 920
 921         RADEON_ENC_END();
 922 }
 923
 924 static void radeon_enc_bitstream(struct radeon_encoder *enc)
 925 {
 926         enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
 927         enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
 928         enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
 929
 930         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
 931         RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
 932         RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
 933         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
 934         RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
 935         RADEON_ENC_END();
 936 }
 937
 938 static void radeon_enc_feedback(struct radeon_encoder *enc)
 939 {
 940         enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
 941         enc->enc_pic.fb_buf.feedback_buffer_size = 16;
 942         enc->enc_pic.fb_buf.feedback_data_size = 40;
 943
 944         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_FEEDBACK_BUFFER);
 945         RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
 946         RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
 947         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
 948         RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
 949         RADEON_ENC_END();
 950 }
 951
 952 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
 953 {
 954         enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
 955         enc->enc_pic.intra_ref.offset = 0;
 956         enc->enc_pic.intra_ref.region_size = 0;
 957
 958         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_INTRA_REFRESH);
 959         RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
 960         RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
 961         RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
 962         RADEON_ENC_END();
 963 }
 964
 965 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
 966 {
 967         if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 968                 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
 969                 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
 970                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
 971                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
 972                 enc->enc_pic.rc_per_pic.max_au_size = 0;
 973                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl.fill_data_enable;
 974                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
 975                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl.enforce_hrd;
 976         } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
 977                 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
 978                 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
 979                 enc->enc_pic.rc_per_pic.min_qp_app = 0;
 980                 enc->enc_pic.rc_per_pic.max_qp_app = 51;
 981                 enc->enc_pic.rc_per_pic.max_au_size = 0;
 982                 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
 983                 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
 984                 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
 985         }
 986
 987         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE);
 988         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
 989         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
 990         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
 991         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
 992         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
 993         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
 994         RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
 995         RADEON_ENC_END();
 996 }
 997
 998 static void radeon_enc_encode_params(struct radeon_encoder *enc)
 999 {
1000         switch(enc->enc_pic.picture_type) {
1001                 case PIPE_H264_ENC_PICTURE_TYPE_I:
1002                 case PIPE_H264_ENC_PICTURE_TYPE_IDR:
1003                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1004                         break;
1005                 case PIPE_H264_ENC_PICTURE_TYPE_P:
1006                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1007                         break;
1008                 case PIPE_H264_ENC_PICTURE_TYPE_SKIP:
1009                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1010                         break;
1011                 case PIPE_H264_ENC_PICTURE_TYPE_B:
1012                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1013                         break;
1014                 default:
1015                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1016         }
1017
1018         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1019         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1020         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1021         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1022
1023         if(enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
1024                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1025         else
1026                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1027
1028         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1029
1030         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1031         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1032         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1033         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1034         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1035         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1036         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1037         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1038         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1039         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1040         RADEON_ENC_END();
1041 }
1042
1043 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1044 {
1045         switch(enc->enc_pic.picture_type) {
1046                 case PIPE_H265_ENC_PICTURE_TYPE_I:
1047                 case PIPE_H265_ENC_PICTURE_TYPE_IDR:
1048                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1049                         break;
1050                 case PIPE_H265_ENC_PICTURE_TYPE_P:
1051                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1052                         break;
1053                 case PIPE_H265_ENC_PICTURE_TYPE_SKIP:
1054                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1055                         break;
1056                 case PIPE_H265_ENC_PICTURE_TYPE_B:
1057                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1058                         break;
1059                 default:
1060                         enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1061         }
1062
1063         enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1064         enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1065         enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1066         enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR;
1067
1068         if(enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1069                 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1070         else
1071                 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1072
1073         enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1074
1075         RADEON_ENC_BEGIN(RENCODE_IB_PARAM_ENCODE_PARAMS);
1076         RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1077         RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1078         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1079         RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1080         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1081         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1082         RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1083         RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1084         RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1085         RADEON_ENC_END();
1086 }
1087
1088 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1089 {
1090         enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1091         enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1092         enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1093         enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1094
1095         RADEON_ENC_BEGIN(RENCODE_H264_IB_PARAM_ENCODE_PARAMS);
1096         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1097         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1098         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1099         RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1100         RADEON_ENC_END();
1101 }
1102
1103 static void radeon_enc_op_init(struct radeon_encoder *enc)
1104 {
1105         RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1106         RADEON_ENC_END();
1107 }
1108
1109 static void radeon_enc_op_close(struct radeon_encoder *enc)
1110 {
1111         RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1112         RADEON_ENC_END();
1113 }
1114
1115 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1116 {
1117         RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1118         RADEON_ENC_END();
1119 }
1120
1121 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1122 {
1123         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1124         RADEON_ENC_END();
1125 }
1126
1127 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1128 {
1129         RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1130         RADEON_ENC_END();
1131 }
1132
1133 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1134 {
1135         RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1136         RADEON_ENC_END();
1137 }
1138
1139 static void begin(struct radeon_encoder *enc, struct pipe_picture_desc *pic)
1140 {
1141         radeon_enc_session_info(enc);
1142         enc->total_task_size = 0;
1143         radeon_enc_task_info(enc, enc->need_feedback);
1144         radeon_enc_op_init(enc);
1145
1146         if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1147                 radeon_enc_session_init(enc);
1148                 radeon_enc_slice_control(enc);
1149                 radeon_enc_spec_misc(enc);
1150                 radeon_enc_deblocking_filter_h264(enc);
1151         } else if (u_reduce_video_profile(pic->profile) == PIPE_VIDEO_FORMAT_HEVC) {
1152                 radeon_enc_session_init_hevc(enc);
1153                 radeon_enc_slice_control_hevc(enc);
1154                 radeon_enc_spec_misc_hevc(enc, pic);
1155                 radeon_enc_deblocking_filter_hevc(enc, pic);
1156         }
1157
1158         radeon_enc_layer_control(enc);
1159         radeon_enc_rc_session_init(enc, pic);
1160         radeon_enc_quality_params(enc);
1161         radeon_enc_layer_select(enc);
1162         radeon_enc_rc_layer_init(enc, pic);
1163         radeon_enc_layer_select(enc);
1164         radeon_enc_rc_per_pic(enc, pic);
1165         radeon_enc_op_init_rc(enc);
1166         radeon_enc_op_init_rc_vbv(enc);
1167         *enc->p_task_size = (enc->total_task_size);
1168 }
1169
1170 static void encode(struct radeon_encoder *enc)
1171 {
1172         radeon_enc_session_info(enc);
1173         enc->total_task_size = 0;
1174         radeon_enc_task_info(enc, enc->need_feedback);
1175
1176         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1177                 if (enc->enc_pic.is_idr) {
1178                         radeon_enc_nalu_sps(enc);
1179                         radeon_enc_nalu_pps(enc);
1180                 }
1181                 radeon_enc_slice_header(enc);
1182                 radeon_enc_encode_params(enc);
1183                 radeon_enc_encode_params_h264(enc);
1184         } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1185                 radeon_enc_nalu_aud_hevc(enc);
1186                 if (enc->enc_pic.is_idr) {
1187                         radeon_enc_nalu_vps(enc);
1188                         radeon_enc_nalu_pps_hevc(enc);
1189                         radeon_enc_nalu_sps_hevc(enc);
1190                 }
1191                 radeon_enc_slice_header_hevc(enc);
1192                 radeon_enc_encode_params_hevc(enc);
1193         }
1194
1195         radeon_enc_ctx(enc);
1196         radeon_enc_bitstream(enc);
1197         radeon_enc_feedback(enc);
1198         radeon_enc_intra_refresh(enc);
1199
1200         radeon_enc_op_speed(enc);
1201         radeon_enc_op_enc(enc);
1202         *enc->p_task_size = (enc->total_task_size);
1203 }
1204
1205 static void destroy(struct radeon_encoder *enc)
1206 {
1207         radeon_enc_session_info(enc);
1208         enc->total_task_size = 0;
1209         radeon_enc_task_info(enc, enc->need_feedback);
1210         radeon_enc_op_close(enc);
1211         *enc->p_task_size = (enc->total_task_size);
1212 }
1213
1214 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1215 {
1216         enc->begin = begin;
1217         enc->encode = encode;
1218         enc->destroy = destroy;
1219 }