1 /**************************************************************************
3 * Copyright 2017 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "pipe/p_video_codec.h"
32 #include "util/u_video.h"
35 #include "radeon_video.h"
36 #include "radeon_vcn_enc.h"
38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
39 #define RENCODE_FW_INTERFACE_MINOR_VERSION 1
41 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
42 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
43 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
44 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
45 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
46 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
47 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
48 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
49 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
50 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
51 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000b
52 #define RENCODE_IB_PARAM_INPUT_FORMAT 0x0000000c
53 #define RENCODE_IB_PARAM_OUTPUT_FORMAT 0x0000000d
54 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000f
55 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
56 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
57 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
58 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
60 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
61 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
62 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
64 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
65 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
66 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
67 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
69 static void radeon_enc_quality_params(struct radeon_encoder
*enc
)
71 enc
->enc_pic
.quality_params
.vbaq_mode
= 0;
72 enc
->enc_pic
.quality_params
.scene_change_sensitivity
= 0;
73 enc
->enc_pic
.quality_params
.scene_change_min_idr_interval
= 0;
74 enc
->enc_pic
.quality_params
.two_pass_search_center_map_mode
= 0;
76 RADEON_ENC_BEGIN(enc
->cmd
.quality_params
);
77 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.vbaq_mode
);
78 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.scene_change_sensitivity
);
79 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.scene_change_min_idr_interval
);
80 RADEON_ENC_CS(enc
->enc_pic
.quality_params
.two_pass_search_center_map_mode
);
84 static void radeon_enc_loop_filter_hevc(struct radeon_encoder
*enc
)
86 RADEON_ENC_BEGIN(enc
->cmd
.deblocking_filter_hevc
);
87 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.loop_filter_across_slices_enabled
);
88 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.deblocking_filter_disabled
);
89 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.beta_offset_div2
);
90 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.tc_offset_div2
);
91 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.cb_qp_offset
);
92 RADEON_ENC_CS(enc
->enc_pic
.hevc_deblock
.cr_qp_offset
);
97 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder
*enc
)
99 RADEON_ENC_BEGIN(enc
->cmd
.nalu
);
100 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS
);
101 uint32_t *size_in_bytes
= &enc
->cs
->current
.buf
[enc
->cs
->current
.cdw
++];
104 radeon_enc_reset(enc
);
105 radeon_enc_set_emulation_prevention(enc
, false);
106 radeon_enc_code_fixed_bits(enc
, 0x00000001, 32);
107 radeon_enc_code_fixed_bits(enc
, 0x4201, 16);
108 radeon_enc_byte_align(enc
);
109 radeon_enc_set_emulation_prevention(enc
, true);
110 radeon_enc_code_fixed_bits(enc
, 0x0, 4);
111 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
- 1, 3);
112 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
113 radeon_enc_code_fixed_bits(enc
, 0x0, 2);
114 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.general_tier_flag
, 1);
115 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.general_profile_idc
, 5);
116 radeon_enc_code_fixed_bits(enc
, 0x60000000, 32);
117 radeon_enc_code_fixed_bits(enc
, 0xb0000000, 32);
118 radeon_enc_code_fixed_bits(enc
, 0x0, 16);
119 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.general_level_idc
, 8);
121 for (i
= 0; i
< (enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
- 1) ; i
++)
122 radeon_enc_code_fixed_bits(enc
, 0x0, 2);
124 if ((enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
- 1) > 0) {
125 for (i
= (enc
->enc_pic
.layer_ctrl
.max_num_temporal_layers
- 1); i
< 8; i
++)
126 radeon_enc_code_fixed_bits(enc
, 0x0, 2);
129 radeon_enc_code_ue(enc
, 0x0);
130 radeon_enc_code_ue(enc
, enc
->enc_pic
.chroma_format_idc
);
131 radeon_enc_code_ue(enc
, enc
->enc_pic
.session_init
.aligned_picture_width
);
132 radeon_enc_code_ue(enc
, enc
->enc_pic
.session_init
.aligned_picture_height
);
133 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
134 radeon_enc_code_ue(enc
, enc
->enc_pic
.bit_depth_luma_minus8
);
135 radeon_enc_code_ue(enc
, enc
->enc_pic
.bit_depth_chroma_minus8
);
136 radeon_enc_code_ue(enc
, enc
->enc_pic
.log2_max_poc
- 4);
137 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
138 radeon_enc_code_ue(enc
, 1);
139 radeon_enc_code_ue(enc
, 0x0);
140 radeon_enc_code_ue(enc
, 0x0);
141 radeon_enc_code_ue(enc
, enc
->enc_pic
.hevc_spec_misc
.log2_min_luma_coding_block_size_minus3
);
142 //Only support CTBSize 64
143 radeon_enc_code_ue(enc
, 6 - (enc
->enc_pic
.hevc_spec_misc
.log2_min_luma_coding_block_size_minus3
+ 3));
144 radeon_enc_code_ue(enc
, enc
->enc_pic
.log2_min_transform_block_size_minus2
);
145 radeon_enc_code_ue(enc
, enc
->enc_pic
.log2_diff_max_min_transform_block_size
);
146 radeon_enc_code_ue(enc
, enc
->enc_pic
.max_transform_hierarchy_depth_inter
);
147 radeon_enc_code_ue(enc
, enc
->enc_pic
.max_transform_hierarchy_depth_intra
);
149 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
150 radeon_enc_code_fixed_bits(enc
, !enc
->enc_pic
.hevc_spec_misc
.amp_disabled
, 1);
151 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.sample_adaptive_offset_enabled_flag
, 1);
152 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.pcm_enabled_flag
, 1);
154 radeon_enc_code_ue(enc
, 1);
155 radeon_enc_code_ue(enc
, 1);
156 radeon_enc_code_ue(enc
, 0);
157 radeon_enc_code_ue(enc
, 0);
158 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
160 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
162 radeon_enc_code_fixed_bits(enc
, 0, 1);
163 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.hevc_spec_misc
.strong_intra_smoothing_enabled
, 1);
165 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
167 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
169 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
171 radeon_enc_byte_align(enc
);
172 radeon_enc_flush_headers(enc
);
173 *size_in_bytes
= (enc
->bits_output
+ 7) / 8;
177 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder
*enc
)
179 RADEON_ENC_BEGIN(enc
->cmd
.nalu
);
180 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS
);
181 uint32_t *size_in_bytes
= &enc
->cs
->current
.buf
[enc
->cs
->current
.cdw
++];
182 radeon_enc_reset(enc
);
183 radeon_enc_set_emulation_prevention(enc
, false);
184 radeon_enc_code_fixed_bits(enc
, 0x00000001, 32);
185 radeon_enc_code_fixed_bits(enc
, 0x4401, 16);
186 radeon_enc_byte_align(enc
);
187 radeon_enc_set_emulation_prevention(enc
, true);
188 radeon_enc_code_ue(enc
, 0x0);
189 radeon_enc_code_ue(enc
, 0x0);
190 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
191 radeon_enc_code_fixed_bits(enc
, 0x0, 4);
192 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
193 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
194 radeon_enc_code_ue(enc
, 0x0);
195 radeon_enc_code_ue(enc
, 0x0);
196 radeon_enc_code_se(enc
, 0x0);
197 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.hevc_spec_misc
.constrained_intra_pred_flag
, 1);
198 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
199 if (enc
->enc_pic
.rc_session_init
.rate_control_method
==
200 RENCODE_RATE_CONTROL_METHOD_NONE
)
201 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
203 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
204 radeon_enc_code_ue(enc
, 0x0);
206 radeon_enc_code_se(enc
, enc
->enc_pic
.hevc_deblock
.cb_qp_offset
);
207 radeon_enc_code_se(enc
, enc
->enc_pic
.hevc_deblock
.cr_qp_offset
);
208 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
209 radeon_enc_code_fixed_bits(enc
, 0x0, 2);
210 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
211 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
212 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
213 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.hevc_deblock
.loop_filter_across_slices_enabled
, 1);
214 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
215 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
216 radeon_enc_code_fixed_bits(enc
, enc
->enc_pic
.hevc_deblock
.deblocking_filter_disabled
, 1);
218 if (!enc
->enc_pic
.hevc_deblock
.deblocking_filter_disabled
) {
219 radeon_enc_code_se(enc
, enc
->enc_pic
.hevc_deblock
.beta_offset_div2
);
220 radeon_enc_code_se(enc
, enc
->enc_pic
.hevc_deblock
.tc_offset_div2
);
223 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
224 radeon_enc_code_fixed_bits(enc
, 0x0, 1);
225 radeon_enc_code_ue(enc
, enc
->enc_pic
.log2_parallel_merge_level_minus2
);
226 radeon_enc_code_fixed_bits(enc
, 0x0, 2);
228 radeon_enc_code_fixed_bits(enc
, 0x1, 1);
230 radeon_enc_byte_align(enc
);
231 radeon_enc_flush_headers(enc
);
232 *size_in_bytes
= (enc
->bits_output
+ 7) / 8;
236 static void radeon_enc_input_format(struct radeon_encoder
*enc
)
238 RADEON_ENC_BEGIN(enc
->cmd
.input_format
);
249 static void radeon_enc_output_format(struct radeon_encoder
*enc
)
251 RADEON_ENC_BEGIN(enc
->cmd
.output_format
);
262 static void encode(struct radeon_encoder
*enc
)
264 enc
->session_info(enc
);
265 enc
->total_task_size
= 0;
266 enc
->task_info(enc
, enc
->need_feedback
);
268 enc
->encode_headers(enc
);
272 enc
->intra_refresh(enc
);
273 enc
->input_format(enc
);
274 enc
->output_format(enc
);
278 *enc
->p_task_size
= (enc
->total_task_size
);
281 void radeon_enc_2_0_init(struct radeon_encoder
*enc
)
283 radeon_enc_1_2_init(enc
);
284 enc
->encode
= encode
;
285 enc
->quality_params
= radeon_enc_quality_params
;
286 enc
->input_format
= radeon_enc_input_format
;
287 enc
->output_format
= radeon_enc_output_format
;
289 if (u_reduce_video_profile(enc
->base
.profile
) == PIPE_VIDEO_FORMAT_HEVC
) {
290 enc
->deblocking_filter
= radeon_enc_loop_filter_hevc
;
291 enc
->nalu_sps
= radeon_enc_nalu_sps_hevc
;
292 enc
->nalu_pps
= radeon_enc_nalu_pps_hevc
;
295 enc
->cmd
.session_info
= RENCODE_IB_PARAM_SESSION_INFO
;
296 enc
->cmd
.task_info
= RENCODE_IB_PARAM_TASK_INFO
;
297 enc
->cmd
.session_init
= RENCODE_IB_PARAM_SESSION_INIT
;
298 enc
->cmd
.layer_control
= RENCODE_IB_PARAM_LAYER_CONTROL
;
299 enc
->cmd
.layer_select
= RENCODE_IB_PARAM_LAYER_SELECT
;
300 enc
->cmd
.rc_session_init
= RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT
;
301 enc
->cmd
.rc_layer_init
= RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT
;
302 enc
->cmd
.rc_per_pic
= RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE
;
303 enc
->cmd
.quality_params
= RENCODE_IB_PARAM_QUALITY_PARAMS
;
304 enc
->cmd
.nalu
= RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU
;
305 enc
->cmd
.slice_header
= RENCODE_IB_PARAM_SLICE_HEADER
;
306 enc
->cmd
.input_format
= RENCODE_IB_PARAM_INPUT_FORMAT
;
307 enc
->cmd
.output_format
= RENCODE_IB_PARAM_OUTPUT_FORMAT
;
308 enc
->cmd
.enc_params
= RENCODE_IB_PARAM_ENCODE_PARAMS
;
309 enc
->cmd
.intra_refresh
= RENCODE_IB_PARAM_INTRA_REFRESH
;
310 enc
->cmd
.ctx
= RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER
;
311 enc
->cmd
.bitstream
= RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER
;
312 enc
->cmd
.feedback
= RENCODE_IB_PARAM_FEEDBACK_BUFFER
;
313 enc
->cmd
.slice_control_hevc
= RENCODE_HEVC_IB_PARAM_SLICE_CONTROL
;
314 enc
->cmd
.spec_misc_hevc
= RENCODE_HEVC_IB_PARAM_SPEC_MISC
;
315 enc
->cmd
.deblocking_filter_hevc
= RENCODE_HEVC_IB_PARAM_LOOP_FILTER
;
316 enc
->cmd
.slice_control_h264
= RENCODE_H264_IB_PARAM_SLICE_CONTROL
;
317 enc
->cmd
.spec_misc_h264
= RENCODE_H264_IB_PARAM_SPEC_MISC
;
318 enc
->cmd
.enc_params_h264
= RENCODE_H264_IB_PARAM_ENCODE_PARAMS
;
319 enc
->cmd
.deblocking_filter_h264
= RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER
;
321 enc
->enc_pic
.session_info
.interface_version
=
322 ((RENCODE_FW_INTERFACE_MAJOR_VERSION
<< RENCODE_IF_MAJOR_VERSION_SHIFT
) |
323 (RENCODE_FW_INTERFACE_MINOR_VERSION
<< RENCODE_IF_MINOR_VERSION_SHIFT
));