src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33
  34 #include "si_pipe.h"
  35 #include "radeon_video.h"
  36 #include "radeon_vcn_enc.h"
  37
  38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION              1
  39 #define RENCODE_FW_INTERFACE_MINOR_VERSION              1
  40
  41 #define RENCODE_IB_PARAM_SESSION_INFO                           0x00000001
  42 #define RENCODE_IB_PARAM_TASK_INFO                              0x00000002
  43 #define RENCODE_IB_PARAM_SESSION_INIT                           0x00000003
  44 #define RENCODE_IB_PARAM_LAYER_CONTROL                          0x00000004
  45 #define RENCODE_IB_PARAM_LAYER_SELECT                           0x00000005
  46 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT              0x00000006
  47 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT                0x00000007
  48 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE               0x00000008
  49 #define RENCODE_IB_PARAM_QUALITY_PARAMS                         0x00000009
  50 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU                     0x0000000a
  51 #define RENCODE_IB_PARAM_SLICE_HEADER                           0x0000000b
  52 #define RENCODE_IB_PARAM_INPUT_FORMAT                           0x0000000c
  53 #define RENCODE_IB_PARAM_OUTPUT_FORMAT                          0x0000000d
  54 #define RENCODE_IB_PARAM_ENCODE_PARAMS                          0x0000000f
  55 #define RENCODE_IB_PARAM_INTRA_REFRESH                          0x00000010
  56 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER                  0x00000011
  57 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER                 0x00000012
  58 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER                        0x00000015
  59
  60 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL                     0x00100001
  61 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC                         0x00100002
  62 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER                       0x00100003
  63
  64 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL                     0x00200001
  65 #define RENCODE_H264_IB_PARAM_SPEC_MISC                         0x00200002
  66 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS                     0x00200003
  67 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER                 0x00200004
  68
  69 static void radeon_enc_quality_params(struct radeon_encoder *enc)
  70 {
  71         enc->enc_pic.quality_params.vbaq_mode = 0;
  72         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
  73         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
  74         enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
  75
  76         RADEON_ENC_BEGIN(enc->cmd.quality_params);
  77         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
  78         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
  79         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
  80         RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
  81         RADEON_ENC_END();
  82 }
  83
  84 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
  85 {
  86         RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
  87         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
  88         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
  89         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
  90         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
  91         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
  92         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
  93         RADEON_ENC_CS(1);
  94         RADEON_ENC_END();
  95 }
  96
  97 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
  98 {
  99         RADEON_ENC_BEGIN(enc->cmd.nalu);
 100         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 101         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 102         int i;
 103
 104         radeon_enc_reset(enc);
 105         radeon_enc_set_emulation_prevention(enc, false);
 106         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 107         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 108         radeon_enc_byte_align(enc);
 109         radeon_enc_set_emulation_prevention(enc, true);
 110         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 111         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 112         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 113         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 114         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 115         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 116         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 117         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 118         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 119         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 120
 121         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 122                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 123
 124         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 125                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 126                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 127         }
 128
 129         radeon_enc_code_ue(enc, 0x0);
 130         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 131         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 132         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 133         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 134         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 135         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 136         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 137         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 138         radeon_enc_code_ue(enc, 1);
 139         radeon_enc_code_ue(enc, 0x0);
 140         radeon_enc_code_ue(enc, 0x0);
 141         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 142         //Only support CTBSize 64
 143         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 144         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 145         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 146         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 147         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 148
 149         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 150         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 151         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 152         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 153
 154         radeon_enc_code_ue(enc, 1);
 155         radeon_enc_code_ue(enc, 1);
 156         radeon_enc_code_ue(enc, 0);
 157         radeon_enc_code_ue(enc, 0);
 158         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 159
 160         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 161
 162         radeon_enc_code_fixed_bits(enc, 0, 1);
 163         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 164
 165         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 166
 167         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 168
 169         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 170
 171         radeon_enc_byte_align(enc);
 172         radeon_enc_flush_headers(enc);
 173         *size_in_bytes = (enc->bits_output + 7) / 8;
 174         RADEON_ENC_END();
 175 }
 176
 177 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 178 {
 179         RADEON_ENC_BEGIN(enc->cmd.nalu);
 180         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 181         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 182         radeon_enc_reset(enc);
 183         radeon_enc_set_emulation_prevention(enc, false);
 184         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 185         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 186         radeon_enc_byte_align(enc);
 187         radeon_enc_set_emulation_prevention(enc, true);
 188         radeon_enc_code_ue(enc, 0x0);
 189         radeon_enc_code_ue(enc, 0x0);
 190         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 191         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 192         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 193         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 194         radeon_enc_code_ue(enc, 0x0);
 195         radeon_enc_code_ue(enc, 0x0);
 196         radeon_enc_code_se(enc, 0x0);
 197         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 198         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 199         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 200         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 201         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 202         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 203         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 204         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 205         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 206         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 207         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 208         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 209         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 210         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 211
 212         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 213                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 214                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 215         }
 216
 217         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 218         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 219         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 220         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 221
 222         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 223
 224         radeon_enc_byte_align(enc);
 225         radeon_enc_flush_headers(enc);
 226         *size_in_bytes = (enc->bits_output + 7) / 8;
 227         RADEON_ENC_END();
 228 }
 229
 230 static void radeon_enc_input_format(struct radeon_encoder *enc)
 231 {
 232         RADEON_ENC_BEGIN(enc->cmd.input_format);
 233         RADEON_ENC_CS(0);
 234         RADEON_ENC_CS(0);
 235         RADEON_ENC_CS(0);
 236         RADEON_ENC_CS(0);
 237         RADEON_ENC_CS(0);
 238         RADEON_ENC_CS(0);
 239         RADEON_ENC_CS(0);
 240         RADEON_ENC_END();
 241 }
 242
 243 static void radeon_enc_output_format(struct radeon_encoder *enc)
 244 {
 245         RADEON_ENC_BEGIN(enc->cmd.output_format);
 246         RADEON_ENC_CS(0);
 247         RADEON_ENC_CS(0);
 248         RADEON_ENC_CS(0);
 249         RADEON_ENC_CS(0);
 250         RADEON_ENC_CS(0);
 251         RADEON_ENC_CS(0);
 252         RADEON_ENC_CS(0);
 253         RADEON_ENC_END();
 254 }
 255
 256 static void encode(struct radeon_encoder *enc)
 257 {
 258         enc->session_info(enc);
 259         enc->total_task_size = 0;
 260         enc->task_info(enc, enc->need_feedback);
 261
 262         enc->encode_headers(enc);
 263         enc->ctx(enc);
 264         enc->bitstream(enc);
 265         enc->feedback(enc);
 266         enc->intra_refresh(enc);
 267         enc->input_format(enc);
 268         enc->output_format(enc);
 269
 270         enc->op_speed(enc);
 271         enc->op_enc(enc);
 272         *enc->p_task_size = (enc->total_task_size);
 273 }
 274
 275 void radeon_enc_2_0_init(struct radeon_encoder *enc)
 276 {
 277         radeon_enc_1_2_init(enc);
 278         enc->encode = encode;
 279         enc->quality_params = radeon_enc_quality_params;
 280         enc->input_format = radeon_enc_input_format;
 281         enc->output_format = radeon_enc_output_format;
 282
 283         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
 284                 enc->deblocking_filter = radeon_enc_loop_filter_hevc;
 285                 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
 286                 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
 287         }
 288
 289         enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
 290         enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
 291         enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
 292         enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
 293         enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
 294         enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
 295         enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
 296         enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
 297         enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
 298         enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
 299         enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
 300         enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
 301         enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
 302         enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
 303         enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
 304         enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
 305         enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
 306         enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
 307         enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
 308         enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
 309         enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
 310         enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
 311         enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
 312         enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
 313         enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
 314
 315         enc->enc_pic.session_info.interface_version =
 316                 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 317                 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 318 }