src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2017 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33
  34 #include "si_pipe.h"
  35 #include "radeon_video.h"
  36 #include "radeon_vcn_enc.h"
  37
  38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION              1
  39 #define RENCODE_FW_INTERFACE_MINOR_VERSION              1
  40
  41 #define RENCODE_IB_PARAM_SESSION_INFO                           0x00000001
  42 #define RENCODE_IB_PARAM_TASK_INFO                              0x00000002
  43 #define RENCODE_IB_PARAM_SESSION_INIT                           0x00000003
  44 #define RENCODE_IB_PARAM_LAYER_CONTROL                          0x00000004
  45 #define RENCODE_IB_PARAM_LAYER_SELECT                           0x00000005
  46 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT              0x00000006
  47 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT                0x00000007
  48 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE               0x00000008
  49 #define RENCODE_IB_PARAM_QUALITY_PARAMS                         0x00000009
  50 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU                     0x0000000a
  51 #define RENCODE_IB_PARAM_SLICE_HEADER                           0x0000000b
  52 #define RENCODE_IB_PARAM_INPUT_FORMAT                           0x0000000c
  53 #define RENCODE_IB_PARAM_OUTPUT_FORMAT                          0x0000000d
  54 #define RENCODE_IB_PARAM_ENCODE_PARAMS                          0x0000000f
  55 #define RENCODE_IB_PARAM_INTRA_REFRESH                          0x00000010
  56 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER                  0x00000011
  57 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER                 0x00000012
  58 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER                        0x00000015
  59
  60 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL                     0x00100001
  61 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC                         0x00100002
  62 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER                       0x00100003
  63
  64 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL                     0x00200001
  65 #define RENCODE_H264_IB_PARAM_SPEC_MISC                         0x00200002
  66 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS                     0x00200003
  67 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER                 0x00200004
  68
  69 #define RENCODE_COLOR_VOLUME_G22_BT709                          0
  70 #define RENCODE_COLOR_VOLUME_G10_BT2020                         3
  71
  72 #define RENCODE_COLOR_BIT_DEPTH_8_BIT                           0
  73 #define RENCODE_COLOR_BIT_DEPTH_10_BIT                          1
  74
  75 #define RENCODE_COLOR_PACKING_FORMAT_NV12                       0
  76 #define RENCODE_COLOR_PACKING_FORMAT_P010                       1
  77
  78
  79 static void radeon_enc_quality_params(struct radeon_encoder *enc)
  80 {
  81         enc->enc_pic.quality_params.vbaq_mode = 0;
  82         enc->enc_pic.quality_params.scene_change_sensitivity = 0;
  83         enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
  84         enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
  85
  86         RADEON_ENC_BEGIN(enc->cmd.quality_params);
  87         RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
  88         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
  89         RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
  90         RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
  91         RADEON_ENC_END();
  92 }
  93
  94 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
  95 {
  96         RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
  97         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
  98         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
  99         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
 100         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
 101         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
 102         RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
 103         RADEON_ENC_CS(1);
 104         RADEON_ENC_END();
 105 }
 106
 107 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
 108 {
 109         RADEON_ENC_BEGIN(enc->cmd.nalu);
 110         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
 111         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 112         int i;
 113
 114         radeon_enc_reset(enc);
 115         radeon_enc_set_emulation_prevention(enc, false);
 116         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 117         radeon_enc_code_fixed_bits(enc, 0x4201, 16);
 118         radeon_enc_byte_align(enc);
 119         radeon_enc_set_emulation_prevention(enc, true);
 120         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 121         radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
 122         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 123         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 124         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
 125         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
 126         radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
 127         radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
 128         radeon_enc_code_fixed_bits(enc, 0x0, 16);
 129         radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
 130
 131         for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) ; i++)
 132                 radeon_enc_code_fixed_bits(enc, 0x0, 2);
 133
 134         if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
 135                 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
 136                         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 137         }
 138
 139         radeon_enc_code_ue(enc, 0x0);
 140         radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
 141         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
 142         radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
 143         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 144         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
 145         radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
 146         radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
 147         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 148         radeon_enc_code_ue(enc, 1);
 149         radeon_enc_code_ue(enc, 0x0);
 150         radeon_enc_code_ue(enc, 0x0);
 151         radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
 152         //Only support CTBSize 64
 153         radeon_enc_code_ue(enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
 154         radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
 155         radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
 156         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
 157         radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
 158
 159         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 160         radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
 161         radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
 162         radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
 163
 164         radeon_enc_code_ue(enc, 1);
 165         radeon_enc_code_ue(enc, 1);
 166         radeon_enc_code_ue(enc, 0);
 167         radeon_enc_code_ue(enc, 0);
 168         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 169
 170         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 171
 172         radeon_enc_code_fixed_bits(enc, 0, 1);
 173         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
 174
 175         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 176
 177         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 178
 179         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 180
 181         radeon_enc_byte_align(enc);
 182         radeon_enc_flush_headers(enc);
 183         *size_in_bytes = (enc->bits_output + 7) / 8;
 184         RADEON_ENC_END();
 185 }
 186
 187 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 188 {
 189         RADEON_ENC_BEGIN(enc->cmd.nalu);
 190         RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
 191         uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
 192         radeon_enc_reset(enc);
 193         radeon_enc_set_emulation_prevention(enc, false);
 194         radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
 195         radeon_enc_code_fixed_bits(enc, 0x4401, 16);
 196         radeon_enc_byte_align(enc);
 197         radeon_enc_set_emulation_prevention(enc, true);
 198         radeon_enc_code_ue(enc, 0x0);
 199         radeon_enc_code_ue(enc, 0x0);
 200         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 201         radeon_enc_code_fixed_bits(enc, 0x0, 4);
 202         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 203         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 204         radeon_enc_code_ue(enc, 0x0);
 205         radeon_enc_code_ue(enc, 0x0);
 206         radeon_enc_code_se(enc, 0x0);
 207         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 208         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 209         if (enc->enc_pic.rc_session_init.rate_control_method ==
 210                 RENCODE_RATE_CONTROL_METHOD_NONE)
 211                 radeon_enc_code_fixed_bits(enc, 0x0, 1);
 212         else {
 213                 radeon_enc_code_fixed_bits(enc, 0x1, 1);
 214                 radeon_enc_code_ue(enc, 0x0);
 215         }
 216         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 217         radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 218         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 219         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 220         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 221         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 222         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 223         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
 224         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 225         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 226         radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
 227
 228         if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
 229                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
 230                 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
 231         }
 232
 233         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 234         radeon_enc_code_fixed_bits(enc, 0x0, 1);
 235         radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
 236         radeon_enc_code_fixed_bits(enc, 0x0, 2);
 237
 238         radeon_enc_code_fixed_bits(enc, 0x1, 1);
 239
 240         radeon_enc_byte_align(enc);
 241         radeon_enc_flush_headers(enc);
 242         *size_in_bytes = (enc->bits_output + 7) / 8;
 243         RADEON_ENC_END();
 244 }
 245
 246
 247 static void radeon_enc_input_format(struct radeon_encoder *enc)
 248 {
 249         RADEON_ENC_BEGIN(enc->cmd.input_format);
 250         if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
 251                 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
 252                 RADEON_ENC_CS(0);
 253                 RADEON_ENC_CS(0);
 254                 RADEON_ENC_CS(0);
 255                 RADEON_ENC_CS(0);
 256                 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
 257                 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_P010);
 258         } else {
 259                 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
 260                 RADEON_ENC_CS(0);
 261                 RADEON_ENC_CS(0);
 262                 RADEON_ENC_CS(0);
 263                 RADEON_ENC_CS(0);
 264                 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
 265                 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_NV12);
 266         }
 267         RADEON_ENC_END();
 268 }
 269
 270 static void radeon_enc_output_format(struct radeon_encoder *enc)
 271 {
 272         RADEON_ENC_BEGIN(enc->cmd.output_format);
 273         if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
 274                 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
 275                 RADEON_ENC_CS(0);
 276                 RADEON_ENC_CS(0);
 277                 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
 278         } else {
 279                 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
 280                 RADEON_ENC_CS(0);
 281                 RADEON_ENC_CS(0);
 282                 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
 283         }
 284         RADEON_ENC_END();
 285 }
 286
 287 static void radeon_enc_ctx(struct radeon_encoder *enc)
 288 {
 289         enc->enc_pic.ctx_buf.swizzle_mode = 0;
 290
 291         uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
 292         uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
 293
 294         enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
 295         enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
 296
 297         int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
 298         if (enc->enc_pic.bit_depth_luma_minus8 == 2)
 299                 luma_size *= 2;
 300         int chroma_size = align(luma_size / 2, enc->alignment);
 301         int offset = 0;
 302
 303         enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
 304         for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
 305                 enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
 306                 offset += luma_size;
 307                 enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
 308                 offset += chroma_size;
 309         }
 310
 311         RADEON_ENC_BEGIN(enc->cmd.ctx);
 312         RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
 313         RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
 314         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
 315         RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
 316         RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
 317
 318         for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
 319                 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
 320                 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
 321         }
 322
 323         for (int i = 0; i < 136 ; i++)
 324                 RADEON_ENC_CS(0x00000000);
 325
 326         RADEON_ENC_END();
 327 }
 328
 329
 330 static void encode(struct radeon_encoder *enc)
 331 {
 332         enc->session_info(enc);
 333         enc->total_task_size = 0;
 334         enc->task_info(enc, enc->need_feedback);
 335
 336         enc->encode_headers(enc);
 337         enc->ctx(enc);
 338         enc->bitstream(enc);
 339         enc->feedback(enc);
 340         enc->intra_refresh(enc);
 341         enc->input_format(enc);
 342         enc->output_format(enc);
 343
 344         enc->op_speed(enc);
 345         enc->op_enc(enc);
 346         *enc->p_task_size = (enc->total_task_size);
 347 }
 348
 349 void radeon_enc_2_0_init(struct radeon_encoder *enc)
 350 {
 351         radeon_enc_1_2_init(enc);
 352         enc->encode = encode;
 353         enc->ctx = radeon_enc_ctx;
 354         enc->quality_params = radeon_enc_quality_params;
 355         enc->input_format = radeon_enc_input_format;
 356         enc->output_format = radeon_enc_output_format;
 357
 358         if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
 359                 enc->deblocking_filter = radeon_enc_loop_filter_hevc;
 360                 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
 361                 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
 362         }
 363
 364         enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
 365         enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
 366         enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
 367         enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
 368         enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
 369         enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
 370         enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
 371         enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
 372         enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
 373         enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
 374         enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
 375         enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
 376         enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
 377         enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
 378         enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
 379         enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
 380         enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
 381         enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
 382         enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
 383         enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
 384         enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
 385         enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
 386         enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
 387         enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
 388         enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
 389
 390         enc->enc_pic.session_info.interface_version =
 391                 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 392                 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 393 }