src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2020 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_video_codec.h"
  31
  32 #include "util/u_video.h"
  33
  34 #include "si_pipe.h"
  35 #include "radeon_video.h"
  36 #include "radeon_vcn_enc.h"
  37
  38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION   0
  39 #define RENCODE_FW_INTERFACE_MINOR_VERSION   0
  40
  41 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
  42 {
  43    enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
  44    enc->enc_pic.spec_misc.cabac_enable = 0;
  45    enc->enc_pic.spec_misc.cabac_init_idc = 0;
  46    enc->enc_pic.spec_misc.half_pel_enabled = 1;
  47    enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
  48    enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
  49    enc->enc_pic.spec_misc.level_idc = enc->base.level;
  50    enc->enc_pic.spec_misc.b_picture_enabled = 0;
  51    enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
  52
  53    RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
  54    RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
  55    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
  56    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
  57    RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
  58    RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
  59    RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
  60    RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
  61    RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
  62    RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
  63    RADEON_ENC_END();
  64 }
  65
  66 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
  67 {
  68    enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
  69    enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0;
  70    enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
  71    enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF;
  72    enc->enc_pic.h264_enc_params.l1_reference_picture0_index= 0xFFFFFFFF;
  73
  74    RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
  75    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
  76    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
  77    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
  78    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type);
  79    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term);
  80    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure);
  81    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt);
  82    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index);
  83    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type);
  84    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term);
  85    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure);
  86    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt);
  87    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index);
  88    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type);
  89    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term);
  90    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure);
  91    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt);
  92    RADEON_ENC_END();
  93 }
  94
  95 void radeon_enc_3_0_init(struct radeon_encoder *enc)
  96 {
  97    radeon_enc_2_0_init(enc);
  98
  99    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 100       enc->spec_misc = radeon_enc_spec_misc;
 101       enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
 102    }
 103
 104    enc->enc_pic.session_info.interface_version =
 105       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
 106       (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
 107 }