1 /**************************************************************************
3 * Copyright 2013 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 * Christian König <christian.koenig@amd.com>
36 #include "util/u_memory.h"
37 #include "util/u_video.h"
39 #include "vl/vl_defines.h"
40 #include "vl/vl_video_buffer.h"
42 #include "r600_pipe_common.h"
43 #include "radeon_video.h"
44 #include "radeon_vce.h"
46 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
48 /* generate an stream handle */
49 unsigned rvid_alloc_stream_handle()
51 static unsigned counter
= 0;
52 unsigned stream_handle
= 0;
53 unsigned pid
= getpid();
56 for (i
= 0; i
< 32; ++i
)
57 stream_handle
|= ((pid
>> i
) & 1) << (31 - i
);
59 stream_handle
^= ++counter
;
63 /* create a buffer in the winsys */
64 bool rvid_create_buffer(struct pipe_screen
*screen
, struct rvid_buffer
*buffer
,
65 unsigned size
, unsigned usage
)
67 memset(buffer
, 0, sizeof(*buffer
));
68 buffer
->usage
= usage
;
70 /* Hardware buffer placement restrictions require the kernel to be
71 * able to move buffers around individually, so request a
72 * non-sub-allocated buffer.
74 buffer
->res
= (struct r600_resource
*)
75 pipe_buffer_create(screen
, PIPE_BIND_SHARED
,
78 return buffer
->res
!= NULL
;
81 /* destroy a buffer */
82 void rvid_destroy_buffer(struct rvid_buffer
*buffer
)
84 r600_resource_reference(&buffer
->res
, NULL
);
87 /* reallocate a buffer, preserving its content */
88 bool rvid_resize_buffer(struct pipe_screen
*screen
, struct radeon_winsys_cs
*cs
,
89 struct rvid_buffer
*new_buf
, unsigned new_size
)
91 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
92 struct radeon_winsys
* ws
= rscreen
->ws
;
93 unsigned bytes
= MIN2(new_buf
->res
->buf
->size
, new_size
);
94 struct rvid_buffer old_buf
= *new_buf
;
95 void *src
= NULL
, *dst
= NULL
;
97 if (!rvid_create_buffer(screen
, new_buf
, new_size
, new_buf
->usage
))
100 src
= ws
->buffer_map(old_buf
.res
->buf
, cs
, PIPE_TRANSFER_READ
);
104 dst
= ws
->buffer_map(new_buf
->res
->buf
, cs
, PIPE_TRANSFER_WRITE
);
108 memcpy(dst
, src
, bytes
);
109 if (new_size
> bytes
) {
112 memset(dst
, 0, new_size
);
114 ws
->buffer_unmap(new_buf
->res
->buf
);
115 ws
->buffer_unmap(old_buf
.res
->buf
);
116 rvid_destroy_buffer(&old_buf
);
121 ws
->buffer_unmap(old_buf
.res
->buf
);
122 rvid_destroy_buffer(new_buf
);
127 /* clear the buffer with zeros */
128 void rvid_clear_buffer(struct pipe_context
*context
, struct rvid_buffer
* buffer
)
130 struct r600_common_context
*rctx
= (struct r600_common_context
*)context
;
132 rctx
->dma_clear_buffer(context
, &buffer
->res
->b
.b
, 0,
133 buffer
->res
->buf
->size
, 0);
134 context
->flush(context
, NULL
, 0);
138 * join surfaces into the same buffer with identical tiling params
139 * sumup their sizes and replace the backend buffers with a single bo
141 void rvid_join_surfaces(struct r600_common_context
*rctx
,
142 struct pb_buffer
** buffers
[VL_NUM_COMPONENTS
],
143 struct radeon_surf
*surfaces
[VL_NUM_COMPONENTS
])
145 struct radeon_winsys
* ws
;
146 unsigned best_tiling
, best_wh
, off
;
147 unsigned size
, alignment
;
148 struct pb_buffer
*pb
;
153 for (i
= 0, best_tiling
= 0, best_wh
= ~0; i
< VL_NUM_COMPONENTS
; ++i
) {
159 if (rctx
->chip_class
< GFX9
) {
160 /* choose the smallest bank w/h for now */
161 wh
= surfaces
[i
]->u
.legacy
.bankw
* surfaces
[i
]->u
.legacy
.bankh
;
169 for (i
= 0, off
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
173 /* adjust the texture layer offsets */
174 off
= align(off
, surfaces
[i
]->surf_alignment
);
176 if (rctx
->chip_class
< GFX9
) {
177 /* copy the tiling parameters */
178 surfaces
[i
]->u
.legacy
.bankw
= surfaces
[best_tiling
]->u
.legacy
.bankw
;
179 surfaces
[i
]->u
.legacy
.bankh
= surfaces
[best_tiling
]->u
.legacy
.bankh
;
180 surfaces
[i
]->u
.legacy
.mtilea
= surfaces
[best_tiling
]->u
.legacy
.mtilea
;
181 surfaces
[i
]->u
.legacy
.tile_split
= surfaces
[best_tiling
]->u
.legacy
.tile_split
;
183 for (j
= 0; j
< ARRAY_SIZE(surfaces
[i
]->u
.legacy
.level
); ++j
)
184 surfaces
[i
]->u
.legacy
.level
[j
].offset
+= off
;
186 surfaces
[i
]->u
.gfx9
.surf_offset
+= off
;
188 off
+= surfaces
[i
]->surf_size
;
191 for (i
= 0, size
= 0, alignment
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
192 if (!buffers
[i
] || !*buffers
[i
])
195 size
= align(size
, (*buffers
[i
])->alignment
);
196 size
+= (*buffers
[i
])->size
;
197 alignment
= MAX2(alignment
, (*buffers
[i
])->alignment
* 1);
203 /* TODO: 2D tiling workaround */
206 pb
= ws
->buffer_create(ws
, size
, alignment
, RADEON_DOMAIN_VRAM
,
211 for (i
= 0; i
< VL_NUM_COMPONENTS
; ++i
) {
212 if (!buffers
[i
] || !*buffers
[i
])
215 pb_reference(buffers
[i
], pb
);
218 pb_reference(&pb
, NULL
);
221 int rvid_get_video_param(struct pipe_screen
*screen
,
222 enum pipe_video_profile profile
,
223 enum pipe_video_entrypoint entrypoint
,
224 enum pipe_video_cap param
)
226 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
227 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
228 struct radeon_info info
;
230 rscreen
->ws
->query_info(rscreen
->ws
, &info
);
232 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
234 case PIPE_VIDEO_CAP_SUPPORTED
:
235 return codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
236 rvce_is_fw_version_supported(rscreen
);
237 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
239 case PIPE_VIDEO_CAP_MAX_WIDTH
:
240 return (rscreen
->family
< CHIP_TONGA
) ? 2048 : 4096;
241 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
242 return (rscreen
->family
< CHIP_TONGA
) ? 1152 : 2304;
243 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
244 return PIPE_FORMAT_NV12
;
245 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
247 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
249 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
251 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
252 return (rscreen
->family
< CHIP_TONGA
) ? 1 : 2;
259 case PIPE_VIDEO_CAP_SUPPORTED
:
261 case PIPE_VIDEO_FORMAT_MPEG12
:
262 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
263 case PIPE_VIDEO_FORMAT_MPEG4
:
264 /* no support for MPEG4 on older hw */
265 return rscreen
->family
>= CHIP_PALM
;
266 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
267 if ((rscreen
->family
== CHIP_POLARIS10
||
268 rscreen
->family
== CHIP_POLARIS11
) &&
269 info
.uvd_fw_version
< UVD_FW_1_66_16
) {
270 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
274 case PIPE_VIDEO_FORMAT_VC1
:
276 case PIPE_VIDEO_FORMAT_HEVC
:
277 /* Carrizo only supports HEVC Main */
278 if (rscreen
->family
>= CHIP_STONEY
)
279 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
280 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
281 else if (rscreen
->family
>= CHIP_CARRIZO
)
282 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
284 case PIPE_VIDEO_FORMAT_JPEG
:
285 if (rscreen
->family
< CHIP_CARRIZO
|| rscreen
->family
>= CHIP_VEGA10
)
287 if (!(rscreen
->info
.drm_major
== 3 && rscreen
->info
.drm_minor
>= 19)) {
288 RVID_ERR("No MJPEG support for the kernel version\n");
295 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
297 case PIPE_VIDEO_CAP_MAX_WIDTH
:
298 return (rscreen
->family
< CHIP_TONGA
) ? 2048 : 4096;
299 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
300 return (rscreen
->family
< CHIP_TONGA
) ? 1152 : 4096;
301 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
302 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
303 return PIPE_FORMAT_P016
;
305 return PIPE_FORMAT_NV12
;
307 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
308 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
309 if (rscreen
->family
< CHIP_PALM
) {
310 /* MPEG2 only with shaders and no support for
311 interlacing on R6xx style UVD */
312 return codec
!= PIPE_VIDEO_FORMAT_MPEG12
&&
313 rscreen
->family
> CHIP_RV770
;
315 enum pipe_video_format format
= u_reduce_video_profile(profile
);
317 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
318 return false; //The firmware doesn't support interlaced HEVC.
319 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
323 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
325 case PIPE_VIDEO_CAP_MAX_LEVEL
:
327 case PIPE_VIDEO_PROFILE_MPEG1
:
329 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
330 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
332 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
334 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
336 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
338 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
340 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
342 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
343 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
344 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
345 return (rscreen
->family
< CHIP_TONGA
) ? 41 : 52;
346 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
347 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
357 boolean
rvid_is_format_supported(struct pipe_screen
*screen
,
358 enum pipe_format format
,
359 enum pipe_video_profile profile
,
360 enum pipe_video_entrypoint entrypoint
)
362 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
363 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
364 return (format
== PIPE_FORMAT_NV12
) ||
365 (format
== PIPE_FORMAT_P016
);
367 /* we can only handle this one with UVD */
368 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
369 return format
== PIPE_FORMAT_NV12
;
371 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);