src/gallium/drivers/radeon/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <unistd.h>
  29
  30 #include "util/u_memory.h"
  31 #include "util/u_video.h"
  32
  33 #include "vl/vl_defines.h"
  34 #include "vl/vl_video_buffer.h"
  35
  36 #include "r600_pipe_common.h"
  37 #include "radeon_video.h"
  38 #include "radeon_vce.h"
  39
  40 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
  41
  42 /* generate an stream handle */
  43 unsigned si_vid_alloc_stream_handle()
  44 {
  45         static unsigned counter = 0;
  46         unsigned stream_handle = 0;
  47         unsigned pid = getpid();
  48         int i;
  49
  50         for (i = 0; i < 32; ++i)
  51                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  52
  53         stream_handle ^= ++counter;
  54         return stream_handle;
  55 }
  56
  57 /* create a buffer in the winsys */
  58 bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
  59                           unsigned size, unsigned usage)
  60 {
  61         memset(buffer, 0, sizeof(*buffer));
  62         buffer->usage = usage;
  63
  64         /* Hardware buffer placement restrictions require the kernel to be
  65          * able to move buffers around individually, so request a
  66          * non-sub-allocated buffer.
  67          */
  68         buffer->res = (struct r600_resource *)
  69                 pipe_buffer_create(screen, PIPE_BIND_SHARED,
  70                                    usage, size);
  71
  72         return buffer->res != NULL;
  73 }
  74
  75 /* destroy a buffer */
  76 void si_vid_destroy_buffer(struct rvid_buffer *buffer)
  77 {
  78         r600_resource_reference(&buffer->res, NULL);
  79 }
  80
  81 /* reallocate a buffer, preserving its content */
  82 bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
  83                           struct rvid_buffer *new_buf, unsigned new_size)
  84 {
  85         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
  86         struct radeon_winsys* ws = rscreen->ws;
  87         unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
  88         struct rvid_buffer old_buf = *new_buf;
  89         void *src = NULL, *dst = NULL;
  90
  91         if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
  92                 goto error;
  93
  94         src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
  95         if (!src)
  96                 goto error;
  97
  98         dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
  99         if (!dst)
 100                 goto error;
 101
 102         memcpy(dst, src, bytes);
 103         if (new_size > bytes) {
 104                 new_size -= bytes;
 105                 dst += bytes;
 106                 memset(dst, 0, new_size);
 107         }
 108         ws->buffer_unmap(new_buf->res->buf);
 109         ws->buffer_unmap(old_buf.res->buf);
 110         si_vid_destroy_buffer(&old_buf);
 111         return true;
 112
 113 error:
 114         if (src)
 115                 ws->buffer_unmap(old_buf.res->buf);
 116         si_vid_destroy_buffer(new_buf);
 117         *new_buf = old_buf;
 118         return false;
 119 }
 120
 121 /* clear the buffer with zeros */
 122 void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 123 {
 124         struct r600_common_context *rctx = (struct r600_common_context*)context;
 125
 126         rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
 127                                buffer->res->buf->size, 0);
 128         context->flush(context, NULL, 0);
 129 }
 130
 131 /**
 132  * join surfaces into the same buffer with identical tiling params
 133  * sumup their sizes and replace the backend buffers with a single bo
 134  */
 135 void si_vid_join_surfaces(struct r600_common_context *rctx,
 136                           struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 137                           struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 138 {
 139         struct radeon_winsys* ws;
 140         unsigned best_tiling, best_wh, off;
 141         unsigned size, alignment;
 142         struct pb_buffer *pb;
 143         unsigned i, j;
 144
 145         ws = rctx->ws;
 146
 147         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 148                 unsigned wh;
 149
 150                 if (!surfaces[i])
 151                         continue;
 152
 153                 if (rctx->chip_class < GFX9) {
 154                         /* choose the smallest bank w/h for now */
 155                         wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
 156                         if (wh < best_wh) {
 157                                 best_wh = wh;
 158                                 best_tiling = i;
 159                         }
 160                 }
 161         }
 162
 163         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 164                 if (!surfaces[i])
 165                         continue;
 166
 167                 /* adjust the texture layer offsets */
 168                 off = align(off, surfaces[i]->surf_alignment);
 169
 170                 if (rctx->chip_class < GFX9) {
 171                         /* copy the tiling parameters */
 172                         surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
 173                         surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
 174                         surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
 175                         surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
 176
 177                         for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
 178                                 surfaces[i]->u.legacy.level[j].offset += off;
 179                 } else {
 180                         surfaces[i]->u.gfx9.surf_offset += off;
 181                         for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
 182                                 surfaces[i]->u.gfx9.offset[j] += off;
 183                 }
 184
 185                 off += surfaces[i]->surf_size;
 186         }
 187
 188         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 189                 if (!buffers[i] || !*buffers[i])
 190                         continue;
 191
 192                 size = align(size, (*buffers[i])->alignment);
 193                 size += (*buffers[i])->size;
 194                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 195         }
 196
 197         if (!size)
 198                 return;
 199
 200         /* TODO: 2D tiling workaround */
 201         alignment *= 2;
 202
 203         pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
 204                                RADEON_FLAG_GTT_WC);
 205         if (!pb)
 206                 return;
 207
 208         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 209                 if (!buffers[i] || !*buffers[i])
 210                         continue;
 211
 212                 pb_reference(buffers[i], pb);
 213         }
 214
 215         pb_reference(&pb, NULL);
 216 }
 217
 218 int si_vid_get_video_param(struct pipe_screen *screen,
 219                            enum pipe_video_profile profile,
 220                            enum pipe_video_entrypoint entrypoint,
 221                            enum pipe_video_cap param)
 222 {
 223         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 224         enum pipe_video_format codec = u_reduce_video_profile(profile);
 225         struct radeon_info info;
 226
 227         rscreen->ws->query_info(rscreen->ws, &info);
 228
 229         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 230                 switch (param) {
 231                 case PIPE_VIDEO_CAP_SUPPORTED:
 232                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 233                                 si_vce_is_fw_version_supported(rscreen);
 234                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 235                         return 1;
 236                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 237                         return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 238                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 239                         return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
 240                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 241                         return PIPE_FORMAT_NV12;
 242                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 243                         return false;
 244                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 245                         return false;
 246                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 247                         return true;
 248                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 249                         return (rscreen->family < CHIP_TONGA) ? 1 : 2;
 250                 default:
 251                         return 0;
 252                 }
 253         }
 254
 255         switch (param) {
 256         case PIPE_VIDEO_CAP_SUPPORTED:
 257                 switch (codec) {
 258                 case PIPE_VIDEO_FORMAT_MPEG12:
 259                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 260                 case PIPE_VIDEO_FORMAT_MPEG4:
 261                         return 1;
 262                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 263                         if ((rscreen->family == CHIP_POLARIS10 ||
 264                              rscreen->family == CHIP_POLARIS11) &&
 265                             info.uvd_fw_version < UVD_FW_1_66_16 ) {
 266                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 267                                 return false;
 268                         }
 269                         return true;
 270                 case PIPE_VIDEO_FORMAT_VC1:
 271                         return true;
 272                 case PIPE_VIDEO_FORMAT_HEVC:
 273                         /* Carrizo only supports HEVC Main */
 274                         if (rscreen->family >= CHIP_STONEY)
 275                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 276                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 277                         else if (rscreen->family >= CHIP_CARRIZO)
 278                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 279                         return false;
 280                 case PIPE_VIDEO_FORMAT_JPEG:
 281                         if (rscreen->family < CHIP_CARRIZO || rscreen->family >= CHIP_VEGA10)
 282                                 return false;
 283                         if (!(rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 19)) {
 284                                 RVID_ERR("No MJPEG support for the kernel version\n");
 285                                 return false;
 286                         }
 287                         return true;
 288                 default:
 289                         return false;
 290                 }
 291         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 292                 return 1;
 293         case PIPE_VIDEO_CAP_MAX_WIDTH:
 294                 return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 295         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 296                 return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
 297         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 298                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 299                         return PIPE_FORMAT_P016;
 300                 else
 301                         return PIPE_FORMAT_NV12;
 302
 303         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 304         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 305                 enum pipe_video_format format = u_reduce_video_profile(profile);
 306
 307                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 308                         return false; //The firmware doesn't support interlaced HEVC.
 309                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 310                         return false;
 311                 return true;
 312         }
 313         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 314                 return true;
 315         case PIPE_VIDEO_CAP_MAX_LEVEL:
 316                 switch (profile) {
 317                 case PIPE_VIDEO_PROFILE_MPEG1:
 318                         return 0;
 319                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 320                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 321                         return 3;
 322                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 323                         return 3;
 324                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 325                         return 5;
 326                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 327                         return 1;
 328                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 329                         return 2;
 330                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 331                         return 4;
 332                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 333                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 334                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 335                         return (rscreen->family < CHIP_TONGA) ? 41 : 52;
 336                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 337                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 338                         return 186;
 339                 default:
 340                         return 0;
 341                 }
 342         default:
 343                 return 0;
 344         }
 345 }
 346
 347 boolean si_vid_is_format_supported(struct pipe_screen *screen,
 348                                    enum pipe_format format,
 349                                    enum pipe_video_profile profile,
 350                                    enum pipe_video_entrypoint entrypoint)
 351 {
 352         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 353         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 354                 return (format == PIPE_FORMAT_NV12) ||
 355                         (format == PIPE_FORMAT_P016);
 356
 357         /* we can only handle this one with UVD */
 358         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 359                 return format == PIPE_FORMAT_NV12;
 360
 361         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 362 }