src/gallium/drivers/radeon/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include "util/u_memory.h"
  37 #include "util/u_video.h"
  38
  39 #include "vl/vl_defines.h"
  40 #include "vl/vl_video_buffer.h"
  41
  42 #include "r600_pipe_common.h"
  43 #include "radeon_video.h"
  44 #include "radeon_vce.h"
  45
  46 #define UVD_FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
  47
  48 /* generate an stream handle */
  49 unsigned rvid_alloc_stream_handle()
  50 {
  51         static unsigned counter = 0;
  52         unsigned stream_handle = 0;
  53         unsigned pid = getpid();
  54         int i;
  55
  56         for (i = 0; i < 32; ++i)
  57                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  58
  59         stream_handle ^= ++counter;
  60         return stream_handle;
  61 }
  62
  63 /* create a buffer in the winsys */
  64 bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
  65                         unsigned size, unsigned usage)
  66 {
  67         memset(buffer, 0, sizeof(*buffer));
  68         buffer->usage = usage;
  69         buffer->res = (struct r600_resource *)
  70                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, usage, size);
  71
  72         return buffer->res != NULL;
  73 }
  74
  75 /* destroy a buffer */
  76 void rvid_destroy_buffer(struct rvid_buffer *buffer)
  77 {
  78         r600_resource_reference(&buffer->res, NULL);
  79 }
  80
  81 /* reallocate a buffer, preserving its content */
  82 bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
  83                         struct rvid_buffer *new_buf, unsigned new_size)
  84 {
  85         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
  86         struct radeon_winsys* ws = rscreen->ws;
  87         unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
  88         struct rvid_buffer old_buf = *new_buf;
  89         void *src = NULL, *dst = NULL;
  90
  91         if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
  92                 goto error;
  93
  94         src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
  95         if (!src)
  96                 goto error;
  97
  98         dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
  99         if (!dst)
 100                 goto error;
 101
 102         memcpy(dst, src, bytes);
 103         if (new_size > bytes) {
 104                 new_size -= bytes;
 105                 dst += bytes;
 106                 memset(dst, 0, new_size);
 107         }
 108         ws->buffer_unmap(new_buf->res->buf);
 109         ws->buffer_unmap(old_buf.res->buf);
 110         rvid_destroy_buffer(&old_buf);
 111         return true;
 112
 113 error:
 114         if (src)
 115                 ws->buffer_unmap(old_buf.res->buf);
 116         rvid_destroy_buffer(new_buf);
 117         *new_buf = old_buf;
 118         return false;
 119 }
 120
 121 /* clear the buffer with zeros */
 122 void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 123 {
 124         struct r600_common_context *rctx = (struct r600_common_context*)context;
 125
 126         rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
 127                            0, R600_COHERENCY_NONE);
 128         context->flush(context, NULL, 0);
 129 }
 130
 131 /**
 132  * join surfaces into the same buffer with identical tiling params
 133  * sumup their sizes and replace the backend buffers with a single bo
 134  */
 135 void rvid_join_surfaces(struct radeon_winsys* ws,
 136                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 137                         struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 138 {
 139         unsigned best_tiling, best_wh, off;
 140         unsigned size, alignment;
 141         struct pb_buffer *pb;
 142         unsigned i, j;
 143
 144         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 145                 unsigned wh;
 146
 147                 if (!surfaces[i])
 148                         continue;
 149
 150                 /* choose the smallest bank w/h for now */
 151                 wh = surfaces[i]->bankw * surfaces[i]->bankh;
 152                 if (wh < best_wh) {
 153                         best_wh = wh;
 154                         best_tiling = i;
 155                 }
 156         }
 157
 158         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 159                 if (!surfaces[i])
 160                         continue;
 161
 162                 /* copy the tiling parameters */
 163                 surfaces[i]->bankw = surfaces[best_tiling]->bankw;
 164                 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
 165                 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
 166                 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
 167
 168                 /* adjust the texture layer offsets */
 169                 off = align(off, surfaces[i]->bo_alignment);
 170                 for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
 171                         surfaces[i]->level[j].offset += off;
 172                 off += surfaces[i]->bo_size;
 173         }
 174
 175         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 176                 if (!buffers[i] || !*buffers[i])
 177                         continue;
 178
 179                 size = align(size, (*buffers[i])->alignment);
 180                 size += (*buffers[i])->size;
 181                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 182         }
 183
 184         if (!size)
 185                 return;
 186
 187         /* TODO: 2D tiling workaround */
 188         alignment *= 2;
 189
 190         pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
 191         if (!pb)
 192                 return;
 193
 194         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 195                 if (!buffers[i] || !*buffers[i])
 196                         continue;
 197
 198                 pb_reference(buffers[i], pb);
 199         }
 200
 201         pb_reference(&pb, NULL);
 202 }
 203
 204 int rvid_get_video_param(struct pipe_screen *screen,
 205                          enum pipe_video_profile profile,
 206                          enum pipe_video_entrypoint entrypoint,
 207                          enum pipe_video_cap param)
 208 {
 209         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 210         enum pipe_video_format codec = u_reduce_video_profile(profile);
 211         struct radeon_info info;
 212
 213         rscreen->ws->query_info(rscreen->ws, &info);
 214
 215         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 216                 switch (param) {
 217                 case PIPE_VIDEO_CAP_SUPPORTED:
 218                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 219                                 rvce_is_fw_version_supported(rscreen);
 220                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 221                         return 1;
 222                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 223                         return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 224                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 225                         return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
 226                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 227                         return PIPE_FORMAT_NV12;
 228                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 229                         return false;
 230                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 231                         return false;
 232                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 233                         return true;
 234                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 235                         return (rscreen->family < CHIP_TONGA) ? 1 : 2;
 236                 default:
 237                         return 0;
 238                 }
 239         }
 240
 241         switch (param) {
 242         case PIPE_VIDEO_CAP_SUPPORTED:
 243                 switch (codec) {
 244                 case PIPE_VIDEO_FORMAT_MPEG12:
 245                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 246                 case PIPE_VIDEO_FORMAT_MPEG4:
 247                         /* no support for MPEG4 on older hw */
 248                         return rscreen->family >= CHIP_PALM;
 249                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 250                         if ((rscreen->family == CHIP_POLARIS10 ||
 251                              rscreen->family == CHIP_POLARIS11) &&
 252                             info.uvd_fw_version < UVD_FW_1_66_16 ) {
 253                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 254                                 return false;
 255                         }
 256                         return true;
 257                 case PIPE_VIDEO_FORMAT_VC1:
 258                         return true;
 259                 case PIPE_VIDEO_FORMAT_HEVC:
 260                         /* Carrizo only supports HEVC Main */
 261                         if (rscreen->family >= CHIP_STONEY)
 262                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 263                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 264                         else if (rscreen->family >= CHIP_CARRIZO)
 265                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 266                 default:
 267                         return false;
 268                 }
 269         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 270                 return 1;
 271         case PIPE_VIDEO_CAP_MAX_WIDTH:
 272                 return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 273         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 274                 return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
 275         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 276                 return PIPE_FORMAT_NV12;
 277         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 278         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 279                 if (rscreen->family < CHIP_PALM) {
 280                         /* MPEG2 only with shaders and no support for
 281                            interlacing on R6xx style UVD */
 282                         return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
 283                                rscreen->family > CHIP_RV770;
 284                 } else {
 285                         if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
 286                                 return false; //The firmware doesn't support interlaced HEVC.
 287                         return true;
 288                 }
 289         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 290                 return true;
 291         case PIPE_VIDEO_CAP_MAX_LEVEL:
 292                 switch (profile) {
 293                 case PIPE_VIDEO_PROFILE_MPEG1:
 294                         return 0;
 295                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 296                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 297                         return 3;
 298                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 299                         return 3;
 300                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 301                         return 5;
 302                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 303                         return 1;
 304                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 305                         return 2;
 306                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 307                         return 4;
 308                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 309                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 310                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 311                         return (rscreen->family < CHIP_TONGA) ? 41 : 52;
 312                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 313                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 314                         return 186;
 315                 default:
 316                         return 0;
 317                 }
 318         default:
 319                 return 0;
 320         }
 321 }
 322
 323 boolean rvid_is_format_supported(struct pipe_screen *screen,
 324                                  enum pipe_format format,
 325                                  enum pipe_video_profile profile,
 326                                  enum pipe_video_entrypoint entrypoint)
 327 {
 328         /* we can only handle this one with UVD */
 329         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 330                 return format == PIPE_FORMAT_NV12;
 331
 332         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 333 }