src/gallium/drivers/radeon/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <unistd.h>
  29
  30 #include "util/u_memory.h"
  31 #include "util/u_video.h"
  32
  33 #include "vl/vl_defines.h"
  34 #include "vl/vl_video_buffer.h"
  35
  36 #include "radeonsi/si_pipe.h"
  37 #include "radeon_video.h"
  38 #include "radeon_vce.h"
  39
  40 /* generate an stream handle */
  41 unsigned si_vid_alloc_stream_handle()
  42 {
  43         static unsigned counter = 0;
  44         unsigned stream_handle = 0;
  45         unsigned pid = getpid();
  46         int i;
  47
  48         for (i = 0; i < 32; ++i)
  49                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  50
  51         stream_handle ^= ++counter;
  52         return stream_handle;
  53 }
  54
  55 /* create a buffer in the winsys */
  56 bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
  57                           unsigned size, unsigned usage)
  58 {
  59         memset(buffer, 0, sizeof(*buffer));
  60         buffer->usage = usage;
  61
  62         /* Hardware buffer placement restrictions require the kernel to be
  63          * able to move buffers around individually, so request a
  64          * non-sub-allocated buffer.
  65          */
  66         buffer->res = r600_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED,
  67                                                        usage, size));
  68
  69         return buffer->res != NULL;
  70 }
  71
  72 /* destroy a buffer */
  73 void si_vid_destroy_buffer(struct rvid_buffer *buffer)
  74 {
  75         r600_resource_reference(&buffer->res, NULL);
  76 }
  77
  78 /* reallocate a buffer, preserving its content */
  79 bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
  80                           struct rvid_buffer *new_buf, unsigned new_size)
  81 {
  82         struct si_screen *sscreen = (struct si_screen *)screen;
  83         struct radeon_winsys* ws = sscreen->ws;
  84         unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
  85         struct rvid_buffer old_buf = *new_buf;
  86         void *src = NULL, *dst = NULL;
  87
  88         if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
  89                 goto error;
  90
  91         src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
  92         if (!src)
  93                 goto error;
  94
  95         dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
  96         if (!dst)
  97                 goto error;
  98
  99         memcpy(dst, src, bytes);
 100         if (new_size > bytes) {
 101                 new_size -= bytes;
 102                 dst += bytes;
 103                 memset(dst, 0, new_size);
 104         }
 105         ws->buffer_unmap(new_buf->res->buf);
 106         ws->buffer_unmap(old_buf.res->buf);
 107         si_vid_destroy_buffer(&old_buf);
 108         return true;
 109
 110 error:
 111         if (src)
 112                 ws->buffer_unmap(old_buf.res->buf);
 113         si_vid_destroy_buffer(new_buf);
 114         *new_buf = old_buf;
 115         return false;
 116 }
 117
 118 /* clear the buffer with zeros */
 119 void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 120 {
 121         struct si_context *sctx = (struct si_context*)context;
 122
 123         sctx->dma_clear_buffer(sctx, &buffer->res->b.b, 0,
 124                                buffer->res->buf->size, 0);
 125         context->flush(context, NULL, 0);
 126 }
 127
 128 /**
 129  * join surfaces into the same buffer with identical tiling params
 130  * sumup their sizes and replace the backend buffers with a single bo
 131  */
 132 void si_vid_join_surfaces(struct si_context *sctx,
 133                           struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 134                           struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 135 {
 136         struct radeon_winsys *ws = sctx->ws;;
 137         unsigned best_tiling, best_wh, off;
 138         unsigned size, alignment;
 139         struct pb_buffer *pb;
 140         unsigned i, j;
 141
 142         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 143                 unsigned wh;
 144
 145                 if (!surfaces[i])
 146                         continue;
 147
 148                 if (sctx->chip_class < GFX9) {
 149                         /* choose the smallest bank w/h for now */
 150                         wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
 151                         if (wh < best_wh) {
 152                                 best_wh = wh;
 153                                 best_tiling = i;
 154                         }
 155                 }
 156         }
 157
 158         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 159                 if (!surfaces[i])
 160                         continue;
 161
 162                 /* adjust the texture layer offsets */
 163                 off = align(off, surfaces[i]->surf_alignment);
 164
 165                 if (sctx->chip_class < GFX9) {
 166                         /* copy the tiling parameters */
 167                         surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
 168                         surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
 169                         surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
 170                         surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
 171
 172                         for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
 173                                 surfaces[i]->u.legacy.level[j].offset += off;
 174                 } else {
 175                         surfaces[i]->u.gfx9.surf_offset += off;
 176                         for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
 177                                 surfaces[i]->u.gfx9.offset[j] += off;
 178                 }
 179
 180                 off += surfaces[i]->surf_size;
 181         }
 182
 183         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 184                 if (!buffers[i] || !*buffers[i])
 185                         continue;
 186
 187                 size = align(size, (*buffers[i])->alignment);
 188                 size += (*buffers[i])->size;
 189                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 190         }
 191
 192         if (!size)
 193                 return;
 194
 195         /* TODO: 2D tiling workaround */
 196         alignment *= 2;
 197
 198         pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
 199                                RADEON_FLAG_GTT_WC);
 200         if (!pb)
 201                 return;
 202
 203         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 204                 if (!buffers[i] || !*buffers[i])
 205                         continue;
 206
 207                 pb_reference(buffers[i], pb);
 208         }
 209
 210         pb_reference(&pb, NULL);
 211 }