src/gallium/drivers/radeon/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include "util/u_memory.h"
  37 #include "util/u_video.h"
  38
  39 #include "vl/vl_defines.h"
  40 #include "vl/vl_video_buffer.h"
  41
  42 #include "r600_pipe_common.h"
  43 #include "radeon_video.h"
  44 #include "radeon_vce.h"
  45
  46 /* generate an stream handle */
  47 unsigned rvid_alloc_stream_handle()
  48 {
  49         static unsigned counter = 0;
  50         unsigned stream_handle = 0;
  51         unsigned pid = getpid();
  52         int i;
  53
  54         for (i = 0; i < 32; ++i)
  55                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  56
  57         stream_handle ^= ++counter;
  58         return stream_handle;
  59 }
  60
  61 /* create a buffer in the winsys */
  62 bool rvid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
  63                         unsigned size, unsigned usage)
  64 {
  65         memset(buffer, 0, sizeof(*buffer));
  66         buffer->usage = usage;
  67         buffer->res = (struct r600_resource *)
  68                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, usage, size);
  69
  70         return buffer->res != NULL;
  71 }
  72
  73 /* destroy a buffer */
  74 void rvid_destroy_buffer(struct rvid_buffer *buffer)
  75 {
  76         pipe_resource_reference((struct pipe_resource **)&buffer->res, NULL);
  77 }
  78
  79 /* reallocate a buffer, preserving its content */
  80 bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_winsys_cs *cs,
  81                         struct rvid_buffer *new_buf, unsigned new_size)
  82 {
  83         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
  84         struct radeon_winsys* ws = rscreen->ws;
  85         unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
  86         struct rvid_buffer old_buf = *new_buf;
  87         void *src = NULL, *dst = NULL;
  88
  89         if (!rvid_create_buffer(screen, new_buf, new_size, new_buf->usage))
  90                 goto error;
  91
  92         src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
  93         if (!src)
  94                 goto error;
  95
  96         dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
  97         if (!dst)
  98                 goto error;
  99
 100         memcpy(dst, src, bytes);
 101         if (new_size > bytes) {
 102                 new_size -= bytes;
 103                 dst += bytes;
 104                 memset(dst, 0, new_size);
 105         }
 106         ws->buffer_unmap(new_buf->res->buf);
 107         ws->buffer_unmap(old_buf.res->buf);
 108         rvid_destroy_buffer(&old_buf);
 109         return true;
 110
 111 error:
 112         if (src)
 113                 ws->buffer_unmap(old_buf.res->buf);
 114         rvid_destroy_buffer(new_buf);
 115         *new_buf = old_buf;
 116         return false;
 117 }
 118
 119 /* clear the buffer with zeros */
 120 void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 121 {
 122         struct r600_common_context *rctx = (struct r600_common_context*)context;
 123
 124         rctx->clear_buffer(context, &buffer->res->b.b, 0, buffer->res->buf->size,
 125                            0, R600_COHERENCY_NONE);
 126         context->flush(context, NULL, 0);
 127 }
 128
 129 /**
 130  * join surfaces into the same buffer with identical tiling params
 131  * sumup their sizes and replace the backend buffers with a single bo
 132  */
 133 void rvid_join_surfaces(struct radeon_winsys* ws,
 134                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 135                         struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 136 {
 137         unsigned best_tiling, best_wh, off;
 138         unsigned size, alignment;
 139         struct pb_buffer *pb;
 140         unsigned i, j;
 141
 142         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 143                 unsigned wh;
 144
 145                 if (!surfaces[i])
 146                         continue;
 147
 148                 /* choose the smallest bank w/h for now */
 149                 wh = surfaces[i]->bankw * surfaces[i]->bankh;
 150                 if (wh < best_wh) {
 151                         best_wh = wh;
 152                         best_tiling = i;
 153                 }
 154         }
 155
 156         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 157                 if (!surfaces[i])
 158                         continue;
 159
 160                 /* copy the tiling parameters */
 161                 surfaces[i]->bankw = surfaces[best_tiling]->bankw;
 162                 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
 163                 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
 164                 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
 165
 166                 /* adjust the texture layer offsets */
 167                 off = align(off, surfaces[i]->bo_alignment);
 168                 for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
 169                         surfaces[i]->level[j].offset += off;
 170                 off += surfaces[i]->bo_size;
 171         }
 172
 173         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 174                 if (!buffers[i] || !*buffers[i])
 175                         continue;
 176
 177                 size = align(size, (*buffers[i])->alignment);
 178                 size += (*buffers[i])->size;
 179                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 180         }
 181
 182         if (!size)
 183                 return;
 184
 185         /* TODO: 2D tiling workaround */
 186         alignment *= 2;
 187
 188         pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
 189         if (!pb)
 190                 return;
 191
 192         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 193                 if (!buffers[i] || !*buffers[i])
 194                         continue;
 195
 196                 pb_reference(buffers[i], pb);
 197         }
 198
 199         pb_reference(&pb, NULL);
 200 }
 201
 202 int rvid_get_video_param(struct pipe_screen *screen,
 203                          enum pipe_video_profile profile,
 204                          enum pipe_video_entrypoint entrypoint,
 205                          enum pipe_video_cap param)
 206 {
 207         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 208         enum pipe_video_format codec = u_reduce_video_profile(profile);
 209
 210         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 211                 switch (param) {
 212                 case PIPE_VIDEO_CAP_SUPPORTED:
 213                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 214                                 rvce_is_fw_version_supported(rscreen);
 215                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 216                         return 1;
 217                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 218                         return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 219                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 220                         return (rscreen->family < CHIP_TONGA) ? 1152 : 2304;
 221                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 222                         return PIPE_FORMAT_NV12;
 223                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 224                         return false;
 225                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 226                         return false;
 227                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 228                         return true;
 229                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 230                         return (rscreen->family < CHIP_TONGA) ? 1 : 2;
 231                 default:
 232                         return 0;
 233                 }
 234         }
 235
 236         switch (param) {
 237         case PIPE_VIDEO_CAP_SUPPORTED:
 238                 switch (codec) {
 239                 case PIPE_VIDEO_FORMAT_MPEG12:
 240                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 241                 case PIPE_VIDEO_FORMAT_MPEG4:
 242                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 243                         if (rscreen->family < CHIP_PALM)
 244                                 /* no support for MPEG4 */
 245                                 return codec != PIPE_VIDEO_FORMAT_MPEG4;
 246                         return true;
 247                 case PIPE_VIDEO_FORMAT_VC1:
 248                         return true;
 249                 case PIPE_VIDEO_FORMAT_HEVC:
 250                         /* Carrizo only supports HEVC Main */
 251                         if (rscreen->family >= CHIP_STONEY)
 252                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 253                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 254                         else if (rscreen->family >= CHIP_CARRIZO)
 255                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 256                 default:
 257                         return false;
 258                 }
 259         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 260                 return 1;
 261         case PIPE_VIDEO_CAP_MAX_WIDTH:
 262                 return (rscreen->family < CHIP_TONGA) ? 2048 : 4096;
 263         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 264                 return (rscreen->family < CHIP_TONGA) ? 1152 : 4096;
 265         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 266                 return PIPE_FORMAT_NV12;
 267         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 268         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 269                 if (rscreen->family < CHIP_PALM) {
 270                         /* MPEG2 only with shaders and no support for
 271                            interlacing on R6xx style UVD */
 272                         return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
 273                                rscreen->family > CHIP_RV770;
 274                 } else {
 275                         if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
 276                                 return false; //The firmware doesn't support interlaced HEVC.
 277                         return true;
 278                 }
 279         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 280                 return true;
 281         case PIPE_VIDEO_CAP_MAX_LEVEL:
 282                 switch (profile) {
 283                 case PIPE_VIDEO_PROFILE_MPEG1:
 284                         return 0;
 285                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 286                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 287                         return 3;
 288                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 289                         return 3;
 290                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 291                         return 5;
 292                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 293                         return 1;
 294                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 295                         return 2;
 296                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 297                         return 4;
 298                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 299                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 300                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 301                         return (rscreen->family < CHIP_TONGA) ? 41 : 52;
 302                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 303                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 304                         return 186;
 305                 default:
 306                         return 0;
 307                 }
 308         default:
 309                 return 0;
 310         }
 311 }
 312
 313 boolean rvid_is_format_supported(struct pipe_screen *screen,
 314                                  enum pipe_format format,
 315                                  enum pipe_video_profile profile,
 316                                  enum pipe_video_entrypoint entrypoint)
 317 {
 318         /* we can only handle this one with UVD */
 319         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 320                 return format == PIPE_FORMAT_NV12;
 321
 322         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 323 }