src/gallium/drivers/radeon/radeon_video.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2013 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * Authors:
  30  *      Christian König <christian.koenig@amd.com>
  31  *
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include "util/u_memory.h"
  37 #include "util/u_video.h"
  38
  39 #include "vl/vl_defines.h"
  40 #include "vl/vl_video_buffer.h"
  41
  42 #include "../../winsys/radeon/drm/radeon_winsys.h"
  43 #include "r600_pipe_common.h"
  44 #include "radeon_video.h"
  45
  46 /* generate an stream handle */
  47 unsigned rvid_alloc_stream_handle()
  48 {
  49         static unsigned counter = 0;
  50         unsigned stream_handle = 0;
  51         unsigned pid = getpid();
  52         int i;
  53
  54         for (i = 0; i < 32; ++i)
  55                 stream_handle |= ((pid >> i) & 1) << (31 - i);
  56
  57         stream_handle ^= ++counter;
  58         return stream_handle;
  59 }
  60
  61 /* create a buffer in the winsys */
  62 bool rvid_create_buffer(struct radeon_winsys *ws, struct rvid_buffer *buffer,
  63                         unsigned size, enum radeon_bo_domain domain)
  64 {
  65         buffer->domain = domain;
  66
  67         buffer->buf = ws->buffer_create(ws, size, 4096, false, domain);
  68         if (!buffer->buf)
  69                 return false;
  70
  71         buffer->cs_handle = ws->buffer_get_cs_handle(buffer->buf);
  72         if (!buffer->cs_handle)
  73                 return false;
  74
  75         return true;
  76 }
  77
  78 /* destroy a buffer */
  79 void rvid_destroy_buffer(struct rvid_buffer *buffer)
  80 {
  81         pb_reference(&buffer->buf, NULL);
  82         buffer->cs_handle = NULL;
  83 }
  84
  85 /* reallocate a buffer, preserving its content */
  86 bool rvid_resize_buffer(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
  87                         struct rvid_buffer *new_buf, unsigned new_size)
  88 {
  89         unsigned bytes = MIN2(new_buf->buf->size, new_size);
  90         struct rvid_buffer old_buf = *new_buf;
  91         void *src = NULL, *dst = NULL;
  92
  93         if (!rvid_create_buffer(ws, new_buf, new_size, new_buf->domain))
  94                 goto error;
  95
  96         src = ws->buffer_map(old_buf.cs_handle, cs, PIPE_TRANSFER_READ);
  97         if (!src)
  98                 goto error;
  99
 100         dst = ws->buffer_map(new_buf->cs_handle, cs, PIPE_TRANSFER_WRITE);
 101         if (!dst)
 102                 goto error;
 103
 104         memcpy(dst, src, bytes);
 105         if (new_size > bytes) {
 106                 new_size -= bytes;
 107                 dst += bytes;
 108                 memset(dst, 0, new_size);
 109         }
 110         ws->buffer_unmap(new_buf->cs_handle);
 111         ws->buffer_unmap(old_buf.cs_handle);
 112         rvid_destroy_buffer(&old_buf);
 113         return true;
 114
 115 error:
 116         if (src)
 117                 ws->buffer_unmap(old_buf.cs_handle);
 118         rvid_destroy_buffer(new_buf);
 119         *new_buf = old_buf;
 120         return false;
 121 }
 122
 123 /* clear the buffer with zeros */
 124 void rvid_clear_buffer(struct radeon_winsys *ws, struct radeon_winsys_cs *cs, struct rvid_buffer* buffer)
 125 {
 126         void *ptr = ws->buffer_map(buffer->cs_handle, cs, PIPE_TRANSFER_WRITE);
 127         if (!ptr)
 128                 return;
 129
 130         memset(ptr, 0, buffer->buf->size);
 131         ws->buffer_unmap(buffer->cs_handle);
 132 }
 133
 134 /**
 135  * join surfaces into the same buffer with identical tiling params
 136  * sumup their sizes and replace the backend buffers with a single bo
 137  */
 138 void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
 139                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 140                         struct radeon_surface *surfaces[VL_NUM_COMPONENTS])
 141 {
 142         unsigned best_tiling, best_wh, off;
 143         unsigned size, alignment;
 144         struct pb_buffer *pb;
 145         unsigned i, j;
 146
 147         for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 148                 unsigned wh;
 149
 150                 if (!surfaces[i])
 151                         continue;
 152
 153                 /* choose the smallest bank w/h for now */
 154                 wh = surfaces[i]->bankw * surfaces[i]->bankh;
 155                 if (wh < best_wh) {
 156                         best_wh = wh;
 157                         best_tiling = i;
 158                 }
 159         }
 160
 161         for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
 162                 if (!surfaces[i])
 163                         continue;
 164
 165                 /* copy the tiling parameters */
 166                 surfaces[i]->bankw = surfaces[best_tiling]->bankw;
 167                 surfaces[i]->bankh = surfaces[best_tiling]->bankh;
 168                 surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
 169                 surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
 170
 171                 /* adjust the texture layer offsets */
 172                 off = align(off, surfaces[i]->bo_alignment);
 173                 for (j = 0; j < Elements(surfaces[i]->level); ++j)
 174                         surfaces[i]->level[j].offset += off;
 175                 off += surfaces[i]->bo_size;
 176         }
 177
 178         for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
 179                 if (!buffers[i] || !*buffers[i])
 180                         continue;
 181
 182                 size = align(size, (*buffers[i])->alignment);
 183                 size += (*buffers[i])->size;
 184                 alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
 185         }
 186
 187         if (!size)
 188                 return;
 189
 190         /* TODO: 2D tiling workaround */
 191         alignment *= 2;
 192
 193         pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM);
 194         if (!pb)
 195                 return;
 196
 197         for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
 198                 if (!buffers[i] || !*buffers[i])
 199                         continue;
 200
 201                 pb_reference(buffers[i], pb);
 202         }
 203
 204         pb_reference(&pb, NULL);
 205 }
 206
 207 int rvid_get_video_param(struct pipe_screen *screen,
 208                          enum pipe_video_profile profile,
 209                          enum pipe_video_entrypoint entrypoint,
 210                          enum pipe_video_cap param)
 211 {
 212         struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
 213
 214         /* UVD 2.x limits */
 215         if (rscreen->family < CHIP_PALM) {
 216                 enum pipe_video_format codec = u_reduce_video_profile(profile);
 217                 switch (param) {
 218                 case PIPE_VIDEO_CAP_SUPPORTED:
 219                         /* no support for MPEG4 */
 220                         return codec != PIPE_VIDEO_FORMAT_MPEG4;
 221                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 222                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 223                         /* and MPEG2 only with shaders */
 224                         return codec != PIPE_VIDEO_FORMAT_MPEG12;
 225                 default:
 226                         break;
 227                 }
 228         }
 229
 230         switch (param) {
 231         case PIPE_VIDEO_CAP_SUPPORTED:
 232                 switch (u_reduce_video_profile(profile)) {
 233                 case PIPE_VIDEO_FORMAT_MPEG12:
 234                 case PIPE_VIDEO_FORMAT_MPEG4:
 235                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 236                         return entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
 237                 case PIPE_VIDEO_FORMAT_VC1:
 238                         /* FIXME: VC-1 simple/main profile is broken */
 239                         return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED &&
 240                                entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
 241                 default:
 242                         return false;
 243                 }
 244         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 245                 return 1;
 246         case PIPE_VIDEO_CAP_MAX_WIDTH:
 247                 return 2048;
 248         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 249                 return 1152;
 250         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 251                 return PIPE_FORMAT_NV12;
 252         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 253                 return true;
 254         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 255                 return true;
 256         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 257                 return true;
 258         case PIPE_VIDEO_CAP_MAX_LEVEL:
 259                 switch (profile) {
 260                 case PIPE_VIDEO_PROFILE_MPEG1:
 261                         return 0;
 262                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 263                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 264                         return 3;
 265                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 266                         return 3;
 267                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 268                         return 5;
 269                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 270                         return 1;
 271                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 272                         return 2;
 273                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 274                         return 4;
 275                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 276                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 277                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 278                         return 41;
 279                 default:
 280                         return 0;
 281                 }
 282         default:
 283                 return 0;
 284         }
 285 }
 286
 287 boolean rvid_is_format_supported(struct pipe_screen *screen,
 288                                  enum pipe_format format,
 289                                  enum pipe_video_profile profile,
 290                                  enum pipe_video_entrypoint entrypoint)
 291 {
 292         /* we can only handle this one with UVD */
 293         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 294                 return format == PIPE_FORMAT_NV12;
 295
 296         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 297 }