src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright 2018 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  25
  26 #ifndef RADEON_WINSYS_H
  27 #define RADEON_WINSYS_H
  28
  29 /* The public winsys interface header for the radeon driver. */
  30
  31 #include "pipebuffer/pb_buffer.h"
  32
  33 #include "amd/common/ac_gpu_info.h"
  34 #include "amd/common/ac_surface.h"
  35
  36 /* Tiling flags. */
  37 enum radeon_bo_layout {
  38     RADEON_LAYOUT_LINEAR = 0,
  39     RADEON_LAYOUT_TILED,
  40     RADEON_LAYOUT_SQUARETILED,
  41
  42     RADEON_LAYOUT_UNKNOWN
  43 };
  44
  45 enum radeon_bo_domain { /* bitfield */
  46     RADEON_DOMAIN_GTT  = 2,
  47     RADEON_DOMAIN_VRAM = 4,
  48     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52     RADEON_FLAG_GTT_WC =        (1 << 0),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  54     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  55     RADEON_FLAG_SPARSE =        (1 << 3),
  56     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  57     RADEON_FLAG_READ_ONLY =     (1 << 5),
  58     RADEON_FLAG_32BIT =    (1 << 6),
  59 };
  60
  61 enum radeon_bo_usage { /* bitfield */
  62     RADEON_USAGE_READ = 2,
  63     RADEON_USAGE_WRITE = 4,
  64     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  65
  66     /* The winsys ensures that the CS submission will be scheduled after
  67      * previously flushed CSs referencing this BO in a conflicting way.
  68      */
  69     RADEON_USAGE_SYNCHRONIZED = 8
  70 };
  71
  72 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  73
  74 enum ring_type {
  75     RING_GFX = 0,
  76     RING_COMPUTE,
  77     RING_DMA,
  78     RING_UVD,
  79     RING_VCE,
  80     RING_UVD_ENC,
  81     RING_VCN_DEC,
  82     RING_VCN_ENC,
  83     RING_LAST,
  84 };
  85
  86 enum radeon_value_id {
  87     RADEON_REQUESTED_VRAM_MEMORY,
  88     RADEON_REQUESTED_GTT_MEMORY,
  89     RADEON_MAPPED_VRAM,
  90     RADEON_MAPPED_GTT,
  91     RADEON_BUFFER_WAIT_TIME_NS,
  92     RADEON_NUM_MAPPED_BUFFERS,
  93     RADEON_TIMESTAMP,
  94     RADEON_NUM_GFX_IBS,
  95     RADEON_NUM_SDMA_IBS,
  96     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
  97     RADEON_GFX_IB_SIZE_COUNTER,
  98     RADEON_NUM_BYTES_MOVED,
  99     RADEON_NUM_EVICTIONS,
 100     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
 101     RADEON_VRAM_USAGE,
 102     RADEON_VRAM_VIS_USAGE,
 103     RADEON_GTT_USAGE,
 104     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 105     RADEON_CURRENT_SCLK,
 106     RADEON_CURRENT_MCLK,
 107     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 108     RADEON_CS_THREAD_TIME,
 109 };
 110
 111 /* Each group of four has the same priority. */
 112 enum radeon_bo_priority {
 113     RADEON_PRIO_FENCE = 0,
 114     RADEON_PRIO_TRACE,
 115     RADEON_PRIO_SO_FILLED_SIZE,
 116     RADEON_PRIO_QUERY,
 117
 118     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 119     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 120     RADEON_PRIO_DRAW_INDIRECT,
 121     RADEON_PRIO_INDEX_BUFFER,
 122
 123     RADEON_PRIO_VCE = 8,
 124     RADEON_PRIO_UVD,
 125     RADEON_PRIO_SDMA_BUFFER,
 126     RADEON_PRIO_SDMA_TEXTURE,
 127
 128     RADEON_PRIO_CP_DMA = 12,
 129
 130     RADEON_PRIO_CONST_BUFFER = 16,
 131     RADEON_PRIO_DESCRIPTORS,
 132     RADEON_PRIO_BORDER_COLORS,
 133
 134     RADEON_PRIO_SAMPLER_BUFFER = 20,
 135     RADEON_PRIO_VERTEX_BUFFER,
 136
 137     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 138     RADEON_PRIO_COMPUTE_GLOBAL,
 139
 140     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 141     RADEON_PRIO_SHADER_RW_IMAGE,
 142
 143     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 144
 145     RADEON_PRIO_COLOR_BUFFER = 36,
 146
 147     RADEON_PRIO_DEPTH_BUFFER = 40,
 148
 149     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 150
 151     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 152
 153     RADEON_PRIO_CMASK = 52,
 154     RADEON_PRIO_DCC,
 155     RADEON_PRIO_HTILE,
 156     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 157
 158     RADEON_PRIO_SHADER_RINGS = 56,
 159
 160     RADEON_PRIO_SCRATCH_BUFFER = 60,
 161     /* 63 is the maximum value */
 162 };
 163
 164 struct winsys_handle;
 165 struct radeon_winsys_ctx;
 166
 167 struct radeon_winsys_cs_chunk {
 168     unsigned cdw;  /* Number of used dwords. */
 169     unsigned max_dw; /* Maximum number of dwords. */
 170     uint32_t *buf; /* The base pointer of the chunk. */
 171 };
 172
 173 struct radeon_winsys_cs {
 174     struct radeon_winsys_cs_chunk current;
 175     struct radeon_winsys_cs_chunk *prev;
 176     unsigned                      num_prev; /* Number of previous chunks. */
 177     unsigned                      max_prev; /* Space in array pointed to by prev. */
 178     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 179
 180     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 181     uint64_t                      used_vram;
 182     uint64_t                      used_gart;
 183 };
 184
 185 /* Tiling info for display code, DRI sharing, and other data. */
 186 struct radeon_bo_metadata {
 187     /* Tiling flags describing the texture layout for display code
 188      * and DRI sharing.
 189      */
 190     union {
 191         struct {
 192             enum radeon_bo_layout   microtile;
 193             enum radeon_bo_layout   macrotile;
 194             unsigned                pipe_config;
 195             unsigned                bankw;
 196             unsigned                bankh;
 197             unsigned                tile_split;
 198             unsigned                mtilea;
 199             unsigned                num_banks;
 200             unsigned                stride;
 201             bool                    scanout;
 202         } legacy;
 203
 204         struct {
 205             /* surface flags */
 206             unsigned swizzle_mode:5;
 207         } gfx9;
 208     } u;
 209
 210     /* Additional metadata associated with the buffer, in bytes.
 211      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 212      * Supported by amdgpu only.
 213      */
 214     uint32_t                size_metadata;
 215     uint32_t                metadata[64];
 216 };
 217
 218 enum radeon_feature_id {
 219     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 220     RADEON_FID_R300_CMASK_ACCESS,
 221 };
 222
 223 struct radeon_bo_list_item {
 224     uint64_t bo_size;
 225     uint64_t vm_address;
 226     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 227 };
 228
 229 struct radeon_winsys {
 230     /**
 231      * The screen object this winsys was created for
 232      */
 233     struct pipe_screen *screen;
 234
 235     /**
 236      * Decrement the winsys reference count.
 237      *
 238      * \param ws  The winsys this function is called for.
 239      * \return    True if the winsys and screen should be destroyed.
 240      */
 241     bool (*unref)(struct radeon_winsys *ws);
 242
 243     /**
 244      * Destroy this winsys.
 245      *
 246      * \param ws        The winsys this function is called from.
 247      */
 248     void (*destroy)(struct radeon_winsys *ws);
 249
 250     /**
 251      * Query an info structure from winsys.
 252      *
 253      * \param ws        The winsys this function is called from.
 254      * \param info      Return structure
 255      */
 256     void (*query_info)(struct radeon_winsys *ws,
 257                        struct radeon_info *info);
 258
 259     /**************************************************************************
 260      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 261      *
 262      * Remember that gallium gets to choose the interface it needs, and the
 263      * window systems must then implement that interface (rather than the
 264      * other way around...).
 265      *************************************************************************/
 266
 267     /**
 268      * Create a buffer object.
 269      *
 270      * \param ws        The winsys this function is called from.
 271      * \param size      The size to allocate.
 272      * \param alignment An alignment of the buffer in memory.
 273      * \param use_reusable_pool Whether the cache buffer manager should be used.
 274      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 275      * \return          The created buffer object.
 276      */
 277     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 278                                        uint64_t size,
 279                                        unsigned alignment,
 280                                        enum radeon_bo_domain domain,
 281                                        enum radeon_bo_flag flags);
 282
 283     /**
 284      * Map the entire data store of a buffer object into the client's address
 285      * space.
 286      *
 287      * \param buf       A winsys buffer object to map.
 288      * \param cs        A command stream to flush if the buffer is referenced by it.
 289      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 290      * \return          The pointer at the beginning of the buffer.
 291      */
 292     void *(*buffer_map)(struct pb_buffer *buf,
 293                         struct radeon_winsys_cs *cs,
 294                         enum pipe_transfer_usage usage);
 295
 296     /**
 297      * Unmap a buffer object from the client's address space.
 298      *
 299      * \param buf       A winsys buffer object to unmap.
 300      */
 301     void (*buffer_unmap)(struct pb_buffer *buf);
 302
 303     /**
 304      * Wait for the buffer and return true if the buffer is not used
 305      * by the device.
 306      *
 307      * The timeout of 0 will only return the status.
 308      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 309      * is idle.
 310      */
 311     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 312                         enum radeon_bo_usage usage);
 313
 314     /**
 315      * Return buffer metadata.
 316      * (tiling info for display code, DRI sharing, and other data)
 317      *
 318      * \param buf       A winsys buffer object to get the flags from.
 319      * \param md        Metadata
 320      */
 321     void (*buffer_get_metadata)(struct pb_buffer *buf,
 322                                 struct radeon_bo_metadata *md);
 323
 324     /**
 325      * Set buffer metadata.
 326      * (tiling info for display code, DRI sharing, and other data)
 327      *
 328      * \param buf       A winsys buffer object to set the flags for.
 329      * \param md        Metadata
 330      */
 331     void (*buffer_set_metadata)(struct pb_buffer *buf,
 332                                 struct radeon_bo_metadata *md);
 333
 334     /**
 335      * Get a winsys buffer from a winsys handle. The internal structure
 336      * of the handle is platform-specific and only a winsys should access it.
 337      *
 338      * \param ws        The winsys this function is called from.
 339      * \param whandle   A winsys handle pointer as was received from a state
 340      *                  tracker.
 341      * \param stride    The returned buffer stride in bytes.
 342      */
 343     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 344                                             struct winsys_handle *whandle,
 345                                             unsigned *stride, unsigned *offset);
 346
 347     /**
 348      * Get a winsys buffer from a user pointer. The resulting buffer can't
 349      * be exported. Both pointer and size must be page aligned.
 350      *
 351      * \param ws        The winsys this function is called from.
 352      * \param pointer   User pointer to turn into a buffer object.
 353      * \param Size      Size in bytes for the new buffer.
 354      */
 355     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 356                                          void *pointer, uint64_t size);
 357
 358     /**
 359      * Whether the buffer was created from a user pointer.
 360      *
 361      * \param buf       A winsys buffer object
 362      * \return          whether \p buf was created via buffer_from_ptr
 363      */
 364     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 365
 366     /** Whether the buffer was suballocated. */
 367     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 368
 369     /**
 370      * Get a winsys handle from a winsys buffer. The internal structure
 371      * of the handle is platform-specific and only a winsys should access it.
 372      *
 373      * \param buf       A winsys buffer object to get the handle from.
 374      * \param whandle   A winsys handle pointer.
 375      * \param stride    A stride of the buffer in bytes, for texturing.
 376      * \return          true on success.
 377      */
 378     bool (*buffer_get_handle)(struct pb_buffer *buf,
 379                               unsigned stride, unsigned offset,
 380                               unsigned slice_size,
 381                               struct winsys_handle *whandle);
 382
 383     /**
 384      * Change the commitment of a (64KB-page aligned) region of the given
 385      * sparse buffer.
 386      *
 387      * \warning There is no automatic synchronization with command submission.
 388      *
 389      * \note Only implemented by the amdgpu winsys.
 390      *
 391      * \return false on out of memory or other failure, true on success.
 392      */
 393     bool (*buffer_commit)(struct pb_buffer *buf,
 394                           uint64_t offset, uint64_t size,
 395                           bool commit);
 396
 397     /**
 398      * Return the virtual address of a buffer.
 399      *
 400      * When virtual memory is not in use, this is the offset relative to the
 401      * relocation base (non-zero for sub-allocated buffers).
 402      *
 403      * \param buf       A winsys buffer object
 404      * \return          virtual address
 405      */
 406     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 407
 408     /**
 409      * Return the offset of this buffer relative to the relocation base.
 410      * This is only non-zero for sub-allocated buffers.
 411      *
 412      * This is only supported in the radeon winsys, since amdgpu uses virtual
 413      * addresses in submissions even for the video engines.
 414      *
 415      * \param buf      A winsys buffer object
 416      * \return         the offset for relocations
 417      */
 418     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 419
 420     /**
 421      * Query the initial placement of the buffer from the kernel driver.
 422      */
 423     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 424
 425     /**************************************************************************
 426      * Command submission.
 427      *
 428      * Each pipe context should create its own command stream and submit
 429      * commands independently of other contexts.
 430      *************************************************************************/
 431
 432     /**
 433      * Create a command submission context.
 434      * Various command streams can be submitted to the same context.
 435      */
 436     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 437
 438     /**
 439      * Destroy a context.
 440      */
 441     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 442
 443     /**
 444      * Query a GPU reset status.
 445      */
 446     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 447
 448     /**
 449      * Create a command stream.
 450      *
 451      * \param ctx       The submission context
 452      * \param ring_type The ring type (GFX, DMA, UVD)
 453      * \param flush     Flush callback function associated with the command stream.
 454      * \param user      User pointer that will be passed to the flush callback.
 455      */
 456     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 457                                           enum ring_type ring_type,
 458                                           void (*flush)(void *ctx, unsigned flags,
 459                                                         struct pipe_fence_handle **fence),
 460                                           void *flush_ctx);
 461
 462     /**
 463      * Destroy a command stream.
 464      *
 465      * \param cs        A command stream to destroy.
 466      */
 467     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 468
 469     /**
 470      * Add a buffer. Each buffer used by a CS must be added using this function.
 471      *
 472      * \param cs      Command stream
 473      * \param buf     Buffer
 474      * \param usage   Whether the buffer is used for read and/or write.
 475      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 476      * \param priority  A higher number means a greater chance of being
 477      *                  placed in the requested domain. 15 is the maximum.
 478      * \return Buffer index.
 479      */
 480     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 481                              struct pb_buffer *buf,
 482                              enum radeon_bo_usage usage,
 483                              enum radeon_bo_domain domain,
 484                              enum radeon_bo_priority priority);
 485
 486     /**
 487      * Return the index of an already-added buffer.
 488      *
 489      * Not supported on amdgpu. Drivers with GPUVM should not care about
 490      * buffer indices.
 491      *
 492      * \param cs        Command stream
 493      * \param buf       Buffer
 494      * \return          The buffer index, or -1 if the buffer has not been added.
 495      */
 496     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 497                             struct pb_buffer *buf);
 498
 499     /**
 500      * Return true if there is enough memory in VRAM and GTT for the buffers
 501      * added so far. If the validation fails, all buffers which have
 502      * been added since the last call of cs_validate will be removed and
 503      * the CS will be flushed (provided there are still any buffers).
 504      *
 505      * \param cs        A command stream to validate.
 506      */
 507     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 508
 509     /**
 510      * Check whether the given number of dwords is available in the IB.
 511      * Optionally chain a new chunk of the IB if necessary and supported.
 512      *
 513      * \param cs        A command stream.
 514      * \param dw        Number of CS dwords requested by the caller.
 515      */
 516     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 517
 518     /**
 519      * Return the buffer list.
 520      *
 521      * This is the buffer list as passed to the kernel, i.e. it only contains
 522      * the parent buffers of sub-allocated buffers.
 523      *
 524      * \param cs    Command stream
 525      * \param list  Returned buffer list. Set to NULL to query the count only.
 526      * \return      The buffer count.
 527      */
 528     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 529                                    struct radeon_bo_list_item *list);
 530
 531     /**
 532      * Flush a command stream.
 533      *
 534      * \param cs          A command stream to flush.
 535      * \param flags,      PIPE_FLUSH_* flags.
 536      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 537      *                    after the CS and is returned through this parameter.
 538      * \return Negative POSIX error code or 0 for success.
 539      *         Asynchronous submissions never return an error.
 540      */
 541     int (*cs_flush)(struct radeon_winsys_cs *cs,
 542                     unsigned flags,
 543                     struct pipe_fence_handle **fence);
 544
 545     /**
 546      * Create a fence before the CS is flushed.
 547      * The user must flush manually to complete the initializaton of the fence.
 548      *
 549      * The fence must not be used for anything except \ref cs_add_fence_dependency
 550      * before the flush.
 551      */
 552     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 553
 554     /**
 555      * Return true if a buffer is referenced by a command stream.
 556      *
 557      * \param cs        A command stream.
 558      * \param buf       A winsys buffer.
 559      */
 560     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 561                                     struct pb_buffer *buf,
 562                                     enum radeon_bo_usage usage);
 563
 564     /**
 565      * Request access to a feature for a command stream.
 566      *
 567      * \param cs        A command stream.
 568      * \param fid       Feature ID, one of RADEON_FID_*
 569      * \param enable    Whether to enable or disable the feature.
 570      */
 571     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 572                                enum radeon_feature_id fid,
 573                                bool enable);
 574      /**
 575       * Make sure all asynchronous flush of the cs have completed
 576       *
 577       * \param cs        A command stream.
 578       */
 579     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 580
 581     /**
 582      * Add a fence dependency to the CS, so that the CS will wait for
 583      * the fence before execution.
 584      */
 585     void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs,
 586                                     struct pipe_fence_handle *fence);
 587
 588     /**
 589      * Signal a syncobj when the CS finishes execution.
 590      */
 591     void (*cs_add_syncobj_signal)(struct radeon_winsys_cs *cs,
 592                                   struct pipe_fence_handle *fence);
 593
 594     /**
 595      * Wait for the fence and return true if the fence has been signalled.
 596      * The timeout of 0 will only return the status.
 597      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 598      * is signalled.
 599      */
 600     bool (*fence_wait)(struct radeon_winsys *ws,
 601                        struct pipe_fence_handle *fence,
 602                        uint64_t timeout);
 603
 604     /**
 605      * Reference counting for fences.
 606      */
 607     void (*fence_reference)(struct pipe_fence_handle **dst,
 608                             struct pipe_fence_handle *src);
 609
 610     /**
 611      * Create a new fence object corresponding to the given syncobj fd.
 612      */
 613     struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
 614                                                       int fd);
 615
 616     /**
 617      * Create a new fence object corresponding to the given sync_file.
 618      */
 619     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 620                                                         int fd);
 621
 622     /**
 623      * Return a sync_file FD corresponding to the given fence object.
 624      */
 625     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 626                                   struct pipe_fence_handle *fence);
 627
 628     /**
 629      * Return a sync file FD that is already signalled.
 630      */
 631     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 632
 633     /**
 634      * Initialize surface
 635      *
 636      * \param ws        The winsys this function is called from.
 637      * \param tex       Input texture description
 638      * \param flags     Bitmask of RADEON_SURF_* flags
 639      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 640      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 641      * \param surf      Output structure
 642      */
 643     int (*surface_init)(struct radeon_winsys *ws,
 644                         const struct pipe_resource *tex,
 645                         unsigned flags, unsigned bpe,
 646                         enum radeon_surf_mode mode,
 647                         struct radeon_surf *surf);
 648
 649     uint64_t (*query_value)(struct radeon_winsys *ws,
 650                             enum radeon_value_id value);
 651
 652     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 653                            unsigned num_registers, uint32_t *out);
 654
 655     const char* (*get_chip_name)(struct radeon_winsys *ws);
 656 };
 657
 658 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 659 {
 660     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 661 }
 662
 663 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 664 {
 665     cs->current.buf[cs->current.cdw++] = value;
 666 }
 667
 668 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 669                                      const uint32_t *values, unsigned count)
 670 {
 671     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 672     cs->current.cdw += count;
 673 }
 674
 675 enum radeon_heap {
 676     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 677     RADEON_HEAP_VRAM_READ_ONLY,
 678     RADEON_HEAP_VRAM_READ_ONLY_32BIT,
 679     RADEON_HEAP_VRAM_32BIT,
 680     RADEON_HEAP_VRAM,
 681     RADEON_HEAP_GTT_WC,
 682     RADEON_HEAP_GTT_WC_READ_ONLY,
 683     RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
 684     RADEON_HEAP_GTT_WC_32BIT,
 685     RADEON_HEAP_GTT,
 686     RADEON_MAX_SLAB_HEAPS,
 687     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 688 };
 689
 690 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 691 {
 692     switch (heap) {
 693     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 694     case RADEON_HEAP_VRAM_READ_ONLY:
 695     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 696     case RADEON_HEAP_VRAM_32BIT:
 697     case RADEON_HEAP_VRAM:
 698         return RADEON_DOMAIN_VRAM;
 699     case RADEON_HEAP_GTT_WC:
 700     case RADEON_HEAP_GTT_WC_READ_ONLY:
 701     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 702     case RADEON_HEAP_GTT_WC_32BIT:
 703     case RADEON_HEAP_GTT:
 704         return RADEON_DOMAIN_GTT;
 705     default:
 706         assert(0);
 707         return (enum radeon_bo_domain)0;
 708     }
 709 }
 710
 711 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 712 {
 713     unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
 714                      (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
 715
 716     switch (heap) {
 717     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 718         return flags |
 719                RADEON_FLAG_NO_CPU_ACCESS;
 720
 721     case RADEON_HEAP_VRAM_READ_ONLY:
 722     case RADEON_HEAP_GTT_WC_READ_ONLY:
 723         return flags |
 724                RADEON_FLAG_READ_ONLY;
 725
 726     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 727     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 728         return flags |
 729                RADEON_FLAG_READ_ONLY |
 730                RADEON_FLAG_32BIT;
 731
 732     case RADEON_HEAP_VRAM_32BIT:
 733     case RADEON_HEAP_GTT_WC_32BIT:
 734         return flags |
 735                RADEON_FLAG_32BIT;
 736
 737     case RADEON_HEAP_VRAM:
 738     case RADEON_HEAP_GTT_WC:
 739     case RADEON_HEAP_GTT:
 740     default:
 741         return flags;
 742     }
 743 }
 744
 745 /* Return the heap index for winsys allocators, or -1 on failure. */
 746 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 747                                         enum radeon_bo_flag flags)
 748 {
 749     /* VRAM implies WC (write combining) */
 750     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 751     /* NO_CPU_ACCESS implies VRAM only. */
 752     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 753
 754     /* Resources with interprocess sharing don't use any winsys allocators. */
 755     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 756         return -1;
 757
 758     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 759     if (flags & ~(RADEON_FLAG_GTT_WC |
 760                   RADEON_FLAG_NO_CPU_ACCESS |
 761                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 762                   RADEON_FLAG_READ_ONLY |
 763                   RADEON_FLAG_32BIT))
 764         return -1;
 765
 766     switch (domain) {
 767     case RADEON_DOMAIN_VRAM:
 768         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
 769                          RADEON_FLAG_READ_ONLY |
 770                          RADEON_FLAG_32BIT)) {
 771         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 772         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 773             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 774             return -1;
 775         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
 776             assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
 777             return -1;
 778         case RADEON_FLAG_NO_CPU_ACCESS:
 779             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 780         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 781             return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
 782         case RADEON_FLAG_READ_ONLY:
 783             return RADEON_HEAP_VRAM_READ_ONLY;
 784         case RADEON_FLAG_32BIT:
 785             return RADEON_HEAP_VRAM_32BIT;
 786         case 0:
 787             return RADEON_HEAP_VRAM;
 788         }
 789         break;
 790     case RADEON_DOMAIN_GTT:
 791         switch (flags & (RADEON_FLAG_GTT_WC |
 792                          RADEON_FLAG_READ_ONLY |
 793                          RADEON_FLAG_32BIT)) {
 794         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 795             return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
 796         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 797             return RADEON_HEAP_GTT_WC_READ_ONLY;
 798         case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
 799             return RADEON_HEAP_GTT_WC_32BIT;
 800         case RADEON_FLAG_GTT_WC:
 801             return RADEON_HEAP_GTT_WC;
 802         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 803         case RADEON_FLAG_READ_ONLY:
 804             assert(!"READ_ONLY without WC is disallowed");
 805             return -1;
 806         case RADEON_FLAG_32BIT:
 807             assert(!"32BIT without WC is disallowed");
 808             return -1;
 809         case 0:
 810             return RADEON_HEAP_GTT;
 811         }
 812         break;
 813     default:
 814         break;
 815     }
 816     return -1;
 817 }
 818
 819 #endif