src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/ac_gpu_info.h"
  32 #include "amd/common/ac_surface.h"
  33
  34 #define RADEON_FLUSH_ASYNC              (1 << 0)
  35 #define RADEON_FLUSH_END_OF_FRAME       (1 << 1)
  36
  37 /* Tiling flags. */
  38 enum radeon_bo_layout {
  39     RADEON_LAYOUT_LINEAR = 0,
  40     RADEON_LAYOUT_TILED,
  41     RADEON_LAYOUT_SQUARETILED,
  42
  43     RADEON_LAYOUT_UNKNOWN
  44 };
  45
  46 enum radeon_bo_domain { /* bitfield */
  47     RADEON_DOMAIN_GTT  = 2,
  48     RADEON_DOMAIN_VRAM = 4,
  49     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  50 };
  51
  52 enum radeon_bo_flag { /* bitfield */
  53     RADEON_FLAG_GTT_WC =        (1 << 0),
  54     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  55     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  56     RADEON_FLAG_HANDLE =        (1 << 3), /* the buffer must not be suballocated */
  57     RADEON_FLAG_SPARSE =        (1 << 4),
  58 };
  59
  60 enum radeon_bo_usage { /* bitfield */
  61     RADEON_USAGE_READ = 2,
  62     RADEON_USAGE_WRITE = 4,
  63     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  64
  65     /* The winsys ensures that the CS submission will be scheduled after
  66      * previously flushed CSs referencing this BO in a conflicting way.
  67      */
  68     RADEON_USAGE_SYNCHRONIZED = 8
  69 };
  70
  71 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  72
  73 enum ring_type {
  74     RING_GFX = 0,
  75     RING_COMPUTE,
  76     RING_DMA,
  77     RING_UVD,
  78     RING_VCE,
  79     RING_UVD_ENC,
  80     RING_VCN_DEC,
  81     RING_LAST,
  82 };
  83
  84 enum radeon_value_id {
  85     RADEON_REQUESTED_VRAM_MEMORY,
  86     RADEON_REQUESTED_GTT_MEMORY,
  87     RADEON_MAPPED_VRAM,
  88     RADEON_MAPPED_GTT,
  89     RADEON_BUFFER_WAIT_TIME_NS,
  90     RADEON_NUM_MAPPED_BUFFERS,
  91     RADEON_TIMESTAMP,
  92     RADEON_NUM_GFX_IBS,
  93     RADEON_NUM_SDMA_IBS,
  94     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
  95     RADEON_NUM_BYTES_MOVED,
  96     RADEON_NUM_EVICTIONS,
  97     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  98     RADEON_VRAM_USAGE,
  99     RADEON_VRAM_VIS_USAGE,
 100     RADEON_GTT_USAGE,
 101     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 102     RADEON_CURRENT_SCLK,
 103     RADEON_CURRENT_MCLK,
 104     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 105     RADEON_CS_THREAD_TIME,
 106 };
 107
 108 /* Each group of four has the same priority. */
 109 enum radeon_bo_priority {
 110     RADEON_PRIO_FENCE = 0,
 111     RADEON_PRIO_TRACE,
 112     RADEON_PRIO_SO_FILLED_SIZE,
 113     RADEON_PRIO_QUERY,
 114
 115     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 116     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 117     RADEON_PRIO_DRAW_INDIRECT,
 118     RADEON_PRIO_INDEX_BUFFER,
 119
 120     RADEON_PRIO_VCE = 8,
 121     RADEON_PRIO_UVD,
 122     RADEON_PRIO_SDMA_BUFFER,
 123     RADEON_PRIO_SDMA_TEXTURE,
 124
 125     RADEON_PRIO_CP_DMA = 12,
 126
 127     RADEON_PRIO_CONST_BUFFER = 16,
 128     RADEON_PRIO_DESCRIPTORS,
 129     RADEON_PRIO_BORDER_COLORS,
 130
 131     RADEON_PRIO_SAMPLER_BUFFER = 20,
 132     RADEON_PRIO_VERTEX_BUFFER,
 133
 134     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 135     RADEON_PRIO_COMPUTE_GLOBAL,
 136
 137     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 138     RADEON_PRIO_SHADER_RW_IMAGE,
 139
 140     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 141
 142     RADEON_PRIO_COLOR_BUFFER = 36,
 143
 144     RADEON_PRIO_DEPTH_BUFFER = 40,
 145
 146     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 147
 148     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 149
 150     RADEON_PRIO_CMASK = 52,
 151     RADEON_PRIO_DCC,
 152     RADEON_PRIO_HTILE,
 153     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 154
 155     RADEON_PRIO_SHADER_RINGS = 56,
 156
 157     RADEON_PRIO_SCRATCH_BUFFER = 60,
 158     /* 63 is the maximum value */
 159 };
 160
 161 struct winsys_handle;
 162 struct radeon_winsys_ctx;
 163
 164 struct radeon_winsys_cs_chunk {
 165     unsigned cdw;  /* Number of used dwords. */
 166     unsigned max_dw; /* Maximum number of dwords. */
 167     uint32_t *buf; /* The base pointer of the chunk. */
 168 };
 169
 170 struct radeon_winsys_cs {
 171     struct radeon_winsys_cs_chunk current;
 172     struct radeon_winsys_cs_chunk *prev;
 173     unsigned                      num_prev; /* Number of previous chunks. */
 174     unsigned                      max_prev; /* Space in array pointed to by prev. */
 175     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 176
 177     /* Memory usage of the buffer list. These are always 0 for CE and preamble
 178      * IBs. */
 179     uint64_t                      used_vram;
 180     uint64_t                      used_gart;
 181 };
 182
 183 /* Tiling info for display code, DRI sharing, and other data. */
 184 struct radeon_bo_metadata {
 185     /* Tiling flags describing the texture layout for display code
 186      * and DRI sharing.
 187      */
 188     union {
 189         struct {
 190             enum radeon_bo_layout   microtile;
 191             enum radeon_bo_layout   macrotile;
 192             unsigned                pipe_config;
 193             unsigned                bankw;
 194             unsigned                bankh;
 195             unsigned                tile_split;
 196             unsigned                mtilea;
 197             unsigned                num_banks;
 198             unsigned                stride;
 199             bool                    scanout;
 200         } legacy;
 201
 202         struct {
 203             /* surface flags */
 204             unsigned swizzle_mode:5;
 205         } gfx9;
 206     } u;
 207
 208     /* Additional metadata associated with the buffer, in bytes.
 209      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 210      * Supported by amdgpu only.
 211      */
 212     uint32_t                size_metadata;
 213     uint32_t                metadata[64];
 214 };
 215
 216 enum radeon_feature_id {
 217     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 218     RADEON_FID_R300_CMASK_ACCESS,
 219 };
 220
 221 struct radeon_bo_list_item {
 222     uint64_t bo_size;
 223     uint64_t vm_address;
 224     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 225 };
 226
 227 struct radeon_winsys {
 228     /**
 229      * The screen object this winsys was created for
 230      */
 231     struct pipe_screen *screen;
 232
 233     /**
 234      * Decrement the winsys reference count.
 235      *
 236      * \param ws  The winsys this function is called for.
 237      * \return    True if the winsys and screen should be destroyed.
 238      */
 239     bool (*unref)(struct radeon_winsys *ws);
 240
 241     /**
 242      * Destroy this winsys.
 243      *
 244      * \param ws        The winsys this function is called from.
 245      */
 246     void (*destroy)(struct radeon_winsys *ws);
 247
 248     /**
 249      * Query an info structure from winsys.
 250      *
 251      * \param ws        The winsys this function is called from.
 252      * \param info      Return structure
 253      */
 254     void (*query_info)(struct radeon_winsys *ws,
 255                        struct radeon_info *info);
 256
 257     /**************************************************************************
 258      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 259      *
 260      * Remember that gallium gets to choose the interface it needs, and the
 261      * window systems must then implement that interface (rather than the
 262      * other way around...).
 263      *************************************************************************/
 264
 265     /**
 266      * Create a buffer object.
 267      *
 268      * \param ws        The winsys this function is called from.
 269      * \param size      The size to allocate.
 270      * \param alignment An alignment of the buffer in memory.
 271      * \param use_reusable_pool Whether the cache buffer manager should be used.
 272      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 273      * \return          The created buffer object.
 274      */
 275     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 276                                        uint64_t size,
 277                                        unsigned alignment,
 278                                        enum radeon_bo_domain domain,
 279                                        enum radeon_bo_flag flags);
 280
 281     /**
 282      * Map the entire data store of a buffer object into the client's address
 283      * space.
 284      *
 285      * \param buf       A winsys buffer object to map.
 286      * \param cs        A command stream to flush if the buffer is referenced by it.
 287      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 288      * \return          The pointer at the beginning of the buffer.
 289      */
 290     void *(*buffer_map)(struct pb_buffer *buf,
 291                         struct radeon_winsys_cs *cs,
 292                         enum pipe_transfer_usage usage);
 293
 294     /**
 295      * Unmap a buffer object from the client's address space.
 296      *
 297      * \param buf       A winsys buffer object to unmap.
 298      */
 299     void (*buffer_unmap)(struct pb_buffer *buf);
 300
 301     /**
 302      * Wait for the buffer and return true if the buffer is not used
 303      * by the device.
 304      *
 305      * The timeout of 0 will only return the status.
 306      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 307      * is idle.
 308      */
 309     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 310                         enum radeon_bo_usage usage);
 311
 312     /**
 313      * Return buffer metadata.
 314      * (tiling info for display code, DRI sharing, and other data)
 315      *
 316      * \param buf       A winsys buffer object to get the flags from.
 317      * \param md        Metadata
 318      */
 319     void (*buffer_get_metadata)(struct pb_buffer *buf,
 320                                 struct radeon_bo_metadata *md);
 321
 322     /**
 323      * Set buffer metadata.
 324      * (tiling info for display code, DRI sharing, and other data)
 325      *
 326      * \param buf       A winsys buffer object to set the flags for.
 327      * \param md        Metadata
 328      */
 329     void (*buffer_set_metadata)(struct pb_buffer *buf,
 330                                 struct radeon_bo_metadata *md);
 331
 332     /**
 333      * Get a winsys buffer from a winsys handle. The internal structure
 334      * of the handle is platform-specific and only a winsys should access it.
 335      *
 336      * \param ws        The winsys this function is called from.
 337      * \param whandle   A winsys handle pointer as was received from a state
 338      *                  tracker.
 339      * \param stride    The returned buffer stride in bytes.
 340      */
 341     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 342                                             struct winsys_handle *whandle,
 343                                             unsigned *stride, unsigned *offset);
 344
 345     /**
 346      * Get a winsys buffer from a user pointer. The resulting buffer can't
 347      * be exported. Both pointer and size must be page aligned.
 348      *
 349      * \param ws        The winsys this function is called from.
 350      * \param pointer   User pointer to turn into a buffer object.
 351      * \param Size      Size in bytes for the new buffer.
 352      */
 353     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 354                                          void *pointer, uint64_t size);
 355
 356     /**
 357      * Whether the buffer was created from a user pointer.
 358      *
 359      * \param buf       A winsys buffer object
 360      * \return          whether \p buf was created via buffer_from_ptr
 361      */
 362     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 363
 364     /**
 365      * Get a winsys handle from a winsys buffer. The internal structure
 366      * of the handle is platform-specific and only a winsys should access it.
 367      *
 368      * \param buf       A winsys buffer object to get the handle from.
 369      * \param whandle   A winsys handle pointer.
 370      * \param stride    A stride of the buffer in bytes, for texturing.
 371      * \return          true on success.
 372      */
 373     bool (*buffer_get_handle)(struct pb_buffer *buf,
 374                               unsigned stride, unsigned offset,
 375                               unsigned slice_size,
 376                               struct winsys_handle *whandle);
 377
 378     /**
 379      * Change the commitment of a (64KB-page aligned) region of the given
 380      * sparse buffer.
 381      *
 382      * \warning There is no automatic synchronization with command submission.
 383      *
 384      * \note Only implemented by the amdgpu winsys.
 385      *
 386      * \return false on out of memory or other failure, true on success.
 387      */
 388     bool (*buffer_commit)(struct pb_buffer *buf,
 389                           uint64_t offset, uint64_t size,
 390                           bool commit);
 391
 392     /**
 393      * Return the virtual address of a buffer.
 394      *
 395      * When virtual memory is not in use, this is the offset relative to the
 396      * relocation base (non-zero for sub-allocated buffers).
 397      *
 398      * \param buf       A winsys buffer object
 399      * \return          virtual address
 400      */
 401     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 402
 403     /**
 404      * Return the offset of this buffer relative to the relocation base.
 405      * This is only non-zero for sub-allocated buffers.
 406      *
 407      * This is only supported in the radeon winsys, since amdgpu uses virtual
 408      * addresses in submissions even for the video engines.
 409      *
 410      * \param buf      A winsys buffer object
 411      * \return         the offset for relocations
 412      */
 413     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 414
 415     /**
 416      * Query the initial placement of the buffer from the kernel driver.
 417      */
 418     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 419
 420     /**************************************************************************
 421      * Command submission.
 422      *
 423      * Each pipe context should create its own command stream and submit
 424      * commands independently of other contexts.
 425      *************************************************************************/
 426
 427     /**
 428      * Create a command submission context.
 429      * Various command streams can be submitted to the same context.
 430      */
 431     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 432
 433     /**
 434      * Destroy a context.
 435      */
 436     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 437
 438     /**
 439      * Query a GPU reset status.
 440      */
 441     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 442
 443     /**
 444      * Create a command stream.
 445      *
 446      * \param ctx       The submission context
 447      * \param ring_type The ring type (GFX, DMA, UVD)
 448      * \param flush     Flush callback function associated with the command stream.
 449      * \param user      User pointer that will be passed to the flush callback.
 450      */
 451     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 452                                           enum ring_type ring_type,
 453                                           void (*flush)(void *ctx, unsigned flags,
 454                                                         struct pipe_fence_handle **fence),
 455                                           void *flush_ctx);
 456
 457     /**
 458      * Add a constant engine IB to a graphics CS. This makes the graphics CS
 459      * from "cs_create" a group of two IBs that share a buffer list and are
 460      * flushed together.
 461      *
 462      * The returned constant CS is only a stream for writing packets to the new
 463      * IB. Calling other winsys functions with it is not allowed, not even
 464      * "cs_destroy".
 465      *
 466      * In order to add buffers and check memory usage, use the graphics CS.
 467      * In order to flush it, use the graphics CS, which will flush both IBs.
 468      * Destroying the graphics CS will destroy both of them.
 469      *
 470      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 471      *            list and will be used for flushing.
 472      */
 473     struct radeon_winsys_cs *(*cs_add_const_ib)(struct radeon_winsys_cs *cs);
 474
 475      /**
 476      * Add a constant engine preamble IB to a graphics CS. This add an extra IB
 477      * in similar manner to cs_add_const_ib. This should always be called after
 478      * cs_add_const_ib.
 479      *
 480      * The returned IB is a constant engine IB that only gets flushed if the
 481      * context changed.
 482      *
 483      * \param cs  The graphics CS from "cs_create" that will hold the buffer
 484      *            list and will be used for flushing.
 485      */
 486     struct radeon_winsys_cs *(*cs_add_const_preamble_ib)(struct radeon_winsys_cs *cs);
 487     /**
 488      * Destroy a command stream.
 489      *
 490      * \param cs        A command stream to destroy.
 491      */
 492     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 493
 494     /**
 495      * Add a buffer. Each buffer used by a CS must be added using this function.
 496      *
 497      * \param cs      Command stream
 498      * \param buf     Buffer
 499      * \param usage   Whether the buffer is used for read and/or write.
 500      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 501      * \param priority  A higher number means a greater chance of being
 502      *                  placed in the requested domain. 15 is the maximum.
 503      * \return Buffer index.
 504      */
 505     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 506                              struct pb_buffer *buf,
 507                              enum radeon_bo_usage usage,
 508                              enum radeon_bo_domain domain,
 509                              enum radeon_bo_priority priority);
 510
 511     /**
 512      * Return the index of an already-added buffer.
 513      *
 514      * Not supported on amdgpu. Drivers with GPUVM should not care about
 515      * buffer indices.
 516      *
 517      * \param cs        Command stream
 518      * \param buf       Buffer
 519      * \return          The buffer index, or -1 if the buffer has not been added.
 520      */
 521     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 522                             struct pb_buffer *buf);
 523
 524     /**
 525      * Return true if there is enough memory in VRAM and GTT for the buffers
 526      * added so far. If the validation fails, all buffers which have
 527      * been added since the last call of cs_validate will be removed and
 528      * the CS will be flushed (provided there are still any buffers).
 529      *
 530      * \param cs        A command stream to validate.
 531      */
 532     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 533
 534     /**
 535      * Check whether the given number of dwords is available in the IB.
 536      * Optionally chain a new chunk of the IB if necessary and supported.
 537      *
 538      * \param cs        A command stream.
 539      * \param dw        Number of CS dwords requested by the caller.
 540      */
 541     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 542
 543     /**
 544      * Return the buffer list.
 545      *
 546      * This is the buffer list as passed to the kernel, i.e. it only contains
 547      * the parent buffers of sub-allocated buffers.
 548      *
 549      * \param cs    Command stream
 550      * \param list  Returned buffer list. Set to NULL to query the count only.
 551      * \return      The buffer count.
 552      */
 553     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 554                                    struct radeon_bo_list_item *list);
 555
 556     /**
 557      * Flush a command stream.
 558      *
 559      * \param cs          A command stream to flush.
 560      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 561      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 562      *                    after the CS and is returned through this parameter.
 563      * \return Negative POSIX error code or 0 for success.
 564      *         Asynchronous submissions never return an error.
 565      */
 566     int (*cs_flush)(struct radeon_winsys_cs *cs,
 567                     unsigned flags,
 568                     struct pipe_fence_handle **fence);
 569
 570     /**
 571      * Create a fence before the CS is flushed.
 572      * The user must flush manually to complete the initializaton of the fence.
 573      * The fence must not be used before the flush.
 574      */
 575     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 576
 577     /**
 578      * Return true if a buffer is referenced by a command stream.
 579      *
 580      * \param cs        A command stream.
 581      * \param buf       A winsys buffer.
 582      */
 583     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 584                                     struct pb_buffer *buf,
 585                                     enum radeon_bo_usage usage);
 586
 587     /**
 588      * Request access to a feature for a command stream.
 589      *
 590      * \param cs        A command stream.
 591      * \param fid       Feature ID, one of RADEON_FID_*
 592      * \param enable    Whether to enable or disable the feature.
 593      */
 594     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 595                                enum radeon_feature_id fid,
 596                                bool enable);
 597      /**
 598       * Make sure all asynchronous flush of the cs have completed
 599       *
 600       * \param cs        A command stream.
 601       */
 602     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 603
 604     /**
 605      * Wait for the fence and return true if the fence has been signalled.
 606      * The timeout of 0 will only return the status.
 607      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 608      * is signalled.
 609      */
 610     bool (*fence_wait)(struct radeon_winsys *ws,
 611                        struct pipe_fence_handle *fence,
 612                        uint64_t timeout);
 613
 614     /**
 615      * Reference counting for fences.
 616      */
 617     void (*fence_reference)(struct pipe_fence_handle **dst,
 618                             struct pipe_fence_handle *src);
 619
 620     /**
 621      * Initialize surface
 622      *
 623      * \param ws        The winsys this function is called from.
 624      * \param tex       Input texture description
 625      * \param flags     Bitmask of RADEON_SURF_* flags
 626      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 627      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 628      * \param surf      Output structure
 629      */
 630     int (*surface_init)(struct radeon_winsys *ws,
 631                         const struct pipe_resource *tex,
 632                         unsigned flags, unsigned bpe,
 633                         enum radeon_surf_mode mode,
 634                         struct radeon_surf *surf);
 635
 636     uint64_t (*query_value)(struct radeon_winsys *ws,
 637                             enum radeon_value_id value);
 638
 639     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 640                            unsigned num_registers, uint32_t *out);
 641
 642     const char* (*get_chip_name)(struct radeon_winsys *ws);
 643 };
 644
 645 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 646 {
 647     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 648 }
 649
 650 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 651 {
 652     cs->current.buf[cs->current.cdw++] = value;
 653 }
 654
 655 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 656                                      const uint32_t *values, unsigned count)
 657 {
 658     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 659     cs->current.cdw += count;
 660 }
 661
 662 #endif