src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #define RADEON_FLUSH_ASYNC              (1 << 0)
  46 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  47 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  48
  49 /* Tiling flags. */
  50 enum radeon_bo_layout {
  51     RADEON_LAYOUT_LINEAR = 0,
  52     RADEON_LAYOUT_TILED,
  53     RADEON_LAYOUT_SQUARETILED,
  54
  55     RADEON_LAYOUT_UNKNOWN
  56 };
  57
  58 enum radeon_bo_domain { /* bitfield */
  59     RADEON_DOMAIN_GTT  = 2,
  60     RADEON_DOMAIN_VRAM = 4,
  61     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  62 };
  63
  64 enum radeon_bo_flag { /* bitfield */
  65     RADEON_FLAG_GTT_WC =        (1 << 0),
  66     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  67     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  68 };
  69
  70 enum radeon_bo_usage { /* bitfield */
  71     RADEON_USAGE_READ = 2,
  72     RADEON_USAGE_WRITE = 4,
  73     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  74 };
  75
  76 enum radeon_family {
  77     CHIP_UNKNOWN = 0,
  78     CHIP_R300, /* R3xx-based cores. */
  79     CHIP_R350,
  80     CHIP_RV350,
  81     CHIP_RV370,
  82     CHIP_RV380,
  83     CHIP_RS400,
  84     CHIP_RC410,
  85     CHIP_RS480,
  86     CHIP_R420,     /* R4xx-based cores. */
  87     CHIP_R423,
  88     CHIP_R430,
  89     CHIP_R480,
  90     CHIP_R481,
  91     CHIP_RV410,
  92     CHIP_RS600,
  93     CHIP_RS690,
  94     CHIP_RS740,
  95     CHIP_RV515,    /* R5xx-based cores. */
  96     CHIP_R520,
  97     CHIP_RV530,
  98     CHIP_R580,
  99     CHIP_RV560,
 100     CHIP_RV570,
 101     CHIP_R600,
 102     CHIP_RV610,
 103     CHIP_RV630,
 104     CHIP_RV670,
 105     CHIP_RV620,
 106     CHIP_RV635,
 107     CHIP_RS780,
 108     CHIP_RS880,
 109     CHIP_RV770,
 110     CHIP_RV730,
 111     CHIP_RV710,
 112     CHIP_RV740,
 113     CHIP_CEDAR,
 114     CHIP_REDWOOD,
 115     CHIP_JUNIPER,
 116     CHIP_CYPRESS,
 117     CHIP_HEMLOCK,
 118     CHIP_PALM,
 119     CHIP_SUMO,
 120     CHIP_SUMO2,
 121     CHIP_BARTS,
 122     CHIP_TURKS,
 123     CHIP_CAICOS,
 124     CHIP_CAYMAN,
 125     CHIP_ARUBA,
 126     CHIP_TAHITI,
 127     CHIP_PITCAIRN,
 128     CHIP_VERDE,
 129     CHIP_OLAND,
 130     CHIP_HAINAN,
 131     CHIP_BONAIRE,
 132     CHIP_KAVERI,
 133     CHIP_KABINI,
 134     CHIP_HAWAII,
 135     CHIP_MULLINS,
 136     CHIP_TONGA,
 137     CHIP_ICELAND,
 138     CHIP_CARRIZO,
 139     CHIP_FIJI,
 140     CHIP_LAST,
 141 };
 142
 143 enum chip_class {
 144     CLASS_UNKNOWN = 0,
 145     R300,
 146     R400,
 147     R500,
 148     R600,
 149     R700,
 150     EVERGREEN,
 151     CAYMAN,
 152     SI,
 153     CIK,
 154     VI,
 155 };
 156
 157 enum ring_type {
 158     RING_GFX = 0,
 159     RING_COMPUTE,
 160     RING_DMA,
 161     RING_UVD,
 162     RING_VCE,
 163     RING_LAST,
 164 };
 165
 166 enum radeon_value_id {
 167     RADEON_REQUESTED_VRAM_MEMORY,
 168     RADEON_REQUESTED_GTT_MEMORY,
 169     RADEON_BUFFER_WAIT_TIME_NS,
 170     RADEON_TIMESTAMP,
 171     RADEON_NUM_CS_FLUSHES,
 172     RADEON_NUM_BYTES_MOVED,
 173     RADEON_VRAM_USAGE,
 174     RADEON_GTT_USAGE,
 175     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 176     RADEON_CURRENT_SCLK,
 177     RADEON_CURRENT_MCLK,
 178     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 179 };
 180
 181 /* Each group of four has the same priority. */
 182 enum radeon_bo_priority {
 183     RADEON_PRIO_FENCE = 0,
 184     RADEON_PRIO_TRACE,
 185     RADEON_PRIO_SO_FILLED_SIZE,
 186     RADEON_PRIO_QUERY,
 187
 188     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 189     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 190     RADEON_PRIO_DRAW_INDIRECT,
 191     RADEON_PRIO_INDEX_BUFFER,
 192
 193     RADEON_PRIO_CP_DMA = 8,
 194
 195     RADEON_PRIO_VCE = 12,
 196     RADEON_PRIO_UVD,
 197     RADEON_PRIO_SDMA_BUFFER,
 198     RADEON_PRIO_SDMA_TEXTURE,
 199
 200     RADEON_PRIO_USER_SHADER = 16,
 201     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 202
 203     /* gap: 20 */
 204
 205     RADEON_PRIO_CONST_BUFFER = 24,
 206     RADEON_PRIO_DESCRIPTORS,
 207     RADEON_PRIO_BORDER_COLORS,
 208
 209     RADEON_PRIO_SAMPLER_BUFFER = 28,
 210     RADEON_PRIO_VERTEX_BUFFER,
 211
 212     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 213     RADEON_PRIO_RINGS_STREAMOUT,
 214     RADEON_PRIO_SCRATCH_BUFFER,
 215     RADEON_PRIO_COMPUTE_GLOBAL,
 216
 217     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 218     RADEON_PRIO_SHADER_RW_IMAGE,
 219
 220     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 221
 222     RADEON_PRIO_COLOR_BUFFER = 44,
 223
 224     RADEON_PRIO_DEPTH_BUFFER = 48,
 225
 226     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 227
 228     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 229
 230     RADEON_PRIO_CMASK = 60,
 231     RADEON_PRIO_DCC,
 232     RADEON_PRIO_HTILE,
 233     /* 63 is the maximum value */
 234 };
 235
 236 struct winsys_handle;
 237 struct radeon_winsys_cs_handle;
 238 struct radeon_winsys_ctx;
 239
 240 struct radeon_winsys_cs {
 241     unsigned                    cdw;  /* Number of used dwords. */
 242     unsigned                    max_dw; /* Maximum number of dwords. */
 243     uint32_t                    *buf; /* The command buffer. */
 244     enum ring_type              ring_type;
 245 };
 246
 247 struct radeon_info {
 248     uint32_t                    pci_id;
 249     enum radeon_family          family;
 250     enum chip_class             chip_class;
 251     uint64_t                    gart_size;
 252     uint64_t                    vram_size;
 253     uint32_t                    max_sclk;
 254     uint32_t                    max_compute_units;
 255     uint32_t                    max_se;
 256     uint32_t                    max_sh_per_se;
 257
 258     uint32_t                    drm_major; /* version */
 259     uint32_t                    drm_minor;
 260     uint32_t                    drm_patchlevel;
 261
 262     boolean                     has_uvd;
 263     uint32_t                    vce_fw_version;
 264     boolean                     has_userptr;
 265     bool                        gfx_ib_pad_with_type2;
 266
 267     uint32_t                    r300_num_gb_pipes;
 268     uint32_t                    r300_num_z_pipes;
 269
 270     uint32_t                    r600_num_backends;
 271     uint32_t                    r600_clock_crystal_freq;
 272     uint32_t                    r600_tiling_config;
 273     uint32_t                    r600_num_tile_pipes;
 274     uint32_t                    r600_max_pipes;
 275     boolean                     r600_virtual_address;
 276     boolean                     r600_has_dma;
 277
 278     uint32_t                    r600_backend_map;
 279     boolean                     r600_backend_map_valid;
 280
 281     boolean                     si_tile_mode_array_valid;
 282     uint32_t                    si_tile_mode_array[32];
 283     uint32_t                    si_backend_enabled_mask;
 284
 285     boolean                     cik_macrotile_mode_array_valid;
 286     uint32_t                    cik_macrotile_mode_array[16];
 287     uint32_t                    vce_harvest_config;
 288 };
 289
 290 enum radeon_feature_id {
 291     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 292     RADEON_FID_R300_CMASK_ACCESS,
 293 };
 294
 295 #define RADEON_SURF_MAX_LEVEL                   32
 296
 297 #define RADEON_SURF_TYPE_MASK                   0xFF
 298 #define RADEON_SURF_TYPE_SHIFT                  0
 299 #define     RADEON_SURF_TYPE_1D                     0
 300 #define     RADEON_SURF_TYPE_2D                     1
 301 #define     RADEON_SURF_TYPE_3D                     2
 302 #define     RADEON_SURF_TYPE_CUBEMAP                3
 303 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 304 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 305 #define RADEON_SURF_MODE_MASK                   0xFF
 306 #define RADEON_SURF_MODE_SHIFT                  8
 307 #define     RADEON_SURF_MODE_LINEAR                 0
 308 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 309 #define     RADEON_SURF_MODE_1D                     2
 310 #define     RADEON_SURF_MODE_2D                     3
 311 #define RADEON_SURF_SCANOUT                     (1 << 16)
 312 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 313 #define RADEON_SURF_SBUFFER                     (1 << 18)
 314 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 315 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 316 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 317 #define RADEON_SURF_FMASK                       (1 << 21)
 318
 319 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 320 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 321 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 322
 323 struct radeon_surf_level {
 324     uint64_t                    offset;
 325     uint64_t                    slice_size;
 326     uint32_t                    npix_x;
 327     uint32_t                    npix_y;
 328     uint32_t                    npix_z;
 329     uint32_t                    nblk_x;
 330     uint32_t                    nblk_y;
 331     uint32_t                    nblk_z;
 332     uint32_t                    pitch_bytes;
 333     uint32_t                    mode;
 334 };
 335
 336 struct radeon_surf {
 337     /* These are inputs to the calculator. */
 338     uint32_t                    npix_x;
 339     uint32_t                    npix_y;
 340     uint32_t                    npix_z;
 341     uint32_t                    blk_w;
 342     uint32_t                    blk_h;
 343     uint32_t                    blk_d;
 344     uint32_t                    array_size;
 345     uint32_t                    last_level;
 346     uint32_t                    bpe;
 347     uint32_t                    nsamples;
 348     uint32_t                    flags;
 349
 350     /* These are return values. Some of them can be set by the caller, but
 351      * they will be treated as hints (e.g. bankw, bankh) and might be
 352      * changed by the calculator.
 353      */
 354     uint64_t                    bo_size;
 355     uint64_t                    bo_alignment;
 356     /* This applies to EG and later. */
 357     uint32_t                    bankw;
 358     uint32_t                    bankh;
 359     uint32_t                    mtilea;
 360     uint32_t                    tile_split;
 361     uint32_t                    stencil_tile_split;
 362     uint64_t                    stencil_offset;
 363     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 364     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 365     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 366     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 367     uint32_t                    pipe_config;
 368     uint32_t                    num_banks;
 369 };
 370
 371 struct radeon_winsys {
 372     /**
 373      * The screen object this winsys was created for
 374      */
 375     struct pipe_screen *screen;
 376
 377     /**
 378      * Decrement the winsys reference count.
 379      *
 380      * \param ws  The winsys this function is called for.
 381      * \return    True if the winsys and screen should be destroyed.
 382      */
 383     bool (*unref)(struct radeon_winsys *ws);
 384
 385     /**
 386      * Destroy this winsys.
 387      *
 388      * \param ws        The winsys this function is called from.
 389      */
 390     void (*destroy)(struct radeon_winsys *ws);
 391
 392     /**
 393      * Query an info structure from winsys.
 394      *
 395      * \param ws        The winsys this function is called from.
 396      * \param info      Return structure
 397      */
 398     void (*query_info)(struct radeon_winsys *ws,
 399                        struct radeon_info *info);
 400
 401     /**************************************************************************
 402      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 403      *
 404      * Remember that gallium gets to choose the interface it needs, and the
 405      * window systems must then implement that interface (rather than the
 406      * other way around...).
 407      *************************************************************************/
 408
 409     /**
 410      * Create a buffer object.
 411      *
 412      * \param ws        The winsys this function is called from.
 413      * \param size      The size to allocate.
 414      * \param alignment An alignment of the buffer in memory.
 415      * \param use_reusable_pool Whether the cache buffer manager should be used.
 416      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 417      * \return          The created buffer object.
 418      */
 419     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 420                                        unsigned size,
 421                                        unsigned alignment,
 422                                        boolean use_reusable_pool,
 423                                        enum radeon_bo_domain domain,
 424                                        enum radeon_bo_flag flags);
 425
 426     struct radeon_winsys_cs_handle *(*buffer_get_cs_handle)(
 427             struct pb_buffer *buf);
 428
 429     /**
 430      * Map the entire data store of a buffer object into the client's address
 431      * space.
 432      *
 433      * \param buf       A winsys buffer object to map.
 434      * \param cs        A command stream to flush if the buffer is referenced by it.
 435      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 436      * \return          The pointer at the beginning of the buffer.
 437      */
 438     void *(*buffer_map)(struct radeon_winsys_cs_handle *buf,
 439                         struct radeon_winsys_cs *cs,
 440                         enum pipe_transfer_usage usage);
 441
 442     /**
 443      * Unmap a buffer object from the client's address space.
 444      *
 445      * \param buf       A winsys buffer object to unmap.
 446      */
 447     void (*buffer_unmap)(struct radeon_winsys_cs_handle *buf);
 448
 449     /**
 450      * Wait for the buffer and return true if the buffer is not used
 451      * by the device.
 452      *
 453      * The timeout of 0 will only return the status.
 454      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 455      * is idle.
 456      */
 457     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 458                         enum radeon_bo_usage usage);
 459
 460     /**
 461      * Return tiling flags describing a memory layout of a buffer object.
 462      *
 463      * \param buf       A winsys buffer object to get the flags from.
 464      * \param macrotile A pointer to the return value of the microtile flag.
 465      * \param microtile A pointer to the return value of the macrotile flag.
 466      *
 467      * \note microtile and macrotile are not bitmasks!
 468      */
 469     void (*buffer_get_tiling)(struct pb_buffer *buf,
 470                               enum radeon_bo_layout *microtile,
 471                               enum radeon_bo_layout *macrotile,
 472                               unsigned *bankw, unsigned *bankh,
 473                               unsigned *tile_split,
 474                               unsigned *stencil_tile_split,
 475                               unsigned *mtilea,
 476                               bool *scanout);
 477
 478     /**
 479      * Set tiling flags describing a memory layout of a buffer object.
 480      *
 481      * \param buf       A winsys buffer object to set the flags for.
 482      * \param cs        A command stream to flush if the buffer is referenced by it.
 483      * \param macrotile A macrotile flag.
 484      * \param microtile A microtile flag.
 485      * \param stride    A stride of the buffer in bytes, for texturing.
 486      *
 487      * \note microtile and macrotile are not bitmasks!
 488      */
 489     void (*buffer_set_tiling)(struct pb_buffer *buf,
 490                               struct radeon_winsys_cs *rcs,
 491                               enum radeon_bo_layout microtile,
 492                               enum radeon_bo_layout macrotile,
 493                               unsigned pipe_config,
 494                               unsigned bankw, unsigned bankh,
 495                               unsigned tile_split,
 496                               unsigned stencil_tile_split,
 497                               unsigned mtilea, unsigned num_banks,
 498                               unsigned stride,
 499                               bool scanout);
 500
 501     /**
 502      * Get a winsys buffer from a winsys handle. The internal structure
 503      * of the handle is platform-specific and only a winsys should access it.
 504      *
 505      * \param ws        The winsys this function is called from.
 506      * \param whandle   A winsys handle pointer as was received from a state
 507      *                  tracker.
 508      * \param stride    The returned buffer stride in bytes.
 509      */
 510     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 511                                             struct winsys_handle *whandle,
 512                                             unsigned *stride);
 513
 514     /**
 515      * Get a winsys buffer from a user pointer. The resulting buffer can't
 516      * be exported. Both pointer and size must be page aligned.
 517      *
 518      * \param ws        The winsys this function is called from.
 519      * \param pointer   User pointer to turn into a buffer object.
 520      * \param Size      Size in bytes for the new buffer.
 521      */
 522     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 523                                          void *pointer, unsigned size);
 524
 525     /**
 526      * Get a winsys handle from a winsys buffer. The internal structure
 527      * of the handle is platform-specific and only a winsys should access it.
 528      *
 529      * \param buf       A winsys buffer object to get the handle from.
 530      * \param whandle   A winsys handle pointer.
 531      * \param stride    A stride of the buffer in bytes, for texturing.
 532      * \return          TRUE on success.
 533      */
 534     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 535                                  unsigned stride,
 536                                  struct winsys_handle *whandle);
 537
 538     /**
 539      * Return the virtual address of a buffer.
 540      *
 541      * \param buf       A winsys buffer object
 542      * \return          virtual address
 543      */
 544     uint64_t (*buffer_get_virtual_address)(struct radeon_winsys_cs_handle *buf);
 545
 546     /**
 547      * Query the initial placement of the buffer from the kernel driver.
 548      */
 549     enum radeon_bo_domain (*buffer_get_initial_domain)(struct radeon_winsys_cs_handle *buf);
 550
 551     /**************************************************************************
 552      * Command submission.
 553      *
 554      * Each pipe context should create its own command stream and submit
 555      * commands independently of other contexts.
 556      *************************************************************************/
 557
 558     /**
 559      * Create a command submission context.
 560      * Various command streams can be submitted to the same context.
 561      */
 562     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 563
 564     /**
 565      * Destroy a context.
 566      */
 567     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 568
 569     /**
 570      * Query a GPU reset status.
 571      */
 572     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 573
 574     /**
 575      * Create a command stream.
 576      *
 577      * \param ctx       The submission context
 578      * \param ring_type The ring type (GFX, DMA, UVD)
 579      * \param flush     Flush callback function associated with the command stream.
 580      * \param user      User pointer that will be passed to the flush callback.
 581      * \param trace_buf Trace buffer when tracing is enabled
 582      */
 583     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 584                                           enum ring_type ring_type,
 585                                           void (*flush)(void *ctx, unsigned flags,
 586                                                         struct pipe_fence_handle **fence),
 587                                           void *flush_ctx,
 588                                           struct radeon_winsys_cs_handle *trace_buf);
 589
 590     /**
 591      * Destroy a command stream.
 592      *
 593      * \param cs        A command stream to destroy.
 594      */
 595     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 596
 597     /**
 598      * Add a buffer. Each buffer used by a CS must be added using this function.
 599      *
 600      * \param cs      Command stream
 601      * \param buf     Buffer
 602      * \param usage   Whether the buffer is used for read and/or write.
 603      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 604      * \param priority  A higher number means a greater chance of being
 605      *                  placed in the requested domain. 15 is the maximum.
 606      * \return Buffer index.
 607      */
 608     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 609                              struct radeon_winsys_cs_handle *buf,
 610                              enum radeon_bo_usage usage,
 611                              enum radeon_bo_domain domain,
 612                              enum radeon_bo_priority priority);
 613
 614     /**
 615      * Return the index of an already-added buffer.
 616      *
 617      * \param cs        Command stream
 618      * \param buf       Buffer
 619      * \return          The buffer index, or -1 if the buffer has not been added.
 620      */
 621     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 622                             struct radeon_winsys_cs_handle *buf);
 623
 624     /**
 625      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 626      * added so far. If the validation fails, all buffers which have
 627      * been added since the last call of cs_validate will be removed and
 628      * the CS will be flushed (provided there are still any buffers).
 629      *
 630      * \param cs        A command stream to validate.
 631      */
 632     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 633
 634     /**
 635      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 636      * added so far.
 637      *
 638      * \param cs        A command stream to validate.
 639      * \param vram      VRAM memory size pending to be use
 640      * \param gtt       GTT memory size pending to be use
 641      */
 642     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 643
 644     /**
 645      * Flush a command stream.
 646      *
 647      * \param cs          A command stream to flush.
 648      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 649      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 650      *                    after the CS and is returned through this parameter.
 651      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 652      */
 653     void (*cs_flush)(struct radeon_winsys_cs *cs,
 654                      unsigned flags,
 655                      struct pipe_fence_handle **fence,
 656                      uint32_t cs_trace_id);
 657
 658     /**
 659      * Return TRUE if a buffer is referenced by a command stream.
 660      *
 661      * \param cs        A command stream.
 662      * \param buf       A winsys buffer.
 663      */
 664     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 665                                        struct radeon_winsys_cs_handle *buf,
 666                                        enum radeon_bo_usage usage);
 667
 668     /**
 669      * Request access to a feature for a command stream.
 670      *
 671      * \param cs        A command stream.
 672      * \param fid       Feature ID, one of RADEON_FID_*
 673      * \param enable    Whether to enable or disable the feature.
 674      */
 675     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 676                                   enum radeon_feature_id fid,
 677                                   boolean enable);
 678      /**
 679       * Make sure all asynchronous flush of the cs have completed
 680       *
 681       * \param cs        A command stream.
 682       */
 683     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 684
 685     /**
 686      * Wait for the fence and return true if the fence has been signalled.
 687      * The timeout of 0 will only return the status.
 688      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 689      * is signalled.
 690      */
 691     bool (*fence_wait)(struct radeon_winsys *ws,
 692                        struct pipe_fence_handle *fence,
 693                        uint64_t timeout);
 694
 695     /**
 696      * Reference counting for fences.
 697      */
 698     void (*fence_reference)(struct pipe_fence_handle **dst,
 699                             struct pipe_fence_handle *src);
 700
 701     /**
 702      * Initialize surface
 703      *
 704      * \param ws        The winsys this function is called from.
 705      * \param surf      Surface structure ptr
 706      */
 707     int (*surface_init)(struct radeon_winsys *ws,
 708                         struct radeon_surf *surf);
 709
 710     /**
 711      * Find best values for a surface
 712      *
 713      * \param ws        The winsys this function is called from.
 714      * \param surf      Surface structure ptr
 715      */
 716     int (*surface_best)(struct radeon_winsys *ws,
 717                         struct radeon_surf *surf);
 718
 719     uint64_t (*query_value)(struct radeon_winsys *ws,
 720                             enum radeon_value_id value);
 721
 722     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 723                            unsigned num_registers, uint32_t *out);
 724 };
 725
 726
 727 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 728 {
 729     cs->buf[cs->cdw++] = value;
 730 }
 731
 732 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 733                                      const uint32_t *values, unsigned count)
 734 {
 735     memcpy(cs->buf+cs->cdw, values, count * 4);
 736     cs->cdw += count;
 737 }
 738
 739 #endif