src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #include "amd/common/ac_gpu_info.h"
  32 #include "amd/common/ac_surface.h"
  33
  34 /* Tiling flags. */
  35 enum radeon_bo_layout {
  36     RADEON_LAYOUT_LINEAR = 0,
  37     RADEON_LAYOUT_TILED,
  38     RADEON_LAYOUT_SQUARETILED,
  39
  40     RADEON_LAYOUT_UNKNOWN
  41 };
  42
  43 enum radeon_bo_domain { /* bitfield */
  44     RADEON_DOMAIN_GTT  = 2,
  45     RADEON_DOMAIN_VRAM = 4,
  46     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  47 };
  48
  49 enum radeon_bo_flag { /* bitfield */
  50     RADEON_FLAG_GTT_WC =        (1 << 0),
  51     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  52     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  53     RADEON_FLAG_SPARSE =        (1 << 3),
  54     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  55     RADEON_FLAG_READ_ONLY =     (1 << 5),
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59     RADEON_USAGE_READ = 2,
  60     RADEON_USAGE_WRITE = 4,
  61     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  62
  63     /* The winsys ensures that the CS submission will be scheduled after
  64      * previously flushed CSs referencing this BO in a conflicting way.
  65      */
  66     RADEON_USAGE_SYNCHRONIZED = 8
  67 };
  68
  69 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  70
  71 enum ring_type {
  72     RING_GFX = 0,
  73     RING_COMPUTE,
  74     RING_DMA,
  75     RING_UVD,
  76     RING_VCE,
  77     RING_UVD_ENC,
  78     RING_VCN_DEC,
  79     RING_VCN_ENC,
  80     RING_LAST,
  81 };
  82
  83 enum radeon_value_id {
  84     RADEON_REQUESTED_VRAM_MEMORY,
  85     RADEON_REQUESTED_GTT_MEMORY,
  86     RADEON_MAPPED_VRAM,
  87     RADEON_MAPPED_GTT,
  88     RADEON_BUFFER_WAIT_TIME_NS,
  89     RADEON_NUM_MAPPED_BUFFERS,
  90     RADEON_TIMESTAMP,
  91     RADEON_NUM_GFX_IBS,
  92     RADEON_NUM_SDMA_IBS,
  93     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
  94     RADEON_GFX_IB_SIZE_COUNTER,
  95     RADEON_NUM_BYTES_MOVED,
  96     RADEON_NUM_EVICTIONS,
  97     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  98     RADEON_VRAM_USAGE,
  99     RADEON_VRAM_VIS_USAGE,
 100     RADEON_GTT_USAGE,
 101     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 102     RADEON_CURRENT_SCLK,
 103     RADEON_CURRENT_MCLK,
 104     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 105     RADEON_CS_THREAD_TIME,
 106 };
 107
 108 /* Each group of four has the same priority. */
 109 enum radeon_bo_priority {
 110     RADEON_PRIO_FENCE = 0,
 111     RADEON_PRIO_TRACE,
 112     RADEON_PRIO_SO_FILLED_SIZE,
 113     RADEON_PRIO_QUERY,
 114
 115     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 116     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 117     RADEON_PRIO_DRAW_INDIRECT,
 118     RADEON_PRIO_INDEX_BUFFER,
 119
 120     RADEON_PRIO_VCE = 8,
 121     RADEON_PRIO_UVD,
 122     RADEON_PRIO_SDMA_BUFFER,
 123     RADEON_PRIO_SDMA_TEXTURE,
 124
 125     RADEON_PRIO_CP_DMA = 12,
 126
 127     RADEON_PRIO_CONST_BUFFER = 16,
 128     RADEON_PRIO_DESCRIPTORS,
 129     RADEON_PRIO_BORDER_COLORS,
 130
 131     RADEON_PRIO_SAMPLER_BUFFER = 20,
 132     RADEON_PRIO_VERTEX_BUFFER,
 133
 134     RADEON_PRIO_SHADER_RW_BUFFER = 24,
 135     RADEON_PRIO_COMPUTE_GLOBAL,
 136
 137     RADEON_PRIO_SAMPLER_TEXTURE = 28,
 138     RADEON_PRIO_SHADER_RW_IMAGE,
 139
 140     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
 141
 142     RADEON_PRIO_COLOR_BUFFER = 36,
 143
 144     RADEON_PRIO_DEPTH_BUFFER = 40,
 145
 146     RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
 147
 148     RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
 149
 150     RADEON_PRIO_CMASK = 52,
 151     RADEON_PRIO_DCC,
 152     RADEON_PRIO_HTILE,
 153     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 154
 155     RADEON_PRIO_SHADER_RINGS = 56,
 156
 157     RADEON_PRIO_SCRATCH_BUFFER = 60,
 158     /* 63 is the maximum value */
 159 };
 160
 161 struct winsys_handle;
 162 struct radeon_winsys_ctx;
 163
 164 struct radeon_winsys_cs_chunk {
 165     unsigned cdw;  /* Number of used dwords. */
 166     unsigned max_dw; /* Maximum number of dwords. */
 167     uint32_t *buf; /* The base pointer of the chunk. */
 168 };
 169
 170 struct radeon_winsys_cs {
 171     struct radeon_winsys_cs_chunk current;
 172     struct radeon_winsys_cs_chunk *prev;
 173     unsigned                      num_prev; /* Number of previous chunks. */
 174     unsigned                      max_prev; /* Space in array pointed to by prev. */
 175     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 176
 177     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 178     uint64_t                      used_vram;
 179     uint64_t                      used_gart;
 180 };
 181
 182 /* Tiling info for display code, DRI sharing, and other data. */
 183 struct radeon_bo_metadata {
 184     /* Tiling flags describing the texture layout for display code
 185      * and DRI sharing.
 186      */
 187     union {
 188         struct {
 189             enum radeon_bo_layout   microtile;
 190             enum radeon_bo_layout   macrotile;
 191             unsigned                pipe_config;
 192             unsigned                bankw;
 193             unsigned                bankh;
 194             unsigned                tile_split;
 195             unsigned                mtilea;
 196             unsigned                num_banks;
 197             unsigned                stride;
 198             bool                    scanout;
 199         } legacy;
 200
 201         struct {
 202             /* surface flags */
 203             unsigned swizzle_mode:5;
 204         } gfx9;
 205     } u;
 206
 207     /* Additional metadata associated with the buffer, in bytes.
 208      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 209      * Supported by amdgpu only.
 210      */
 211     uint32_t                size_metadata;
 212     uint32_t                metadata[64];
 213 };
 214
 215 enum radeon_feature_id {
 216     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 217     RADEON_FID_R300_CMASK_ACCESS,
 218 };
 219
 220 struct radeon_bo_list_item {
 221     uint64_t bo_size;
 222     uint64_t vm_address;
 223     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 224 };
 225
 226 struct radeon_winsys {
 227     /**
 228      * The screen object this winsys was created for
 229      */
 230     struct pipe_screen *screen;
 231
 232     /**
 233      * Decrement the winsys reference count.
 234      *
 235      * \param ws  The winsys this function is called for.
 236      * \return    True if the winsys and screen should be destroyed.
 237      */
 238     bool (*unref)(struct radeon_winsys *ws);
 239
 240     /**
 241      * Destroy this winsys.
 242      *
 243      * \param ws        The winsys this function is called from.
 244      */
 245     void (*destroy)(struct radeon_winsys *ws);
 246
 247     /**
 248      * Query an info structure from winsys.
 249      *
 250      * \param ws        The winsys this function is called from.
 251      * \param info      Return structure
 252      */
 253     void (*query_info)(struct radeon_winsys *ws,
 254                        struct radeon_info *info);
 255
 256     /**************************************************************************
 257      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 258      *
 259      * Remember that gallium gets to choose the interface it needs, and the
 260      * window systems must then implement that interface (rather than the
 261      * other way around...).
 262      *************************************************************************/
 263
 264     /**
 265      * Create a buffer object.
 266      *
 267      * \param ws        The winsys this function is called from.
 268      * \param size      The size to allocate.
 269      * \param alignment An alignment of the buffer in memory.
 270      * \param use_reusable_pool Whether the cache buffer manager should be used.
 271      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 272      * \return          The created buffer object.
 273      */
 274     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 275                                        uint64_t size,
 276                                        unsigned alignment,
 277                                        enum radeon_bo_domain domain,
 278                                        enum radeon_bo_flag flags);
 279
 280     /**
 281      * Map the entire data store of a buffer object into the client's address
 282      * space.
 283      *
 284      * \param buf       A winsys buffer object to map.
 285      * \param cs        A command stream to flush if the buffer is referenced by it.
 286      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 287      * \return          The pointer at the beginning of the buffer.
 288      */
 289     void *(*buffer_map)(struct pb_buffer *buf,
 290                         struct radeon_winsys_cs *cs,
 291                         enum pipe_transfer_usage usage);
 292
 293     /**
 294      * Unmap a buffer object from the client's address space.
 295      *
 296      * \param buf       A winsys buffer object to unmap.
 297      */
 298     void (*buffer_unmap)(struct pb_buffer *buf);
 299
 300     /**
 301      * Wait for the buffer and return true if the buffer is not used
 302      * by the device.
 303      *
 304      * The timeout of 0 will only return the status.
 305      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 306      * is idle.
 307      */
 308     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 309                         enum radeon_bo_usage usage);
 310
 311     /**
 312      * Return buffer metadata.
 313      * (tiling info for display code, DRI sharing, and other data)
 314      *
 315      * \param buf       A winsys buffer object to get the flags from.
 316      * \param md        Metadata
 317      */
 318     void (*buffer_get_metadata)(struct pb_buffer *buf,
 319                                 struct radeon_bo_metadata *md);
 320
 321     /**
 322      * Set buffer metadata.
 323      * (tiling info for display code, DRI sharing, and other data)
 324      *
 325      * \param buf       A winsys buffer object to set the flags for.
 326      * \param md        Metadata
 327      */
 328     void (*buffer_set_metadata)(struct pb_buffer *buf,
 329                                 struct radeon_bo_metadata *md);
 330
 331     /**
 332      * Get a winsys buffer from a winsys handle. The internal structure
 333      * of the handle is platform-specific and only a winsys should access it.
 334      *
 335      * \param ws        The winsys this function is called from.
 336      * \param whandle   A winsys handle pointer as was received from a state
 337      *                  tracker.
 338      * \param stride    The returned buffer stride in bytes.
 339      */
 340     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 341                                             struct winsys_handle *whandle,
 342                                             unsigned *stride, unsigned *offset);
 343
 344     /**
 345      * Get a winsys buffer from a user pointer. The resulting buffer can't
 346      * be exported. Both pointer and size must be page aligned.
 347      *
 348      * \param ws        The winsys this function is called from.
 349      * \param pointer   User pointer to turn into a buffer object.
 350      * \param Size      Size in bytes for the new buffer.
 351      */
 352     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 353                                          void *pointer, uint64_t size);
 354
 355     /**
 356      * Whether the buffer was created from a user pointer.
 357      *
 358      * \param buf       A winsys buffer object
 359      * \return          whether \p buf was created via buffer_from_ptr
 360      */
 361     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 362
 363     /** Whether the buffer was suballocated. */
 364     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 365
 366     /**
 367      * Get a winsys handle from a winsys buffer. The internal structure
 368      * of the handle is platform-specific and only a winsys should access it.
 369      *
 370      * \param buf       A winsys buffer object to get the handle from.
 371      * \param whandle   A winsys handle pointer.
 372      * \param stride    A stride of the buffer in bytes, for texturing.
 373      * \return          true on success.
 374      */
 375     bool (*buffer_get_handle)(struct pb_buffer *buf,
 376                               unsigned stride, unsigned offset,
 377                               unsigned slice_size,
 378                               struct winsys_handle *whandle);
 379
 380     /**
 381      * Change the commitment of a (64KB-page aligned) region of the given
 382      * sparse buffer.
 383      *
 384      * \warning There is no automatic synchronization with command submission.
 385      *
 386      * \note Only implemented by the amdgpu winsys.
 387      *
 388      * \return false on out of memory or other failure, true on success.
 389      */
 390     bool (*buffer_commit)(struct pb_buffer *buf,
 391                           uint64_t offset, uint64_t size,
 392                           bool commit);
 393
 394     /**
 395      * Return the virtual address of a buffer.
 396      *
 397      * When virtual memory is not in use, this is the offset relative to the
 398      * relocation base (non-zero for sub-allocated buffers).
 399      *
 400      * \param buf       A winsys buffer object
 401      * \return          virtual address
 402      */
 403     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 404
 405     /**
 406      * Return the offset of this buffer relative to the relocation base.
 407      * This is only non-zero for sub-allocated buffers.
 408      *
 409      * This is only supported in the radeon winsys, since amdgpu uses virtual
 410      * addresses in submissions even for the video engines.
 411      *
 412      * \param buf      A winsys buffer object
 413      * \return         the offset for relocations
 414      */
 415     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 416
 417     /**
 418      * Query the initial placement of the buffer from the kernel driver.
 419      */
 420     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 421
 422     /**************************************************************************
 423      * Command submission.
 424      *
 425      * Each pipe context should create its own command stream and submit
 426      * commands independently of other contexts.
 427      *************************************************************************/
 428
 429     /**
 430      * Create a command submission context.
 431      * Various command streams can be submitted to the same context.
 432      */
 433     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 434
 435     /**
 436      * Destroy a context.
 437      */
 438     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 439
 440     /**
 441      * Query a GPU reset status.
 442      */
 443     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 444
 445     /**
 446      * Create a command stream.
 447      *
 448      * \param ctx       The submission context
 449      * \param ring_type The ring type (GFX, DMA, UVD)
 450      * \param flush     Flush callback function associated with the command stream.
 451      * \param user      User pointer that will be passed to the flush callback.
 452      */
 453     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 454                                           enum ring_type ring_type,
 455                                           void (*flush)(void *ctx, unsigned flags,
 456                                                         struct pipe_fence_handle **fence),
 457                                           void *flush_ctx);
 458
 459     /**
 460      * Destroy a command stream.
 461      *
 462      * \param cs        A command stream to destroy.
 463      */
 464     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 465
 466     /**
 467      * Add a buffer. Each buffer used by a CS must be added using this function.
 468      *
 469      * \param cs      Command stream
 470      * \param buf     Buffer
 471      * \param usage   Whether the buffer is used for read and/or write.
 472      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 473      * \param priority  A higher number means a greater chance of being
 474      *                  placed in the requested domain. 15 is the maximum.
 475      * \return Buffer index.
 476      */
 477     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 478                              struct pb_buffer *buf,
 479                              enum radeon_bo_usage usage,
 480                              enum radeon_bo_domain domain,
 481                              enum radeon_bo_priority priority);
 482
 483     /**
 484      * Return the index of an already-added buffer.
 485      *
 486      * Not supported on amdgpu. Drivers with GPUVM should not care about
 487      * buffer indices.
 488      *
 489      * \param cs        Command stream
 490      * \param buf       Buffer
 491      * \return          The buffer index, or -1 if the buffer has not been added.
 492      */
 493     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 494                             struct pb_buffer *buf);
 495
 496     /**
 497      * Return true if there is enough memory in VRAM and GTT for the buffers
 498      * added so far. If the validation fails, all buffers which have
 499      * been added since the last call of cs_validate will be removed and
 500      * the CS will be flushed (provided there are still any buffers).
 501      *
 502      * \param cs        A command stream to validate.
 503      */
 504     bool (*cs_validate)(struct radeon_winsys_cs *cs);
 505
 506     /**
 507      * Check whether the given number of dwords is available in the IB.
 508      * Optionally chain a new chunk of the IB if necessary and supported.
 509      *
 510      * \param cs        A command stream.
 511      * \param dw        Number of CS dwords requested by the caller.
 512      */
 513     bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 514
 515     /**
 516      * Return the buffer list.
 517      *
 518      * This is the buffer list as passed to the kernel, i.e. it only contains
 519      * the parent buffers of sub-allocated buffers.
 520      *
 521      * \param cs    Command stream
 522      * \param list  Returned buffer list. Set to NULL to query the count only.
 523      * \return      The buffer count.
 524      */
 525     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 526                                    struct radeon_bo_list_item *list);
 527
 528     /**
 529      * Flush a command stream.
 530      *
 531      * \param cs          A command stream to flush.
 532      * \param flags,      PIPE_FLUSH_* flags.
 533      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 534      *                    after the CS and is returned through this parameter.
 535      * \return Negative POSIX error code or 0 for success.
 536      *         Asynchronous submissions never return an error.
 537      */
 538     int (*cs_flush)(struct radeon_winsys_cs *cs,
 539                     unsigned flags,
 540                     struct pipe_fence_handle **fence);
 541
 542     /**
 543      * Create a fence before the CS is flushed.
 544      * The user must flush manually to complete the initializaton of the fence.
 545      *
 546      * The fence must not be used for anything except \ref cs_add_fence_dependency
 547      * before the flush.
 548      */
 549     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs *cs);
 550
 551     /**
 552      * Return true if a buffer is referenced by a command stream.
 553      *
 554      * \param cs        A command stream.
 555      * \param buf       A winsys buffer.
 556      */
 557     bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 558                                     struct pb_buffer *buf,
 559                                     enum radeon_bo_usage usage);
 560
 561     /**
 562      * Request access to a feature for a command stream.
 563      *
 564      * \param cs        A command stream.
 565      * \param fid       Feature ID, one of RADEON_FID_*
 566      * \param enable    Whether to enable or disable the feature.
 567      */
 568     bool (*cs_request_feature)(struct radeon_winsys_cs *cs,
 569                                enum radeon_feature_id fid,
 570                                bool enable);
 571      /**
 572       * Make sure all asynchronous flush of the cs have completed
 573       *
 574       * \param cs        A command stream.
 575       */
 576     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 577
 578     /**
 579      * Add a fence dependency to the CS, so that the CS will wait for
 580      * the fence before execution.
 581      */
 582     void (*cs_add_fence_dependency)(struct radeon_winsys_cs *cs,
 583                                     struct pipe_fence_handle *fence);
 584
 585     /**
 586      * Wait for the fence and return true if the fence has been signalled.
 587      * The timeout of 0 will only return the status.
 588      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 589      * is signalled.
 590      */
 591     bool (*fence_wait)(struct radeon_winsys *ws,
 592                        struct pipe_fence_handle *fence,
 593                        uint64_t timeout);
 594
 595     /**
 596      * Reference counting for fences.
 597      */
 598     void (*fence_reference)(struct pipe_fence_handle **dst,
 599                             struct pipe_fence_handle *src);
 600
 601     /**
 602      * Create a new fence object corresponding to the given sync_file.
 603      */
 604     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 605                                                         int fd);
 606
 607     /**
 608      * Return a sync_file FD corresponding to the given fence object.
 609      */
 610     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 611                                   struct pipe_fence_handle *fence);
 612
 613     /**
 614      * Return a sync file FD that is already signalled.
 615      */
 616     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 617
 618     /**
 619      * Initialize surface
 620      *
 621      * \param ws        The winsys this function is called from.
 622      * \param tex       Input texture description
 623      * \param flags     Bitmask of RADEON_SURF_* flags
 624      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 625      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 626      * \param surf      Output structure
 627      */
 628     int (*surface_init)(struct radeon_winsys *ws,
 629                         const struct pipe_resource *tex,
 630                         unsigned flags, unsigned bpe,
 631                         enum radeon_surf_mode mode,
 632                         struct radeon_surf *surf);
 633
 634     uint64_t (*query_value)(struct radeon_winsys *ws,
 635                             enum radeon_value_id value);
 636
 637     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 638                            unsigned num_registers, uint32_t *out);
 639
 640     const char* (*get_chip_name)(struct radeon_winsys *ws);
 641 };
 642
 643 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 644 {
 645     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 646 }
 647
 648 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 649 {
 650     cs->current.buf[cs->current.cdw++] = value;
 651 }
 652
 653 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 654                                      const uint32_t *values, unsigned count)
 655 {
 656     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 657     cs->current.cdw += count;
 658 }
 659
 660 enum radeon_heap {
 661     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 662     RADEON_HEAP_VRAM_READ_ONLY,
 663     RADEON_HEAP_VRAM,
 664     RADEON_HEAP_GTT_WC,
 665     RADEON_HEAP_GTT_WC_READ_ONLY,
 666     RADEON_HEAP_GTT,
 667     RADEON_MAX_SLAB_HEAPS,
 668     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 669 };
 670
 671 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 672 {
 673     switch (heap) {
 674     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 675     case RADEON_HEAP_VRAM_READ_ONLY:
 676     case RADEON_HEAP_VRAM:
 677         return RADEON_DOMAIN_VRAM;
 678     case RADEON_HEAP_GTT_WC:
 679     case RADEON_HEAP_GTT_WC_READ_ONLY:
 680     case RADEON_HEAP_GTT:
 681         return RADEON_DOMAIN_GTT;
 682     default:
 683         assert(0);
 684         return (enum radeon_bo_domain)0;
 685     }
 686 }
 687
 688 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 689 {
 690     switch (heap) {
 691     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 692         return RADEON_FLAG_GTT_WC |
 693                RADEON_FLAG_NO_CPU_ACCESS |
 694                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 695
 696     case RADEON_HEAP_VRAM_READ_ONLY:
 697         return RADEON_FLAG_GTT_WC |
 698                RADEON_FLAG_NO_INTERPROCESS_SHARING |
 699                RADEON_FLAG_READ_ONLY;
 700
 701     case RADEON_HEAP_VRAM:
 702     case RADEON_HEAP_GTT_WC:
 703         return RADEON_FLAG_GTT_WC |
 704                RADEON_FLAG_NO_INTERPROCESS_SHARING;
 705
 706     case RADEON_HEAP_GTT_WC_READ_ONLY:
 707         return RADEON_FLAG_GTT_WC |
 708                RADEON_FLAG_NO_INTERPROCESS_SHARING |
 709                RADEON_FLAG_READ_ONLY;
 710
 711     case RADEON_HEAP_GTT:
 712     default:
 713         return RADEON_FLAG_NO_INTERPROCESS_SHARING;
 714     }
 715 }
 716
 717 /* The pb cache bucket is chosen to minimize pb_cache misses.
 718  * It must be between 0 and 3 inclusive.
 719  */
 720 static inline unsigned radeon_get_pb_cache_bucket_index(enum radeon_heap heap)
 721 {
 722     switch (heap) {
 723     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 724         return 0;
 725     case RADEON_HEAP_VRAM_READ_ONLY:
 726     case RADEON_HEAP_VRAM:
 727         return 1;
 728     case RADEON_HEAP_GTT_WC:
 729     case RADEON_HEAP_GTT_WC_READ_ONLY:
 730         return 2;
 731     case RADEON_HEAP_GTT:
 732     default:
 733         return 3;
 734     }
 735 }
 736
 737 /* Return the heap index for winsys allocators, or -1 on failure. */
 738 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 739                                         enum radeon_bo_flag flags)
 740 {
 741     /* VRAM implies WC (write combining) */
 742     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 743     /* NO_CPU_ACCESS implies VRAM only. */
 744     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 745
 746     /* Resources with interprocess sharing don't use any winsys allocators. */
 747     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 748         return -1;
 749
 750     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 751     if (flags & ~(RADEON_FLAG_GTT_WC |
 752                   RADEON_FLAG_NO_CPU_ACCESS |
 753                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 754                   RADEON_FLAG_READ_ONLY))
 755         return -1;
 756
 757     switch (domain) {
 758     case RADEON_DOMAIN_VRAM:
 759         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY)) {
 760         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 761             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 762             return -1;
 763         case RADEON_FLAG_NO_CPU_ACCESS:
 764             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 765         case RADEON_FLAG_READ_ONLY:
 766             return RADEON_HEAP_VRAM_READ_ONLY;
 767         case 0:
 768             return RADEON_HEAP_VRAM;
 769         }
 770         break;
 771     case RADEON_DOMAIN_GTT:
 772         switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY)) {
 773         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 774             return RADEON_HEAP_GTT_WC_READ_ONLY;
 775         case RADEON_FLAG_GTT_WC:
 776             return RADEON_HEAP_GTT_WC;
 777         case RADEON_FLAG_READ_ONLY:
 778             assert(!"READ_ONLY without WC is disallowed");
 779             return -1;
 780         case 0:
 781             return RADEON_HEAP_GTT;
 782         }
 783         break;
 784     default:
 785         break;
 786     }
 787     return -1;
 788 }
 789
 790 #endif