src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #define RADEON_FLUSH_ASYNC              (1 << 0)
  46 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  47 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  48
  49 /* Tiling flags. */
  50 enum radeon_bo_layout {
  51     RADEON_LAYOUT_LINEAR = 0,
  52     RADEON_LAYOUT_TILED,
  53     RADEON_LAYOUT_SQUARETILED,
  54
  55     RADEON_LAYOUT_UNKNOWN
  56 };
  57
  58 enum radeon_bo_domain { /* bitfield */
  59     RADEON_DOMAIN_GTT  = 2,
  60     RADEON_DOMAIN_VRAM = 4,
  61     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  62 };
  63
  64 enum radeon_bo_flag { /* bitfield */
  65     RADEON_FLAG_GTT_WC =        (1 << 0),
  66     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  67     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  68 };
  69
  70 enum radeon_bo_usage { /* bitfield */
  71     RADEON_USAGE_READ = 2,
  72     RADEON_USAGE_WRITE = 4,
  73     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  74 };
  75
  76 enum radeon_family {
  77     CHIP_UNKNOWN = 0,
  78     CHIP_R300, /* R3xx-based cores. */
  79     CHIP_R350,
  80     CHIP_RV350,
  81     CHIP_RV370,
  82     CHIP_RV380,
  83     CHIP_RS400,
  84     CHIP_RC410,
  85     CHIP_RS480,
  86     CHIP_R420,     /* R4xx-based cores. */
  87     CHIP_R423,
  88     CHIP_R430,
  89     CHIP_R480,
  90     CHIP_R481,
  91     CHIP_RV410,
  92     CHIP_RS600,
  93     CHIP_RS690,
  94     CHIP_RS740,
  95     CHIP_RV515,    /* R5xx-based cores. */
  96     CHIP_R520,
  97     CHIP_RV530,
  98     CHIP_R580,
  99     CHIP_RV560,
 100     CHIP_RV570,
 101     CHIP_R600,
 102     CHIP_RV610,
 103     CHIP_RV630,
 104     CHIP_RV670,
 105     CHIP_RV620,
 106     CHIP_RV635,
 107     CHIP_RS780,
 108     CHIP_RS880,
 109     CHIP_RV770,
 110     CHIP_RV730,
 111     CHIP_RV710,
 112     CHIP_RV740,
 113     CHIP_CEDAR,
 114     CHIP_REDWOOD,
 115     CHIP_JUNIPER,
 116     CHIP_CYPRESS,
 117     CHIP_HEMLOCK,
 118     CHIP_PALM,
 119     CHIP_SUMO,
 120     CHIP_SUMO2,
 121     CHIP_BARTS,
 122     CHIP_TURKS,
 123     CHIP_CAICOS,
 124     CHIP_CAYMAN,
 125     CHIP_ARUBA,
 126     CHIP_TAHITI,
 127     CHIP_PITCAIRN,
 128     CHIP_VERDE,
 129     CHIP_OLAND,
 130     CHIP_HAINAN,
 131     CHIP_BONAIRE,
 132     CHIP_KAVERI,
 133     CHIP_KABINI,
 134     CHIP_HAWAII,
 135     CHIP_MULLINS,
 136     CHIP_TONGA,
 137     CHIP_ICELAND,
 138     CHIP_CARRIZO,
 139     CHIP_FIJI,
 140     CHIP_STONEY,
 141     CHIP_LAST,
 142 };
 143
 144 enum chip_class {
 145     CLASS_UNKNOWN = 0,
 146     R300,
 147     R400,
 148     R500,
 149     R600,
 150     R700,
 151     EVERGREEN,
 152     CAYMAN,
 153     SI,
 154     CIK,
 155     VI,
 156 };
 157
 158 enum ring_type {
 159     RING_GFX = 0,
 160     RING_COMPUTE,
 161     RING_DMA,
 162     RING_UVD,
 163     RING_VCE,
 164     RING_LAST,
 165 };
 166
 167 enum radeon_value_id {
 168     RADEON_REQUESTED_VRAM_MEMORY,
 169     RADEON_REQUESTED_GTT_MEMORY,
 170     RADEON_BUFFER_WAIT_TIME_NS,
 171     RADEON_TIMESTAMP,
 172     RADEON_NUM_CS_FLUSHES,
 173     RADEON_NUM_BYTES_MOVED,
 174     RADEON_VRAM_USAGE,
 175     RADEON_GTT_USAGE,
 176     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 177     RADEON_CURRENT_SCLK,
 178     RADEON_CURRENT_MCLK,
 179     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 180 };
 181
 182 /* Each group of four has the same priority. */
 183 enum radeon_bo_priority {
 184     RADEON_PRIO_FENCE = 0,
 185     RADEON_PRIO_TRACE,
 186     RADEON_PRIO_SO_FILLED_SIZE,
 187     RADEON_PRIO_QUERY,
 188
 189     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 190     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 191     RADEON_PRIO_DRAW_INDIRECT,
 192     RADEON_PRIO_INDEX_BUFFER,
 193
 194     RADEON_PRIO_CP_DMA = 8,
 195
 196     RADEON_PRIO_VCE = 12,
 197     RADEON_PRIO_UVD,
 198     RADEON_PRIO_SDMA_BUFFER,
 199     RADEON_PRIO_SDMA_TEXTURE,
 200
 201     RADEON_PRIO_USER_SHADER = 16,
 202     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 203
 204     /* gap: 20 */
 205
 206     RADEON_PRIO_CONST_BUFFER = 24,
 207     RADEON_PRIO_DESCRIPTORS,
 208     RADEON_PRIO_BORDER_COLORS,
 209
 210     RADEON_PRIO_SAMPLER_BUFFER = 28,
 211     RADEON_PRIO_VERTEX_BUFFER,
 212
 213     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 214     RADEON_PRIO_RINGS_STREAMOUT,
 215     RADEON_PRIO_SCRATCH_BUFFER,
 216     RADEON_PRIO_COMPUTE_GLOBAL,
 217
 218     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 219     RADEON_PRIO_SHADER_RW_IMAGE,
 220
 221     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 222
 223     RADEON_PRIO_COLOR_BUFFER = 44,
 224
 225     RADEON_PRIO_DEPTH_BUFFER = 48,
 226
 227     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 228
 229     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 230
 231     RADEON_PRIO_CMASK = 60,
 232     RADEON_PRIO_DCC,
 233     RADEON_PRIO_HTILE,
 234     /* 63 is the maximum value */
 235 };
 236
 237 struct winsys_handle;
 238 struct radeon_winsys_ctx;
 239
 240 struct radeon_winsys_cs {
 241     unsigned                    cdw;  /* Number of used dwords. */
 242     unsigned                    max_dw; /* Maximum number of dwords. */
 243     uint32_t                    *buf; /* The command buffer. */
 244     enum ring_type              ring_type;
 245 };
 246
 247 struct radeon_info {
 248     uint32_t                    pci_id;
 249     enum radeon_family          family;
 250     enum chip_class             chip_class;
 251     uint64_t                    gart_size;
 252     uint64_t                    vram_size;
 253     uint32_t                    max_sclk;
 254     uint32_t                    max_compute_units;
 255     uint32_t                    max_se;
 256     uint32_t                    max_sh_per_se;
 257
 258     uint32_t                    drm_major; /* version */
 259     uint32_t                    drm_minor;
 260     uint32_t                    drm_patchlevel;
 261
 262     boolean                     has_uvd;
 263     uint32_t                    vce_fw_version;
 264     boolean                     has_userptr;
 265     bool                        gfx_ib_pad_with_type2;
 266
 267     uint32_t                    r300_num_gb_pipes;
 268     uint32_t                    r300_num_z_pipes;
 269
 270     uint32_t                    r600_num_backends;
 271     uint32_t                    r600_clock_crystal_freq;
 272     uint32_t                    r600_tiling_config;
 273     uint32_t                    r600_num_tile_pipes;
 274     uint32_t                    r600_max_pipes;
 275     boolean                     r600_virtual_address;
 276     boolean                     r600_has_dma;
 277
 278     uint32_t                    r600_backend_map;
 279     boolean                     r600_backend_map_valid;
 280
 281     boolean                     si_tile_mode_array_valid;
 282     uint32_t                    si_tile_mode_array[32];
 283     uint32_t                    si_backend_enabled_mask;
 284
 285     boolean                     cik_macrotile_mode_array_valid;
 286     uint32_t                    cik_macrotile_mode_array[16];
 287     uint32_t                    vce_harvest_config;
 288 };
 289
 290 enum radeon_feature_id {
 291     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 292     RADEON_FID_R300_CMASK_ACCESS,
 293 };
 294
 295 #define RADEON_SURF_MAX_LEVEL                   32
 296
 297 #define RADEON_SURF_TYPE_MASK                   0xFF
 298 #define RADEON_SURF_TYPE_SHIFT                  0
 299 #define     RADEON_SURF_TYPE_1D                     0
 300 #define     RADEON_SURF_TYPE_2D                     1
 301 #define     RADEON_SURF_TYPE_3D                     2
 302 #define     RADEON_SURF_TYPE_CUBEMAP                3
 303 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 304 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 305 #define RADEON_SURF_MODE_MASK                   0xFF
 306 #define RADEON_SURF_MODE_SHIFT                  8
 307 #define     RADEON_SURF_MODE_LINEAR                 0
 308 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 309 #define     RADEON_SURF_MODE_1D                     2
 310 #define     RADEON_SURF_MODE_2D                     3
 311 #define RADEON_SURF_SCANOUT                     (1 << 16)
 312 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 313 #define RADEON_SURF_SBUFFER                     (1 << 18)
 314 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 315 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 316 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 317 #define RADEON_SURF_FMASK                       (1 << 21)
 318
 319 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 320 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 321 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 322
 323 struct radeon_surf_level {
 324     uint64_t                    offset;
 325     uint64_t                    slice_size;
 326     uint32_t                    npix_x;
 327     uint32_t                    npix_y;
 328     uint32_t                    npix_z;
 329     uint32_t                    nblk_x;
 330     uint32_t                    nblk_y;
 331     uint32_t                    nblk_z;
 332     uint32_t                    pitch_bytes;
 333     uint32_t                    mode;
 334     uint64_t                    dcc_offset;
 335 };
 336
 337 struct radeon_surf {
 338     /* These are inputs to the calculator. */
 339     uint32_t                    npix_x;
 340     uint32_t                    npix_y;
 341     uint32_t                    npix_z;
 342     uint32_t                    blk_w;
 343     uint32_t                    blk_h;
 344     uint32_t                    blk_d;
 345     uint32_t                    array_size;
 346     uint32_t                    last_level;
 347     uint32_t                    bpe;
 348     uint32_t                    nsamples;
 349     uint32_t                    flags;
 350
 351     /* These are return values. Some of them can be set by the caller, but
 352      * they will be treated as hints (e.g. bankw, bankh) and might be
 353      * changed by the calculator.
 354      */
 355     uint64_t                    bo_size;
 356     uint64_t                    bo_alignment;
 357     /* This applies to EG and later. */
 358     uint32_t                    bankw;
 359     uint32_t                    bankh;
 360     uint32_t                    mtilea;
 361     uint32_t                    tile_split;
 362     uint32_t                    stencil_tile_split;
 363     uint64_t                    stencil_offset;
 364     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 365     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 366     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 367     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 368     uint32_t                    pipe_config;
 369     uint32_t                    num_banks;
 370
 371     uint64_t                    dcc_size;
 372     uint64_t                    dcc_alignment;
 373 };
 374
 375 struct radeon_bo_list_item {
 376     struct pb_buffer *buf;
 377     uint64_t vm_address;
 378     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 379 };
 380
 381 struct radeon_winsys {
 382     /**
 383      * The screen object this winsys was created for
 384      */
 385     struct pipe_screen *screen;
 386
 387     /**
 388      * Decrement the winsys reference count.
 389      *
 390      * \param ws  The winsys this function is called for.
 391      * \return    True if the winsys and screen should be destroyed.
 392      */
 393     bool (*unref)(struct radeon_winsys *ws);
 394
 395     /**
 396      * Destroy this winsys.
 397      *
 398      * \param ws        The winsys this function is called from.
 399      */
 400     void (*destroy)(struct radeon_winsys *ws);
 401
 402     /**
 403      * Query an info structure from winsys.
 404      *
 405      * \param ws        The winsys this function is called from.
 406      * \param info      Return structure
 407      */
 408     void (*query_info)(struct radeon_winsys *ws,
 409                        struct radeon_info *info);
 410
 411     /**************************************************************************
 412      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 413      *
 414      * Remember that gallium gets to choose the interface it needs, and the
 415      * window systems must then implement that interface (rather than the
 416      * other way around...).
 417      *************************************************************************/
 418
 419     /**
 420      * Create a buffer object.
 421      *
 422      * \param ws        The winsys this function is called from.
 423      * \param size      The size to allocate.
 424      * \param alignment An alignment of the buffer in memory.
 425      * \param use_reusable_pool Whether the cache buffer manager should be used.
 426      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 427      * \return          The created buffer object.
 428      */
 429     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 430                                        unsigned size,
 431                                        unsigned alignment,
 432                                        boolean use_reusable_pool,
 433                                        enum radeon_bo_domain domain,
 434                                        enum radeon_bo_flag flags);
 435
 436     /**
 437      * Map the entire data store of a buffer object into the client's address
 438      * space.
 439      *
 440      * \param buf       A winsys buffer object to map.
 441      * \param cs        A command stream to flush if the buffer is referenced by it.
 442      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 443      * \return          The pointer at the beginning of the buffer.
 444      */
 445     void *(*buffer_map)(struct pb_buffer *buf,
 446                         struct radeon_winsys_cs *cs,
 447                         enum pipe_transfer_usage usage);
 448
 449     /**
 450      * Unmap a buffer object from the client's address space.
 451      *
 452      * \param buf       A winsys buffer object to unmap.
 453      */
 454     void (*buffer_unmap)(struct pb_buffer *buf);
 455
 456     /**
 457      * Wait for the buffer and return true if the buffer is not used
 458      * by the device.
 459      *
 460      * The timeout of 0 will only return the status.
 461      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 462      * is idle.
 463      */
 464     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 465                         enum radeon_bo_usage usage);
 466
 467     /**
 468      * Return tiling flags describing a memory layout of a buffer object.
 469      *
 470      * \param buf       A winsys buffer object to get the flags from.
 471      * \param macrotile A pointer to the return value of the microtile flag.
 472      * \param microtile A pointer to the return value of the macrotile flag.
 473      *
 474      * \note microtile and macrotile are not bitmasks!
 475      */
 476     void (*buffer_get_tiling)(struct pb_buffer *buf,
 477                               enum radeon_bo_layout *microtile,
 478                               enum radeon_bo_layout *macrotile,
 479                               unsigned *bankw, unsigned *bankh,
 480                               unsigned *tile_split,
 481                               unsigned *stencil_tile_split,
 482                               unsigned *mtilea,
 483                               bool *scanout);
 484
 485     /**
 486      * Set tiling flags describing a memory layout of a buffer object.
 487      *
 488      * \param buf       A winsys buffer object to set the flags for.
 489      * \param cs        A command stream to flush if the buffer is referenced by it.
 490      * \param macrotile A macrotile flag.
 491      * \param microtile A microtile flag.
 492      * \param stride    A stride of the buffer in bytes, for texturing.
 493      *
 494      * \note microtile and macrotile are not bitmasks!
 495      */
 496     void (*buffer_set_tiling)(struct pb_buffer *buf,
 497                               struct radeon_winsys_cs *rcs,
 498                               enum radeon_bo_layout microtile,
 499                               enum radeon_bo_layout macrotile,
 500                               unsigned pipe_config,
 501                               unsigned bankw, unsigned bankh,
 502                               unsigned tile_split,
 503                               unsigned stencil_tile_split,
 504                               unsigned mtilea, unsigned num_banks,
 505                               unsigned stride,
 506                               bool scanout);
 507
 508     /**
 509      * Get a winsys buffer from a winsys handle. The internal structure
 510      * of the handle is platform-specific and only a winsys should access it.
 511      *
 512      * \param ws        The winsys this function is called from.
 513      * \param whandle   A winsys handle pointer as was received from a state
 514      *                  tracker.
 515      * \param stride    The returned buffer stride in bytes.
 516      */
 517     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 518                                             struct winsys_handle *whandle,
 519                                             unsigned *stride);
 520
 521     /**
 522      * Get a winsys buffer from a user pointer. The resulting buffer can't
 523      * be exported. Both pointer and size must be page aligned.
 524      *
 525      * \param ws        The winsys this function is called from.
 526      * \param pointer   User pointer to turn into a buffer object.
 527      * \param Size      Size in bytes for the new buffer.
 528      */
 529     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 530                                          void *pointer, unsigned size);
 531
 532     /**
 533      * Get a winsys handle from a winsys buffer. The internal structure
 534      * of the handle is platform-specific and only a winsys should access it.
 535      *
 536      * \param buf       A winsys buffer object to get the handle from.
 537      * \param whandle   A winsys handle pointer.
 538      * \param stride    A stride of the buffer in bytes, for texturing.
 539      * \return          TRUE on success.
 540      */
 541     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 542                                  unsigned stride,
 543                                  struct winsys_handle *whandle);
 544
 545     /**
 546      * Return the virtual address of a buffer.
 547      *
 548      * \param buf       A winsys buffer object
 549      * \return          virtual address
 550      */
 551     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 552
 553     /**
 554      * Query the initial placement of the buffer from the kernel driver.
 555      */
 556     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 557
 558     /**************************************************************************
 559      * Command submission.
 560      *
 561      * Each pipe context should create its own command stream and submit
 562      * commands independently of other contexts.
 563      *************************************************************************/
 564
 565     /**
 566      * Create a command submission context.
 567      * Various command streams can be submitted to the same context.
 568      */
 569     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 570
 571     /**
 572      * Destroy a context.
 573      */
 574     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 575
 576     /**
 577      * Query a GPU reset status.
 578      */
 579     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 580
 581     /**
 582      * Create a command stream.
 583      *
 584      * \param ctx       The submission context
 585      * \param ring_type The ring type (GFX, DMA, UVD)
 586      * \param flush     Flush callback function associated with the command stream.
 587      * \param user      User pointer that will be passed to the flush callback.
 588      * \param trace_buf Trace buffer when tracing is enabled
 589      */
 590     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 591                                           enum ring_type ring_type,
 592                                           void (*flush)(void *ctx, unsigned flags,
 593                                                         struct pipe_fence_handle **fence),
 594                                           void *flush_ctx,
 595                                           struct pb_buffer *trace_buf);
 596
 597     /**
 598      * Destroy a command stream.
 599      *
 600      * \param cs        A command stream to destroy.
 601      */
 602     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 603
 604     /**
 605      * Add a buffer. Each buffer used by a CS must be added using this function.
 606      *
 607      * \param cs      Command stream
 608      * \param buf     Buffer
 609      * \param usage   Whether the buffer is used for read and/or write.
 610      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 611      * \param priority  A higher number means a greater chance of being
 612      *                  placed in the requested domain. 15 is the maximum.
 613      * \return Buffer index.
 614      */
 615     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 616                              struct pb_buffer *buf,
 617                              enum radeon_bo_usage usage,
 618                              enum radeon_bo_domain domain,
 619                              enum radeon_bo_priority priority);
 620
 621     /**
 622      * Return the index of an already-added buffer.
 623      *
 624      * \param cs        Command stream
 625      * \param buf       Buffer
 626      * \return          The buffer index, or -1 if the buffer has not been added.
 627      */
 628     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 629                             struct pb_buffer *buf);
 630
 631     /**
 632      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 633      * added so far. If the validation fails, all buffers which have
 634      * been added since the last call of cs_validate will be removed and
 635      * the CS will be flushed (provided there are still any buffers).
 636      *
 637      * \param cs        A command stream to validate.
 638      */
 639     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 640
 641     /**
 642      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 643      * added so far.
 644      *
 645      * \param cs        A command stream to validate.
 646      * \param vram      VRAM memory size pending to be use
 647      * \param gtt       GTT memory size pending to be use
 648      */
 649     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 650
 651     /**
 652      * Return the buffer list.
 653      *
 654      * \param cs    Command stream
 655      * \param list  Returned buffer list. Set to NULL to query the count only.
 656      * \return      The buffer count.
 657      */
 658     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 659                                    struct radeon_bo_list_item *list);
 660
 661     /**
 662      * Flush a command stream.
 663      *
 664      * \param cs          A command stream to flush.
 665      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 666      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 667      *                    after the CS and is returned through this parameter.
 668      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 669      */
 670     void (*cs_flush)(struct radeon_winsys_cs *cs,
 671                      unsigned flags,
 672                      struct pipe_fence_handle **fence,
 673                      uint32_t cs_trace_id);
 674
 675     /**
 676      * Return TRUE if a buffer is referenced by a command stream.
 677      *
 678      * \param cs        A command stream.
 679      * \param buf       A winsys buffer.
 680      */
 681     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 682                                        struct pb_buffer *buf,
 683                                        enum radeon_bo_usage usage);
 684
 685     /**
 686      * Request access to a feature for a command stream.
 687      *
 688      * \param cs        A command stream.
 689      * \param fid       Feature ID, one of RADEON_FID_*
 690      * \param enable    Whether to enable or disable the feature.
 691      */
 692     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 693                                   enum radeon_feature_id fid,
 694                                   boolean enable);
 695      /**
 696       * Make sure all asynchronous flush of the cs have completed
 697       *
 698       * \param cs        A command stream.
 699       */
 700     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 701
 702     /**
 703      * Wait for the fence and return true if the fence has been signalled.
 704      * The timeout of 0 will only return the status.
 705      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 706      * is signalled.
 707      */
 708     bool (*fence_wait)(struct radeon_winsys *ws,
 709                        struct pipe_fence_handle *fence,
 710                        uint64_t timeout);
 711
 712     /**
 713      * Reference counting for fences.
 714      */
 715     void (*fence_reference)(struct pipe_fence_handle **dst,
 716                             struct pipe_fence_handle *src);
 717
 718     /**
 719      * Initialize surface
 720      *
 721      * \param ws        The winsys this function is called from.
 722      * \param surf      Surface structure ptr
 723      */
 724     int (*surface_init)(struct radeon_winsys *ws,
 725                         struct radeon_surf *surf);
 726
 727     /**
 728      * Find best values for a surface
 729      *
 730      * \param ws        The winsys this function is called from.
 731      * \param surf      Surface structure ptr
 732      */
 733     int (*surface_best)(struct radeon_winsys *ws,
 734                         struct radeon_surf *surf);
 735
 736     uint64_t (*query_value)(struct radeon_winsys *ws,
 737                             enum radeon_value_id value);
 738
 739     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 740                            unsigned num_registers, uint32_t *out);
 741 };
 742
 743
 744 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 745 {
 746     cs->buf[cs->cdw++] = value;
 747 }
 748
 749 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 750                                      const uint32_t *values, unsigned count)
 751 {
 752     memcpy(cs->buf+cs->cdw, values, count * 4);
 753     cs->cdw += count;
 754 }
 755
 756 #endif