src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  * Copyright 2018 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  25
  26 #ifndef RADEON_WINSYS_H
  27 #define RADEON_WINSYS_H
  28
  29 /* The public winsys interface header for the radeon driver. */
  30
  31 /* Whether the next IB can start immediately and not wait for draws and
  32  * dispatches from the current IB to finish. */
  33 #define RADEON_FLUSH_START_NEXT_GFX_IB_NOW      (1u << 31)
  34
  35 #define RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW \
  36         (PIPE_FLUSH_ASYNC | RADEON_FLUSH_START_NEXT_GFX_IB_NOW)
  37
  38 #include "pipebuffer/pb_buffer.h"
  39
  40 #include "amd/common/ac_gpu_info.h"
  41 #include "amd/common/ac_surface.h"
  42
  43 /* Tiling flags. */
  44 enum radeon_bo_layout {
  45     RADEON_LAYOUT_LINEAR = 0,
  46     RADEON_LAYOUT_TILED,
  47     RADEON_LAYOUT_SQUARETILED,
  48
  49     RADEON_LAYOUT_UNKNOWN
  50 };
  51
  52 enum radeon_bo_domain { /* bitfield */
  53     RADEON_DOMAIN_GTT  = 2,
  54     RADEON_DOMAIN_VRAM = 4,
  55     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
  56     RADEON_DOMAIN_GDS = 8,
  57     RADEON_DOMAIN_OA = 16,
  58 };
  59
  60 enum radeon_bo_flag { /* bitfield */
  61     RADEON_FLAG_GTT_WC =        (1 << 0),
  62     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  63     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  64     RADEON_FLAG_SPARSE =        (1 << 3),
  65     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  66     RADEON_FLAG_READ_ONLY =     (1 << 5),
  67     RADEON_FLAG_32BIT =    (1 << 6),
  68 };
  69
  70 enum radeon_bo_usage { /* bitfield */
  71     RADEON_USAGE_READ = 2,
  72     RADEON_USAGE_WRITE = 4,
  73     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
  74
  75     /* The winsys ensures that the CS submission will be scheduled after
  76      * previously flushed CSs referencing this BO in a conflicting way.
  77      */
  78     RADEON_USAGE_SYNCHRONIZED = 8
  79 };
  80
  81 enum radeon_transfer_flags {
  82    /* Indicates that the caller will unmap the buffer.
  83     *
  84     * Not unmapping buffers is an important performance optimization for
  85     * OpenGL (avoids kernel overhead for frequently mapped buffers).
  86     */
  87    RADEON_TRANSFER_TEMPORARY = (PIPE_TRANSFER_DRV_PRV << 0),
  88 };
  89
  90 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
  91
  92 enum ring_type {
  93     RING_GFX = 0,
  94     RING_COMPUTE,
  95     RING_DMA,
  96     RING_UVD,
  97     RING_VCE,
  98     RING_UVD_ENC,
  99     RING_VCN_DEC,
 100     RING_VCN_ENC,
 101     RING_VCN_JPEG,
 102     RING_LAST,
 103 };
 104
 105 enum radeon_value_id {
 106     RADEON_REQUESTED_VRAM_MEMORY,
 107     RADEON_REQUESTED_GTT_MEMORY,
 108     RADEON_MAPPED_VRAM,
 109     RADEON_MAPPED_GTT,
 110     RADEON_BUFFER_WAIT_TIME_NS,
 111     RADEON_NUM_MAPPED_BUFFERS,
 112     RADEON_TIMESTAMP,
 113     RADEON_NUM_GFX_IBS,
 114     RADEON_NUM_SDMA_IBS,
 115     RADEON_GFX_BO_LIST_COUNTER, /* number of BOs submitted in gfx IBs */
 116     RADEON_GFX_IB_SIZE_COUNTER,
 117     RADEON_NUM_BYTES_MOVED,
 118     RADEON_NUM_EVICTIONS,
 119     RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
 120     RADEON_VRAM_USAGE,
 121     RADEON_VRAM_VIS_USAGE,
 122     RADEON_GTT_USAGE,
 123     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 124     RADEON_CURRENT_SCLK,
 125     RADEON_CURRENT_MCLK,
 126     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 127     RADEON_CS_THREAD_TIME,
 128 };
 129
 130 enum radeon_bo_priority {
 131     /* Each group of two has the same priority. */
 132     RADEON_PRIO_FENCE = 0,
 133     RADEON_PRIO_TRACE,
 134
 135     RADEON_PRIO_SO_FILLED_SIZE = 2,
 136     RADEON_PRIO_QUERY,
 137
 138     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 139     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 140
 141     RADEON_PRIO_DRAW_INDIRECT = 6,
 142     RADEON_PRIO_INDEX_BUFFER,
 143
 144     RADEON_PRIO_CP_DMA = 8,
 145     RADEON_PRIO_BORDER_COLORS,
 146
 147     RADEON_PRIO_CONST_BUFFER = 10,
 148     RADEON_PRIO_DESCRIPTORS,
 149
 150     RADEON_PRIO_SAMPLER_BUFFER = 12,
 151     RADEON_PRIO_VERTEX_BUFFER,
 152
 153     RADEON_PRIO_SHADER_RW_BUFFER = 14,
 154     RADEON_PRIO_COMPUTE_GLOBAL,
 155
 156     RADEON_PRIO_SAMPLER_TEXTURE = 16,
 157     RADEON_PRIO_SHADER_RW_IMAGE,
 158
 159     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
 160     RADEON_PRIO_COLOR_BUFFER,
 161
 162     RADEON_PRIO_DEPTH_BUFFER = 20,
 163
 164     RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
 165
 166     RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
 167
 168     RADEON_PRIO_SEPARATE_META = 26,
 169     RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
 170
 171     RADEON_PRIO_SHADER_RINGS = 28,
 172
 173     RADEON_PRIO_SCRATCH_BUFFER = 30,
 174     /* 31 is the maximum value */
 175 };
 176
 177 struct winsys_handle;
 178 struct radeon_winsys_ctx;
 179
 180 struct radeon_cmdbuf_chunk {
 181     unsigned cdw;  /* Number of used dwords. */
 182     unsigned max_dw; /* Maximum number of dwords. */
 183     uint32_t *buf; /* The base pointer of the chunk. */
 184 };
 185
 186 struct radeon_cmdbuf {
 187     struct radeon_cmdbuf_chunk current;
 188     struct radeon_cmdbuf_chunk *prev;
 189     unsigned                      num_prev; /* Number of previous chunks. */
 190     unsigned                      max_prev; /* Space in array pointed to by prev. */
 191     unsigned                      prev_dw; /* Total number of dwords in previous chunks. */
 192
 193     /* Memory usage of the buffer list. These are always 0 for preamble IBs. */
 194     uint64_t                      used_vram;
 195     uint64_t                      used_gart;
 196 };
 197
 198 /* Tiling info for display code, DRI sharing, and other data. */
 199 struct radeon_bo_metadata {
 200     /* Tiling flags describing the texture layout for display code
 201      * and DRI sharing.
 202      */
 203     union {
 204         struct {
 205             enum radeon_bo_layout   microtile;
 206             enum radeon_bo_layout   macrotile;
 207             unsigned                pipe_config;
 208             unsigned                bankw;
 209             unsigned                bankh;
 210             unsigned                tile_split;
 211             unsigned                mtilea;
 212             unsigned                num_banks;
 213             unsigned                stride;
 214             bool                    scanout;
 215         } legacy;
 216
 217         struct {
 218             /* surface flags */
 219             unsigned swizzle_mode:5;
 220
 221             /* DCC flags */
 222             /* [31:8]: max offset = 4GB - 256; 0 = DCC disabled */
 223             unsigned dcc_offset_256B:24;
 224             unsigned dcc_pitch_max:14;   /* (mip chain pitch - 1) for DCN */
 225             unsigned dcc_independent_64B:1;
 226         } gfx9;
 227     } u;
 228
 229     /* Additional metadata associated with the buffer, in bytes.
 230      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 231      * Supported by amdgpu only.
 232      */
 233     uint32_t                size_metadata;
 234     uint32_t                metadata[64];
 235 };
 236
 237 enum radeon_feature_id {
 238     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 239     RADEON_FID_R300_CMASK_ACCESS,
 240 };
 241
 242 struct radeon_bo_list_item {
 243     uint64_t bo_size;
 244     uint64_t vm_address;
 245     uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 246 };
 247
 248 struct radeon_winsys {
 249     /**
 250      * The screen object this winsys was created for
 251      */
 252     struct pipe_screen *screen;
 253
 254     /**
 255      * Decrement the winsys reference count.
 256      *
 257      * \param ws  The winsys this function is called for.
 258      * \return    True if the winsys and screen should be destroyed.
 259      */
 260     bool (*unref)(struct radeon_winsys *ws);
 261
 262     /**
 263      * Destroy this winsys.
 264      *
 265      * \param ws        The winsys this function is called from.
 266      */
 267     void (*destroy)(struct radeon_winsys *ws);
 268
 269     /**
 270      * Query an info structure from winsys.
 271      *
 272      * \param ws        The winsys this function is called from.
 273      * \param info      Return structure
 274      */
 275     void (*query_info)(struct radeon_winsys *ws,
 276                        struct radeon_info *info);
 277
 278     /**
 279      * A hint for the winsys that it should pin its execution threads to
 280      * a group of cores sharing a specific L3 cache if the CPU has multiple
 281      * L3 caches. This is needed for good multithreading performance on
 282      * AMD Zen CPUs.
 283      */
 284     void (*pin_threads_to_L3_cache)(struct radeon_winsys *ws, unsigned cache);
 285
 286     /**************************************************************************
 287      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 288      *
 289      * Remember that gallium gets to choose the interface it needs, and the
 290      * window systems must then implement that interface (rather than the
 291      * other way around...).
 292      *************************************************************************/
 293
 294     /**
 295      * Create a buffer object.
 296      *
 297      * \param ws        The winsys this function is called from.
 298      * \param size      The size to allocate.
 299      * \param alignment An alignment of the buffer in memory.
 300      * \param use_reusable_pool Whether the cache buffer manager should be used.
 301      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 302      * \return          The created buffer object.
 303      */
 304     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 305                                        uint64_t size,
 306                                        unsigned alignment,
 307                                        enum radeon_bo_domain domain,
 308                                        enum radeon_bo_flag flags);
 309
 310     /**
 311      * Map the entire data store of a buffer object into the client's address
 312      * space.
 313      *
 314      * Callers are expected to unmap buffers again if and only if the
 315      * RADEON_TRANSFER_TEMPORARY flag is set in \p usage.
 316      *
 317      * \param buf       A winsys buffer object to map.
 318      * \param cs        A command stream to flush if the buffer is referenced by it.
 319      * \param usage     A bitmask of the PIPE_TRANSFER_* and RADEON_TRANSFER_* flags.
 320      * \return          The pointer at the beginning of the buffer.
 321      */
 322     void *(*buffer_map)(struct pb_buffer *buf,
 323                         struct radeon_cmdbuf *cs,
 324                         enum pipe_transfer_usage usage);
 325
 326     /**
 327      * Unmap a buffer object from the client's address space.
 328      *
 329      * \param buf       A winsys buffer object to unmap.
 330      */
 331     void (*buffer_unmap)(struct pb_buffer *buf);
 332
 333     /**
 334      * Wait for the buffer and return true if the buffer is not used
 335      * by the device.
 336      *
 337      * The timeout of 0 will only return the status.
 338      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 339      * is idle.
 340      */
 341     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 342                         enum radeon_bo_usage usage);
 343
 344     /**
 345      * Return buffer metadata.
 346      * (tiling info for display code, DRI sharing, and other data)
 347      *
 348      * \param buf       A winsys buffer object to get the flags from.
 349      * \param md        Metadata
 350      */
 351     void (*buffer_get_metadata)(struct pb_buffer *buf,
 352                                 struct radeon_bo_metadata *md);
 353
 354     /**
 355      * Set buffer metadata.
 356      * (tiling info for display code, DRI sharing, and other data)
 357      *
 358      * \param buf       A winsys buffer object to set the flags for.
 359      * \param md        Metadata
 360      */
 361     void (*buffer_set_metadata)(struct pb_buffer *buf,
 362                                 struct radeon_bo_metadata *md);
 363
 364     /**
 365      * Get a winsys buffer from a winsys handle. The internal structure
 366      * of the handle is platform-specific and only a winsys should access it.
 367      *
 368      * \param ws        The winsys this function is called from.
 369      * \param whandle   A winsys handle pointer as was received from a state
 370      *                  tracker.
 371      * \param stride    The returned buffer stride in bytes.
 372      */
 373     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 374                                             struct winsys_handle *whandle,
 375                                             unsigned vm_alignment,
 376                                             unsigned *stride, unsigned *offset);
 377
 378     /**
 379      * Get a winsys buffer from a user pointer. The resulting buffer can't
 380      * be exported. Both pointer and size must be page aligned.
 381      *
 382      * \param ws        The winsys this function is called from.
 383      * \param pointer   User pointer to turn into a buffer object.
 384      * \param Size      Size in bytes for the new buffer.
 385      */
 386     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 387                                          void *pointer, uint64_t size);
 388
 389     /**
 390      * Whether the buffer was created from a user pointer.
 391      *
 392      * \param buf       A winsys buffer object
 393      * \return          whether \p buf was created via buffer_from_ptr
 394      */
 395     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 396
 397     /** Whether the buffer was suballocated. */
 398     bool (*buffer_is_suballocated)(struct pb_buffer *buf);
 399
 400     /**
 401      * Get a winsys handle from a winsys buffer. The internal structure
 402      * of the handle is platform-specific and only a winsys should access it.
 403      *
 404      * \param buf       A winsys buffer object to get the handle from.
 405      * \param whandle   A winsys handle pointer.
 406      * \param stride    A stride of the buffer in bytes, for texturing.
 407      * \return          true on success.
 408      */
 409     bool (*buffer_get_handle)(struct pb_buffer *buf,
 410                               unsigned stride, unsigned offset,
 411                               unsigned slice_size,
 412                               struct winsys_handle *whandle);
 413
 414     /**
 415      * Change the commitment of a (64KB-page aligned) region of the given
 416      * sparse buffer.
 417      *
 418      * \warning There is no automatic synchronization with command submission.
 419      *
 420      * \note Only implemented by the amdgpu winsys.
 421      *
 422      * \return false on out of memory or other failure, true on success.
 423      */
 424     bool (*buffer_commit)(struct pb_buffer *buf,
 425                           uint64_t offset, uint64_t size,
 426                           bool commit);
 427
 428     /**
 429      * Return the virtual address of a buffer.
 430      *
 431      * When virtual memory is not in use, this is the offset relative to the
 432      * relocation base (non-zero for sub-allocated buffers).
 433      *
 434      * \param buf       A winsys buffer object
 435      * \return          virtual address
 436      */
 437     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 438
 439     /**
 440      * Return the offset of this buffer relative to the relocation base.
 441      * This is only non-zero for sub-allocated buffers.
 442      *
 443      * This is only supported in the radeon winsys, since amdgpu uses virtual
 444      * addresses in submissions even for the video engines.
 445      *
 446      * \param buf      A winsys buffer object
 447      * \return         the offset for relocations
 448      */
 449     unsigned (*buffer_get_reloc_offset)(struct pb_buffer *buf);
 450
 451     /**
 452      * Query the initial placement of the buffer from the kernel driver.
 453      */
 454     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 455
 456     /**************************************************************************
 457      * Command submission.
 458      *
 459      * Each pipe context should create its own command stream and submit
 460      * commands independently of other contexts.
 461      *************************************************************************/
 462
 463     /**
 464      * Create a command submission context.
 465      * Various command streams can be submitted to the same context.
 466      */
 467     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 468
 469     /**
 470      * Destroy a context.
 471      */
 472     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 473
 474     /**
 475      * Query a GPU reset status.
 476      */
 477     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 478
 479     /**
 480      * Create a command stream.
 481      *
 482      * \param ctx       The submission context
 483      * \param ring_type The ring type (GFX, DMA, UVD)
 484      * \param flush     Flush callback function associated with the command stream.
 485      * \param user      User pointer that will be passed to the flush callback.
 486      */
 487     struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx,
 488                                        enum ring_type ring_type,
 489                                        void (*flush)(void *ctx, unsigned flags,
 490                                                      struct pipe_fence_handle **fence),
 491                                        void *flush_ctx,
 492                                        bool stop_exec_on_failure);
 493
 494     /**
 495      * Destroy a command stream.
 496      *
 497      * \param cs        A command stream to destroy.
 498      */
 499     void (*cs_destroy)(struct radeon_cmdbuf *cs);
 500
 501     /**
 502      * Add a buffer. Each buffer used by a CS must be added using this function.
 503      *
 504      * \param cs      Command stream
 505      * \param buf     Buffer
 506      * \param usage   Whether the buffer is used for read and/or write.
 507      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 508      * \param priority  A higher number means a greater chance of being
 509      *                  placed in the requested domain. 15 is the maximum.
 510      * \return Buffer index.
 511      */
 512     unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 513                              struct pb_buffer *buf,
 514                              enum radeon_bo_usage usage,
 515                              enum radeon_bo_domain domain,
 516                              enum radeon_bo_priority priority);
 517
 518     /**
 519      * Return the index of an already-added buffer.
 520      *
 521      * Not supported on amdgpu. Drivers with GPUVM should not care about
 522      * buffer indices.
 523      *
 524      * \param cs        Command stream
 525      * \param buf       Buffer
 526      * \return          The buffer index, or -1 if the buffer has not been added.
 527      */
 528     int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs,
 529                             struct pb_buffer *buf);
 530
 531     /**
 532      * Return true if there is enough memory in VRAM and GTT for the buffers
 533      * added so far. If the validation fails, all buffers which have
 534      * been added since the last call of cs_validate will be removed and
 535      * the CS will be flushed (provided there are still any buffers).
 536      *
 537      * \param cs        A command stream to validate.
 538      */
 539     bool (*cs_validate)(struct radeon_cmdbuf *cs);
 540
 541     /**
 542      * Check whether the given number of dwords is available in the IB.
 543      * Optionally chain a new chunk of the IB if necessary and supported.
 544      *
 545      * \param cs        A command stream.
 546      * \param dw        Number of CS dwords requested by the caller.
 547      */
 548     bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw);
 549
 550     /**
 551      * Return the buffer list.
 552      *
 553      * This is the buffer list as passed to the kernel, i.e. it only contains
 554      * the parent buffers of sub-allocated buffers.
 555      *
 556      * \param cs    Command stream
 557      * \param list  Returned buffer list. Set to NULL to query the count only.
 558      * \return      The buffer count.
 559      */
 560     unsigned (*cs_get_buffer_list)(struct radeon_cmdbuf *cs,
 561                                    struct radeon_bo_list_item *list);
 562
 563     /**
 564      * Flush a command stream.
 565      *
 566      * \param cs          A command stream to flush.
 567      * \param flags,      PIPE_FLUSH_* flags.
 568      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 569      *                    after the CS and is returned through this parameter.
 570      * \return Negative POSIX error code or 0 for success.
 571      *         Asynchronous submissions never return an error.
 572      */
 573     int (*cs_flush)(struct radeon_cmdbuf *cs,
 574                     unsigned flags,
 575                     struct pipe_fence_handle **fence);
 576
 577     /**
 578      * Create a fence before the CS is flushed.
 579      * The user must flush manually to complete the initializaton of the fence.
 580      *
 581      * The fence must not be used for anything except \ref cs_add_fence_dependency
 582      * before the flush.
 583      */
 584     struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_cmdbuf *cs);
 585
 586     /**
 587      * Return true if a buffer is referenced by a command stream.
 588      *
 589      * \param cs        A command stream.
 590      * \param buf       A winsys buffer.
 591      */
 592     bool (*cs_is_buffer_referenced)(struct radeon_cmdbuf *cs,
 593                                     struct pb_buffer *buf,
 594                                     enum radeon_bo_usage usage);
 595
 596     /**
 597      * Request access to a feature for a command stream.
 598      *
 599      * \param cs        A command stream.
 600      * \param fid       Feature ID, one of RADEON_FID_*
 601      * \param enable    Whether to enable or disable the feature.
 602      */
 603     bool (*cs_request_feature)(struct radeon_cmdbuf *cs,
 604                                enum radeon_feature_id fid,
 605                                bool enable);
 606      /**
 607       * Make sure all asynchronous flush of the cs have completed
 608       *
 609       * \param cs        A command stream.
 610       */
 611     void (*cs_sync_flush)(struct radeon_cmdbuf *cs);
 612
 613     /**
 614      * Add a fence dependency to the CS, so that the CS will wait for
 615      * the fence before execution.
 616      */
 617     void (*cs_add_fence_dependency)(struct radeon_cmdbuf *cs,
 618                                     struct pipe_fence_handle *fence);
 619
 620     /**
 621      * Signal a syncobj when the CS finishes execution.
 622      */
 623     void (*cs_add_syncobj_signal)(struct radeon_cmdbuf *cs,
 624                                   struct pipe_fence_handle *fence);
 625
 626     /**
 627      * Wait for the fence and return true if the fence has been signalled.
 628      * The timeout of 0 will only return the status.
 629      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 630      * is signalled.
 631      */
 632     bool (*fence_wait)(struct radeon_winsys *ws,
 633                        struct pipe_fence_handle *fence,
 634                        uint64_t timeout);
 635
 636     /**
 637      * Reference counting for fences.
 638      */
 639     void (*fence_reference)(struct pipe_fence_handle **dst,
 640                             struct pipe_fence_handle *src);
 641
 642     /**
 643      * Create a new fence object corresponding to the given syncobj fd.
 644      */
 645     struct pipe_fence_handle *(*fence_import_syncobj)(struct radeon_winsys *ws,
 646                                                       int fd);
 647
 648     /**
 649      * Create a new fence object corresponding to the given sync_file.
 650      */
 651     struct pipe_fence_handle *(*fence_import_sync_file)(struct radeon_winsys *ws,
 652                                                         int fd);
 653
 654     /**
 655      * Return a sync_file FD corresponding to the given fence object.
 656      */
 657     int (*fence_export_sync_file)(struct radeon_winsys *ws,
 658                                   struct pipe_fence_handle *fence);
 659
 660     /**
 661      * Return a sync file FD that is already signalled.
 662      */
 663     int (*export_signalled_sync_file)(struct radeon_winsys *ws);
 664
 665     /**
 666      * Initialize surface
 667      *
 668      * \param ws        The winsys this function is called from.
 669      * \param tex       Input texture description
 670      * \param flags     Bitmask of RADEON_SURF_* flags
 671      * \param bpe       Bytes per pixel, it can be different for Z buffers.
 672      * \param mode      Preferred tile mode. (linear, 1D, or 2D)
 673      * \param surf      Output structure
 674      */
 675     int (*surface_init)(struct radeon_winsys *ws,
 676                         const struct pipe_resource *tex,
 677                         unsigned flags, unsigned bpe,
 678                         enum radeon_surf_mode mode,
 679                         struct radeon_surf *surf);
 680
 681     uint64_t (*query_value)(struct radeon_winsys *ws,
 682                             enum radeon_value_id value);
 683
 684     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 685                            unsigned num_registers, uint32_t *out);
 686
 687     const char* (*get_chip_name)(struct radeon_winsys *ws);
 688 };
 689
 690 static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
 691 {
 692     return cs && (cs->prev_dw + cs->current.cdw > num_dw);
 693 }
 694
 695 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 696 {
 697     cs->current.buf[cs->current.cdw++] = value;
 698 }
 699
 700 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 701                                      const uint32_t *values, unsigned count)
 702 {
 703     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
 704     cs->current.cdw += count;
 705 }
 706
 707 enum radeon_heap {
 708     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
 709     RADEON_HEAP_VRAM_READ_ONLY,
 710     RADEON_HEAP_VRAM_READ_ONLY_32BIT,
 711     RADEON_HEAP_VRAM_32BIT,
 712     RADEON_HEAP_VRAM,
 713     RADEON_HEAP_GTT_WC,
 714     RADEON_HEAP_GTT_WC_READ_ONLY,
 715     RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
 716     RADEON_HEAP_GTT_WC_32BIT,
 717     RADEON_HEAP_GTT,
 718     RADEON_MAX_SLAB_HEAPS,
 719     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 720 };
 721
 722 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 723 {
 724     switch (heap) {
 725     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 726     case RADEON_HEAP_VRAM_READ_ONLY:
 727     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 728     case RADEON_HEAP_VRAM_32BIT:
 729     case RADEON_HEAP_VRAM:
 730         return RADEON_DOMAIN_VRAM;
 731     case RADEON_HEAP_GTT_WC:
 732     case RADEON_HEAP_GTT_WC_READ_ONLY:
 733     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 734     case RADEON_HEAP_GTT_WC_32BIT:
 735     case RADEON_HEAP_GTT:
 736         return RADEON_DOMAIN_GTT;
 737     default:
 738         assert(0);
 739         return (enum radeon_bo_domain)0;
 740     }
 741 }
 742
 743 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 744 {
 745     unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING |
 746                      (heap != RADEON_HEAP_GTT ? RADEON_FLAG_GTT_WC : 0);
 747
 748     switch (heap) {
 749     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
 750         return flags |
 751                RADEON_FLAG_NO_CPU_ACCESS;
 752
 753     case RADEON_HEAP_VRAM_READ_ONLY:
 754     case RADEON_HEAP_GTT_WC_READ_ONLY:
 755         return flags |
 756                RADEON_FLAG_READ_ONLY;
 757
 758     case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
 759     case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
 760         return flags |
 761                RADEON_FLAG_READ_ONLY |
 762                RADEON_FLAG_32BIT;
 763
 764     case RADEON_HEAP_VRAM_32BIT:
 765     case RADEON_HEAP_GTT_WC_32BIT:
 766         return flags |
 767                RADEON_FLAG_32BIT;
 768
 769     case RADEON_HEAP_VRAM:
 770     case RADEON_HEAP_GTT_WC:
 771     case RADEON_HEAP_GTT:
 772     default:
 773         return flags;
 774     }
 775 }
 776
 777 /* Return the heap index for winsys allocators, or -1 on failure. */
 778 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 779                                         enum radeon_bo_flag flags)
 780 {
 781     /* VRAM implies WC (write combining) */
 782     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 783     /* NO_CPU_ACCESS implies VRAM only. */
 784     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 785
 786     /* Resources with interprocess sharing don't use any winsys allocators. */
 787     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
 788         return -1;
 789
 790     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
 791     if (flags & ~(RADEON_FLAG_GTT_WC |
 792                   RADEON_FLAG_NO_CPU_ACCESS |
 793                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
 794                   RADEON_FLAG_READ_ONLY |
 795                   RADEON_FLAG_32BIT))
 796         return -1;
 797
 798     switch (domain) {
 799     case RADEON_DOMAIN_VRAM:
 800         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
 801                          RADEON_FLAG_READ_ONLY |
 802                          RADEON_FLAG_32BIT)) {
 803         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 804         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
 805             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
 806             return -1;
 807         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
 808             assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
 809             return -1;
 810         case RADEON_FLAG_NO_CPU_ACCESS:
 811             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
 812         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 813             return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
 814         case RADEON_FLAG_READ_ONLY:
 815             return RADEON_HEAP_VRAM_READ_ONLY;
 816         case RADEON_FLAG_32BIT:
 817             return RADEON_HEAP_VRAM_32BIT;
 818         case 0:
 819             return RADEON_HEAP_VRAM;
 820         }
 821         break;
 822     case RADEON_DOMAIN_GTT:
 823         switch (flags & (RADEON_FLAG_GTT_WC |
 824                          RADEON_FLAG_READ_ONLY |
 825                          RADEON_FLAG_32BIT)) {
 826         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 827             return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
 828         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
 829             return RADEON_HEAP_GTT_WC_READ_ONLY;
 830         case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
 831             return RADEON_HEAP_GTT_WC_32BIT;
 832         case RADEON_FLAG_GTT_WC:
 833             return RADEON_HEAP_GTT_WC;
 834         case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
 835         case RADEON_FLAG_READ_ONLY:
 836             assert(!"READ_ONLY without WC is disallowed");
 837             return -1;
 838         case RADEON_FLAG_32BIT:
 839             assert(!"32BIT without WC is disallowed");
 840             return -1;
 841         case 0:
 842             return RADEON_HEAP_GTT;
 843         }
 844         break;
 845     default:
 846         break;
 847     }
 848     return -1;
 849 }
 850
 851 #endif