2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
24 #ifndef RADEON_WINSYS_H
25 #define RADEON_WINSYS_H
27 /* The public winsys interface header for the radeon driver. */
29 #include "pipebuffer/pb_buffer.h"
31 #include "amd/common/ac_gpu_info.h"
32 #include "amd/common/ac_surface.h"
34 #define RADEON_FLUSH_ASYNC (1 << 0)
35 #define RADEON_FLUSH_END_OF_FRAME (1 << 1)
38 enum radeon_bo_layout
{
39 RADEON_LAYOUT_LINEAR
= 0,
41 RADEON_LAYOUT_SQUARETILED
,
46 enum radeon_bo_domain
{ /* bitfield */
47 RADEON_DOMAIN_GTT
= 2,
48 RADEON_DOMAIN_VRAM
= 4,
49 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
52 enum radeon_bo_flag
{ /* bitfield */
53 RADEON_FLAG_GTT_WC
= (1 << 0),
54 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
55 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
56 RADEON_FLAG_HANDLE
= (1 << 3), /* the buffer must not be suballocated */
57 RADEON_FLAG_SPARSE
= (1 << 4),
60 enum radeon_bo_usage
{ /* bitfield */
61 RADEON_USAGE_READ
= 2,
62 RADEON_USAGE_WRITE
= 4,
63 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
,
65 /* The winsys ensures that the CS submission will be scheduled after
66 * previously flushed CSs referencing this BO in a conflicting way.
68 RADEON_USAGE_SYNCHRONIZED
= 8
71 #define RADEON_SPARSE_PAGE_SIZE (64 * 1024)
84 enum radeon_value_id
{
85 RADEON_REQUESTED_VRAM_MEMORY
,
86 RADEON_REQUESTED_GTT_MEMORY
,
89 RADEON_BUFFER_WAIT_TIME_NS
,
90 RADEON_NUM_MAPPED_BUFFERS
,
94 RADEON_NUM_BYTES_MOVED
,
96 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
98 RADEON_VRAM_VIS_USAGE
,
100 RADEON_GPU_TEMPERATURE
, /* DRM 2.42.0 */
103 RADEON_GPU_RESET_COUNTER
, /* DRM 2.43.0 */
104 RADEON_CS_THREAD_TIME
,
107 /* Each group of four has the same priority. */
108 enum radeon_bo_priority
{
109 RADEON_PRIO_FENCE
= 0,
111 RADEON_PRIO_SO_FILLED_SIZE
,
114 RADEON_PRIO_IB1
= 4, /* main IB submitted to the kernel */
115 RADEON_PRIO_IB2
, /* IB executed with INDIRECT_BUFFER */
116 RADEON_PRIO_DRAW_INDIRECT
,
117 RADEON_PRIO_INDEX_BUFFER
,
121 RADEON_PRIO_SDMA_BUFFER
,
122 RADEON_PRIO_SDMA_TEXTURE
,
124 RADEON_PRIO_CP_DMA
= 12,
126 RADEON_PRIO_CONST_BUFFER
= 16,
127 RADEON_PRIO_DESCRIPTORS
,
128 RADEON_PRIO_BORDER_COLORS
,
130 RADEON_PRIO_SAMPLER_BUFFER
= 20,
131 RADEON_PRIO_VERTEX_BUFFER
,
133 RADEON_PRIO_SHADER_RW_BUFFER
= 24,
134 RADEON_PRIO_COMPUTE_GLOBAL
,
136 RADEON_PRIO_SAMPLER_TEXTURE
= 28,
137 RADEON_PRIO_SHADER_RW_IMAGE
,
139 RADEON_PRIO_SAMPLER_TEXTURE_MSAA
= 32,
141 RADEON_PRIO_COLOR_BUFFER
= 36,
143 RADEON_PRIO_DEPTH_BUFFER
= 40,
145 RADEON_PRIO_COLOR_BUFFER_MSAA
= 44,
147 RADEON_PRIO_DEPTH_BUFFER_MSAA
= 48,
149 RADEON_PRIO_CMASK
= 52,
152 RADEON_PRIO_SHADER_BINARY
, /* the hw can't hide instruction cache misses */
154 RADEON_PRIO_SHADER_RINGS
= 56,
156 RADEON_PRIO_SCRATCH_BUFFER
= 60,
157 /* 63 is the maximum value */
160 struct winsys_handle
;
161 struct radeon_winsys_ctx
;
163 struct radeon_winsys_cs_chunk
{
164 unsigned cdw
; /* Number of used dwords. */
165 unsigned max_dw
; /* Maximum number of dwords. */
166 uint32_t *buf
; /* The base pointer of the chunk. */
169 struct radeon_winsys_cs
{
170 struct radeon_winsys_cs_chunk current
;
171 struct radeon_winsys_cs_chunk
*prev
;
172 unsigned num_prev
; /* Number of previous chunks. */
173 unsigned max_prev
; /* Space in array pointed to by prev. */
174 unsigned prev_dw
; /* Total number of dwords in previous chunks. */
176 /* Memory usage of the buffer list. These are always 0 for CE and preamble
182 /* Tiling info for display code, DRI sharing, and other data. */
183 struct radeon_bo_metadata
{
184 /* Tiling flags describing the texture layout for display code
189 enum radeon_bo_layout microtile
;
190 enum radeon_bo_layout macrotile
;
191 unsigned pipe_config
;
203 unsigned swizzle_mode
:5;
207 /* Additional metadata associated with the buffer, in bytes.
208 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
209 * Supported by amdgpu only.
211 uint32_t size_metadata
;
212 uint32_t metadata
[64];
215 enum radeon_feature_id
{
216 RADEON_FID_R300_HYPERZ_ACCESS
, /* ZMask + HiZ */
217 RADEON_FID_R300_CMASK_ACCESS
,
220 struct radeon_bo_list_item
{
223 uint64_t priority_usage
; /* mask of (1 << RADEON_PRIO_*) */
226 struct radeon_winsys
{
228 * The screen object this winsys was created for
230 struct pipe_screen
*screen
;
233 * Decrement the winsys reference count.
235 * \param ws The winsys this function is called for.
236 * \return True if the winsys and screen should be destroyed.
238 bool (*unref
)(struct radeon_winsys
*ws
);
241 * Destroy this winsys.
243 * \param ws The winsys this function is called from.
245 void (*destroy
)(struct radeon_winsys
*ws
);
248 * Query an info structure from winsys.
250 * \param ws The winsys this function is called from.
251 * \param info Return structure
253 void (*query_info
)(struct radeon_winsys
*ws
,
254 struct radeon_info
*info
);
256 /**************************************************************************
257 * Buffer management. Buffer attributes are mostly fixed over its lifetime.
259 * Remember that gallium gets to choose the interface it needs, and the
260 * window systems must then implement that interface (rather than the
261 * other way around...).
262 *************************************************************************/
265 * Create a buffer object.
267 * \param ws The winsys this function is called from.
268 * \param size The size to allocate.
269 * \param alignment An alignment of the buffer in memory.
270 * \param use_reusable_pool Whether the cache buffer manager should be used.
271 * \param domain A bitmask of the RADEON_DOMAIN_* flags.
272 * \return The created buffer object.
274 struct pb_buffer
*(*buffer_create
)(struct radeon_winsys
*ws
,
277 enum radeon_bo_domain domain
,
278 enum radeon_bo_flag flags
);
281 * Map the entire data store of a buffer object into the client's address
284 * \param buf A winsys buffer object to map.
285 * \param cs A command stream to flush if the buffer is referenced by it.
286 * \param usage A bitmask of the PIPE_TRANSFER_* flags.
287 * \return The pointer at the beginning of the buffer.
289 void *(*buffer_map
)(struct pb_buffer
*buf
,
290 struct radeon_winsys_cs
*cs
,
291 enum pipe_transfer_usage usage
);
294 * Unmap a buffer object from the client's address space.
296 * \param buf A winsys buffer object to unmap.
298 void (*buffer_unmap
)(struct pb_buffer
*buf
);
301 * Wait for the buffer and return true if the buffer is not used
304 * The timeout of 0 will only return the status.
305 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
308 bool (*buffer_wait
)(struct pb_buffer
*buf
, uint64_t timeout
,
309 enum radeon_bo_usage usage
);
312 * Return buffer metadata.
313 * (tiling info for display code, DRI sharing, and other data)
315 * \param buf A winsys buffer object to get the flags from.
318 void (*buffer_get_metadata
)(struct pb_buffer
*buf
,
319 struct radeon_bo_metadata
*md
);
322 * Set buffer metadata.
323 * (tiling info for display code, DRI sharing, and other data)
325 * \param buf A winsys buffer object to set the flags for.
328 void (*buffer_set_metadata
)(struct pb_buffer
*buf
,
329 struct radeon_bo_metadata
*md
);
332 * Get a winsys buffer from a winsys handle. The internal structure
333 * of the handle is platform-specific and only a winsys should access it.
335 * \param ws The winsys this function is called from.
336 * \param whandle A winsys handle pointer as was received from a state
338 * \param stride The returned buffer stride in bytes.
340 struct pb_buffer
*(*buffer_from_handle
)(struct radeon_winsys
*ws
,
341 struct winsys_handle
*whandle
,
342 unsigned *stride
, unsigned *offset
);
345 * Get a winsys buffer from a user pointer. The resulting buffer can't
346 * be exported. Both pointer and size must be page aligned.
348 * \param ws The winsys this function is called from.
349 * \param pointer User pointer to turn into a buffer object.
350 * \param Size Size in bytes for the new buffer.
352 struct pb_buffer
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
353 void *pointer
, uint64_t size
);
356 * Whether the buffer was created from a user pointer.
358 * \param buf A winsys buffer object
359 * \return whether \p buf was created via buffer_from_ptr
361 bool (*buffer_is_user_ptr
)(struct pb_buffer
*buf
);
364 * Get a winsys handle from a winsys buffer. The internal structure
365 * of the handle is platform-specific and only a winsys should access it.
367 * \param buf A winsys buffer object to get the handle from.
368 * \param whandle A winsys handle pointer.
369 * \param stride A stride of the buffer in bytes, for texturing.
370 * \return true on success.
372 bool (*buffer_get_handle
)(struct pb_buffer
*buf
,
373 unsigned stride
, unsigned offset
,
375 struct winsys_handle
*whandle
);
378 * Change the commitment of a (64KB-page aligned) region of the given
381 * \warning There is no automatic synchronization with command submission.
383 * \note Only implemented by the amdgpu winsys.
385 * \return false on out of memory or other failure, true on success.
387 bool (*buffer_commit
)(struct pb_buffer
*buf
,
388 uint64_t offset
, uint64_t size
,
392 * Return the virtual address of a buffer.
394 * When virtual memory is not in use, this is the offset relative to the
395 * relocation base (non-zero for sub-allocated buffers).
397 * \param buf A winsys buffer object
398 * \return virtual address
400 uint64_t (*buffer_get_virtual_address
)(struct pb_buffer
*buf
);
403 * Return the offset of this buffer relative to the relocation base.
404 * This is only non-zero for sub-allocated buffers.
406 * This is only supported in the radeon winsys, since amdgpu uses virtual
407 * addresses in submissions even for the video engines.
409 * \param buf A winsys buffer object
410 * \return the offset for relocations
412 unsigned (*buffer_get_reloc_offset
)(struct pb_buffer
*buf
);
415 * Query the initial placement of the buffer from the kernel driver.
417 enum radeon_bo_domain (*buffer_get_initial_domain
)(struct pb_buffer
*buf
);
419 /**************************************************************************
420 * Command submission.
422 * Each pipe context should create its own command stream and submit
423 * commands independently of other contexts.
424 *************************************************************************/
427 * Create a command submission context.
428 * Various command streams can be submitted to the same context.
430 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
435 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
438 * Query a GPU reset status.
440 enum pipe_reset_status (*ctx_query_reset_status
)(struct radeon_winsys_ctx
*ctx
);
443 * Create a command stream.
445 * \param ctx The submission context
446 * \param ring_type The ring type (GFX, DMA, UVD)
447 * \param flush Flush callback function associated with the command stream.
448 * \param user User pointer that will be passed to the flush callback.
450 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys_ctx
*ctx
,
451 enum ring_type ring_type
,
452 void (*flush
)(void *ctx
, unsigned flags
,
453 struct pipe_fence_handle
**fence
),
457 * Add a constant engine IB to a graphics CS. This makes the graphics CS
458 * from "cs_create" a group of two IBs that share a buffer list and are
461 * The returned constant CS is only a stream for writing packets to the new
462 * IB. Calling other winsys functions with it is not allowed, not even
465 * In order to add buffers and check memory usage, use the graphics CS.
466 * In order to flush it, use the graphics CS, which will flush both IBs.
467 * Destroying the graphics CS will destroy both of them.
469 * \param cs The graphics CS from "cs_create" that will hold the buffer
470 * list and will be used for flushing.
472 struct radeon_winsys_cs
*(*cs_add_const_ib
)(struct radeon_winsys_cs
*cs
);
475 * Add a constant engine preamble IB to a graphics CS. This add an extra IB
476 * in similar manner to cs_add_const_ib. This should always be called after
479 * The returned IB is a constant engine IB that only gets flushed if the
482 * \param cs The graphics CS from "cs_create" that will hold the buffer
483 * list and will be used for flushing.
485 struct radeon_winsys_cs
*(*cs_add_const_preamble_ib
)(struct radeon_winsys_cs
*cs
);
487 * Destroy a command stream.
489 * \param cs A command stream to destroy.
491 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
494 * Add a buffer. Each buffer used by a CS must be added using this function.
496 * \param cs Command stream
498 * \param usage Whether the buffer is used for read and/or write.
499 * \param domain Bitmask of the RADEON_DOMAIN_* flags.
500 * \param priority A higher number means a greater chance of being
501 * placed in the requested domain. 15 is the maximum.
502 * \return Buffer index.
504 unsigned (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
505 struct pb_buffer
*buf
,
506 enum radeon_bo_usage usage
,
507 enum radeon_bo_domain domain
,
508 enum radeon_bo_priority priority
);
511 * Return the index of an already-added buffer.
513 * Not supported on amdgpu. Drivers with GPUVM should not care about
516 * \param cs Command stream
518 * \return The buffer index, or -1 if the buffer has not been added.
520 int (*cs_lookup_buffer
)(struct radeon_winsys_cs
*cs
,
521 struct pb_buffer
*buf
);
524 * Return true if there is enough memory in VRAM and GTT for the buffers
525 * added so far. If the validation fails, all buffers which have
526 * been added since the last call of cs_validate will be removed and
527 * the CS will be flushed (provided there are still any buffers).
529 * \param cs A command stream to validate.
531 bool (*cs_validate
)(struct radeon_winsys_cs
*cs
);
534 * Check whether the given number of dwords is available in the IB.
535 * Optionally chain a new chunk of the IB if necessary and supported.
537 * \param cs A command stream.
538 * \param dw Number of CS dwords requested by the caller.
540 bool (*cs_check_space
)(struct radeon_winsys_cs
*cs
, unsigned dw
);
543 * Return the buffer list.
545 * This is the buffer list as passed to the kernel, i.e. it only contains
546 * the parent buffers of sub-allocated buffers.
548 * \param cs Command stream
549 * \param list Returned buffer list. Set to NULL to query the count only.
550 * \return The buffer count.
552 unsigned (*cs_get_buffer_list
)(struct radeon_winsys_cs
*cs
,
553 struct radeon_bo_list_item
*list
);
556 * Flush a command stream.
558 * \param cs A command stream to flush.
559 * \param flags, RADEON_FLUSH_ASYNC or 0.
560 * \param fence Pointer to a fence. If non-NULL, a fence is inserted
561 * after the CS and is returned through this parameter.
562 * \return Negative POSIX error code or 0 for success.
563 * Asynchronous submissions never return an error.
565 int (*cs_flush
)(struct radeon_winsys_cs
*cs
,
567 struct pipe_fence_handle
**fence
);
570 * Create a fence before the CS is flushed.
571 * The user must flush manually to complete the initializaton of the fence.
572 * The fence must not be used before the flush.
574 struct pipe_fence_handle
*(*cs_get_next_fence
)(struct radeon_winsys_cs
*cs
);
577 * Return true if a buffer is referenced by a command stream.
579 * \param cs A command stream.
580 * \param buf A winsys buffer.
582 bool (*cs_is_buffer_referenced
)(struct radeon_winsys_cs
*cs
,
583 struct pb_buffer
*buf
,
584 enum radeon_bo_usage usage
);
587 * Request access to a feature for a command stream.
589 * \param cs A command stream.
590 * \param fid Feature ID, one of RADEON_FID_*
591 * \param enable Whether to enable or disable the feature.
593 bool (*cs_request_feature
)(struct radeon_winsys_cs
*cs
,
594 enum radeon_feature_id fid
,
597 * Make sure all asynchronous flush of the cs have completed
599 * \param cs A command stream.
601 void (*cs_sync_flush
)(struct radeon_winsys_cs
*cs
);
604 * Wait for the fence and return true if the fence has been signalled.
605 * The timeout of 0 will only return the status.
606 * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
609 bool (*fence_wait
)(struct radeon_winsys
*ws
,
610 struct pipe_fence_handle
*fence
,
614 * Reference counting for fences.
616 void (*fence_reference
)(struct pipe_fence_handle
**dst
,
617 struct pipe_fence_handle
*src
);
622 * \param ws The winsys this function is called from.
623 * \param tex Input texture description
624 * \param flags Bitmask of RADEON_SURF_* flags
625 * \param bpe Bytes per pixel, it can be different for Z buffers.
626 * \param mode Preferred tile mode. (linear, 1D, or 2D)
627 * \param surf Output structure
629 int (*surface_init
)(struct radeon_winsys
*ws
,
630 const struct pipe_resource
*tex
,
631 unsigned flags
, unsigned bpe
,
632 enum radeon_surf_mode mode
,
633 struct radeon_surf
*surf
);
635 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
636 enum radeon_value_id value
);
638 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
639 unsigned num_registers
, uint32_t *out
);
642 static inline bool radeon_emitted(struct radeon_winsys_cs
*cs
, unsigned num_dw
)
644 return cs
&& (cs
->prev_dw
+ cs
->current
.cdw
> num_dw
);
647 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
649 cs
->current
.buf
[cs
->current
.cdw
++] = value
;
652 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
653 const uint32_t *values
, unsigned count
)
655 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, values
, count
* 4);
656 cs
->current
.cdw
+= count
;