src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 #include "pipebuffer/pb_buffer.h"
  30
  31 #define RADEON_FLUSH_ASYNC              (1 << 0)
  32 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1)
  33 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  34
  35 /* Tiling flags. */
  36 enum radeon_bo_layout {
  37     RADEON_LAYOUT_LINEAR = 0,
  38     RADEON_LAYOUT_TILED,
  39     RADEON_LAYOUT_SQUARETILED,
  40
  41     RADEON_LAYOUT_UNKNOWN
  42 };
  43
  44 enum radeon_bo_domain { /* bitfield */
  45     RADEON_DOMAIN_GTT  = 2,
  46     RADEON_DOMAIN_VRAM = 4,
  47     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51     RADEON_FLAG_GTT_WC =        (1 << 0),
  52     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57     RADEON_USAGE_READ = 2,
  58     RADEON_USAGE_WRITE = 4,
  59     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum radeon_family {
  63     CHIP_UNKNOWN = 0,
  64     CHIP_R300, /* R3xx-based cores. */
  65     CHIP_R350,
  66     CHIP_RV350,
  67     CHIP_RV370,
  68     CHIP_RV380,
  69     CHIP_RS400,
  70     CHIP_RC410,
  71     CHIP_RS480,
  72     CHIP_R420,     /* R4xx-based cores. */
  73     CHIP_R423,
  74     CHIP_R430,
  75     CHIP_R480,
  76     CHIP_R481,
  77     CHIP_RV410,
  78     CHIP_RS600,
  79     CHIP_RS690,
  80     CHIP_RS740,
  81     CHIP_RV515,    /* R5xx-based cores. */
  82     CHIP_R520,
  83     CHIP_RV530,
  84     CHIP_R580,
  85     CHIP_RV560,
  86     CHIP_RV570,
  87     CHIP_R600,
  88     CHIP_RV610,
  89     CHIP_RV630,
  90     CHIP_RV670,
  91     CHIP_RV620,
  92     CHIP_RV635,
  93     CHIP_RS780,
  94     CHIP_RS880,
  95     CHIP_RV770,
  96     CHIP_RV730,
  97     CHIP_RV710,
  98     CHIP_RV740,
  99     CHIP_CEDAR,
 100     CHIP_REDWOOD,
 101     CHIP_JUNIPER,
 102     CHIP_CYPRESS,
 103     CHIP_HEMLOCK,
 104     CHIP_PALM,
 105     CHIP_SUMO,
 106     CHIP_SUMO2,
 107     CHIP_BARTS,
 108     CHIP_TURKS,
 109     CHIP_CAICOS,
 110     CHIP_CAYMAN,
 111     CHIP_ARUBA,
 112     CHIP_TAHITI,
 113     CHIP_PITCAIRN,
 114     CHIP_VERDE,
 115     CHIP_OLAND,
 116     CHIP_HAINAN,
 117     CHIP_BONAIRE,
 118     CHIP_KAVERI,
 119     CHIP_KABINI,
 120     CHIP_HAWAII,
 121     CHIP_MULLINS,
 122     CHIP_TONGA,
 123     CHIP_ICELAND,
 124     CHIP_CARRIZO,
 125     CHIP_FIJI,
 126     CHIP_STONEY,
 127     CHIP_LAST,
 128 };
 129
 130 enum chip_class {
 131     CLASS_UNKNOWN = 0,
 132     R300,
 133     R400,
 134     R500,
 135     R600,
 136     R700,
 137     EVERGREEN,
 138     CAYMAN,
 139     SI,
 140     CIK,
 141     VI,
 142 };
 143
 144 enum ring_type {
 145     RING_GFX = 0,
 146     RING_COMPUTE,
 147     RING_DMA,
 148     RING_UVD,
 149     RING_VCE,
 150     RING_LAST,
 151 };
 152
 153 enum radeon_value_id {
 154     RADEON_REQUESTED_VRAM_MEMORY,
 155     RADEON_REQUESTED_GTT_MEMORY,
 156     RADEON_BUFFER_WAIT_TIME_NS,
 157     RADEON_TIMESTAMP,
 158     RADEON_NUM_CS_FLUSHES,
 159     RADEON_NUM_BYTES_MOVED,
 160     RADEON_VRAM_USAGE,
 161     RADEON_GTT_USAGE,
 162     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 163     RADEON_CURRENT_SCLK,
 164     RADEON_CURRENT_MCLK,
 165     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 166 };
 167
 168 /* Each group of four has the same priority. */
 169 enum radeon_bo_priority {
 170     RADEON_PRIO_FENCE = 0,
 171     RADEON_PRIO_TRACE,
 172     RADEON_PRIO_SO_FILLED_SIZE,
 173     RADEON_PRIO_QUERY,
 174
 175     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 176     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 177     RADEON_PRIO_DRAW_INDIRECT,
 178     RADEON_PRIO_INDEX_BUFFER,
 179
 180     RADEON_PRIO_CP_DMA = 8,
 181
 182     RADEON_PRIO_VCE = 12,
 183     RADEON_PRIO_UVD,
 184     RADEON_PRIO_SDMA_BUFFER,
 185     RADEON_PRIO_SDMA_TEXTURE,
 186
 187     RADEON_PRIO_USER_SHADER = 16,
 188     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 189
 190     /* gap: 20 */
 191
 192     RADEON_PRIO_CONST_BUFFER = 24,
 193     RADEON_PRIO_DESCRIPTORS,
 194     RADEON_PRIO_BORDER_COLORS,
 195
 196     RADEON_PRIO_SAMPLER_BUFFER = 28,
 197     RADEON_PRIO_VERTEX_BUFFER,
 198
 199     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 200     RADEON_PRIO_RINGS_STREAMOUT,
 201     RADEON_PRIO_SCRATCH_BUFFER,
 202     RADEON_PRIO_COMPUTE_GLOBAL,
 203
 204     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 205     RADEON_PRIO_SHADER_RW_IMAGE,
 206
 207     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 208
 209     RADEON_PRIO_COLOR_BUFFER = 44,
 210
 211     RADEON_PRIO_DEPTH_BUFFER = 48,
 212
 213     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 214
 215     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 216
 217     RADEON_PRIO_CMASK = 60,
 218     RADEON_PRIO_DCC,
 219     RADEON_PRIO_HTILE,
 220     /* 63 is the maximum value */
 221 };
 222
 223 struct winsys_handle;
 224 struct radeon_winsys_ctx;
 225
 226 struct radeon_winsys_cs {
 227     unsigned                    cdw;  /* Number of used dwords. */
 228     unsigned                    max_dw; /* Maximum number of dwords. */
 229     uint32_t                    *buf; /* The command buffer. */
 230     enum ring_type              ring_type;
 231 };
 232
 233 struct radeon_info {
 234     /* Device info. */
 235     uint32_t                    pci_id;
 236     enum radeon_family          family;
 237     enum chip_class             chip_class;
 238     uint64_t                    gart_size;
 239     uint64_t                    vram_size;
 240     boolean                     has_virtual_memory;
 241     bool                        gfx_ib_pad_with_type2;
 242     boolean                     has_sdma;
 243     boolean                     has_uvd;
 244     uint32_t                    vce_fw_version;
 245     uint32_t                    vce_harvest_config;
 246     uint32_t                    clock_crystal_freq;
 247
 248     /* Kernel info. */
 249     uint32_t                    drm_major; /* version */
 250     uint32_t                    drm_minor;
 251     uint32_t                    drm_patchlevel;
 252     boolean                     has_userptr;
 253
 254     /* Shader cores. */
 255     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 256     uint32_t                    max_shader_clock;
 257     uint32_t                    num_good_compute_units;
 258     uint32_t                    max_se; /* shader engines */
 259     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 260
 261     /* Render backends (color + depth blocks). */
 262     uint32_t                    r300_num_gb_pipes;
 263     uint32_t                    r300_num_z_pipes;
 264     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 265     boolean                     r600_gb_backend_map_valid;
 266     uint32_t                    r600_num_banks;
 267     uint32_t                    num_render_backends;
 268     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 269     uint32_t                    pipe_interleave_bytes;
 270     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 271
 272     /* Tile modes. */
 273     boolean                     si_tile_mode_array_valid;
 274     uint32_t                    si_tile_mode_array[32];
 275     boolean                     cik_macrotile_mode_array_valid;
 276     uint32_t                    cik_macrotile_mode_array[16];
 277 };
 278
 279 /* Tiling info for display code, DRI sharing, and other data. */
 280 struct radeon_bo_metadata {
 281     enum radeon_bo_layout   microtile;
 282     enum radeon_bo_layout   macrotile;
 283     unsigned                pipe_config;
 284     unsigned                bankw;
 285     unsigned                bankh;
 286     unsigned                tile_split;
 287     unsigned                stencil_tile_split;
 288     unsigned                mtilea;
 289     unsigned                num_banks;
 290     unsigned                stride;
 291     bool                    scanout;
 292 };
 293
 294 enum radeon_feature_id {
 295     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 296     RADEON_FID_R300_CMASK_ACCESS,
 297 };
 298
 299 #define RADEON_SURF_MAX_LEVEL                   32
 300
 301 #define RADEON_SURF_TYPE_MASK                   0xFF
 302 #define RADEON_SURF_TYPE_SHIFT                  0
 303 #define     RADEON_SURF_TYPE_1D                     0
 304 #define     RADEON_SURF_TYPE_2D                     1
 305 #define     RADEON_SURF_TYPE_3D                     2
 306 #define     RADEON_SURF_TYPE_CUBEMAP                3
 307 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 308 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 309 #define RADEON_SURF_MODE_MASK                   0xFF
 310 #define RADEON_SURF_MODE_SHIFT                  8
 311 #define     RADEON_SURF_MODE_LINEAR                 0
 312 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 313 #define     RADEON_SURF_MODE_1D                     2
 314 #define     RADEON_SURF_MODE_2D                     3
 315 #define RADEON_SURF_SCANOUT                     (1 << 16)
 316 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 317 #define RADEON_SURF_SBUFFER                     (1 << 18)
 318 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 319 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 320 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 321 #define RADEON_SURF_FMASK                       (1 << 21)
 322
 323 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 324 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 325 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 326
 327 struct radeon_surf_level {
 328     uint64_t                    offset;
 329     uint64_t                    slice_size;
 330     uint32_t                    npix_x;
 331     uint32_t                    npix_y;
 332     uint32_t                    npix_z;
 333     uint32_t                    nblk_x;
 334     uint32_t                    nblk_y;
 335     uint32_t                    nblk_z;
 336     uint32_t                    pitch_bytes;
 337     uint32_t                    mode;
 338     uint64_t                    dcc_offset;
 339 };
 340
 341 struct radeon_surf {
 342     /* These are inputs to the calculator. */
 343     uint32_t                    npix_x;
 344     uint32_t                    npix_y;
 345     uint32_t                    npix_z;
 346     uint32_t                    blk_w;
 347     uint32_t                    blk_h;
 348     uint32_t                    blk_d;
 349     uint32_t                    array_size;
 350     uint32_t                    last_level;
 351     uint32_t                    bpe;
 352     uint32_t                    nsamples;
 353     uint32_t                    flags;
 354
 355     /* These are return values. Some of them can be set by the caller, but
 356      * they will be treated as hints (e.g. bankw, bankh) and might be
 357      * changed by the calculator.
 358      */
 359     uint64_t                    bo_size;
 360     uint64_t                    bo_alignment;
 361     /* This applies to EG and later. */
 362     uint32_t                    bankw;
 363     uint32_t                    bankh;
 364     uint32_t                    mtilea;
 365     uint32_t                    tile_split;
 366     uint32_t                    stencil_tile_split;
 367     uint64_t                    stencil_offset;
 368     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 369     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 370     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 371     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 372     uint32_t                    pipe_config;
 373     uint32_t                    num_banks;
 374
 375     uint64_t                    dcc_size;
 376     uint64_t                    dcc_alignment;
 377 };
 378
 379 struct radeon_bo_list_item {
 380     struct pb_buffer *buf;
 381     uint64_t vm_address;
 382     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 383 };
 384
 385 struct radeon_winsys {
 386     /**
 387      * The screen object this winsys was created for
 388      */
 389     struct pipe_screen *screen;
 390
 391     /**
 392      * Decrement the winsys reference count.
 393      *
 394      * \param ws  The winsys this function is called for.
 395      * \return    True if the winsys and screen should be destroyed.
 396      */
 397     bool (*unref)(struct radeon_winsys *ws);
 398
 399     /**
 400      * Destroy this winsys.
 401      *
 402      * \param ws        The winsys this function is called from.
 403      */
 404     void (*destroy)(struct radeon_winsys *ws);
 405
 406     /**
 407      * Query an info structure from winsys.
 408      *
 409      * \param ws        The winsys this function is called from.
 410      * \param info      Return structure
 411      */
 412     void (*query_info)(struct radeon_winsys *ws,
 413                        struct radeon_info *info);
 414
 415     /**************************************************************************
 416      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 417      *
 418      * Remember that gallium gets to choose the interface it needs, and the
 419      * window systems must then implement that interface (rather than the
 420      * other way around...).
 421      *************************************************************************/
 422
 423     /**
 424      * Create a buffer object.
 425      *
 426      * \param ws        The winsys this function is called from.
 427      * \param size      The size to allocate.
 428      * \param alignment An alignment of the buffer in memory.
 429      * \param use_reusable_pool Whether the cache buffer manager should be used.
 430      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 431      * \return          The created buffer object.
 432      */
 433     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 434                                        unsigned size,
 435                                        unsigned alignment,
 436                                        boolean use_reusable_pool,
 437                                        enum radeon_bo_domain domain,
 438                                        enum radeon_bo_flag flags);
 439
 440     /**
 441      * Map the entire data store of a buffer object into the client's address
 442      * space.
 443      *
 444      * \param buf       A winsys buffer object to map.
 445      * \param cs        A command stream to flush if the buffer is referenced by it.
 446      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 447      * \return          The pointer at the beginning of the buffer.
 448      */
 449     void *(*buffer_map)(struct pb_buffer *buf,
 450                         struct radeon_winsys_cs *cs,
 451                         enum pipe_transfer_usage usage);
 452
 453     /**
 454      * Unmap a buffer object from the client's address space.
 455      *
 456      * \param buf       A winsys buffer object to unmap.
 457      */
 458     void (*buffer_unmap)(struct pb_buffer *buf);
 459
 460     /**
 461      * Wait for the buffer and return true if the buffer is not used
 462      * by the device.
 463      *
 464      * The timeout of 0 will only return the status.
 465      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 466      * is idle.
 467      */
 468     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 469                         enum radeon_bo_usage usage);
 470
 471     /**
 472      * Return buffer metadata.
 473      * (tiling info for display code, DRI sharing, and other data)
 474      *
 475      * \param buf       A winsys buffer object to get the flags from.
 476      * \param md        Metadata
 477      */
 478     void (*buffer_get_metadata)(struct pb_buffer *buf,
 479                                 struct radeon_bo_metadata *md);
 480
 481     /**
 482      * Set buffer metadata.
 483      * (tiling info for display code, DRI sharing, and other data)
 484      *
 485      * \param buf       A winsys buffer object to set the flags for.
 486      * \param md        Metadata
 487      */
 488     void (*buffer_set_metadata)(struct pb_buffer *buf,
 489                                 struct radeon_bo_metadata *md);
 490
 491     /**
 492      * Get a winsys buffer from a winsys handle. The internal structure
 493      * of the handle is platform-specific and only a winsys should access it.
 494      *
 495      * \param ws        The winsys this function is called from.
 496      * \param whandle   A winsys handle pointer as was received from a state
 497      *                  tracker.
 498      * \param stride    The returned buffer stride in bytes.
 499      */
 500     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 501                                             struct winsys_handle *whandle,
 502                                             unsigned *stride);
 503
 504     /**
 505      * Get a winsys buffer from a user pointer. The resulting buffer can't
 506      * be exported. Both pointer and size must be page aligned.
 507      *
 508      * \param ws        The winsys this function is called from.
 509      * \param pointer   User pointer to turn into a buffer object.
 510      * \param Size      Size in bytes for the new buffer.
 511      */
 512     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 513                                          void *pointer, unsigned size);
 514
 515     /**
 516      * Whether the buffer was created from a user pointer.
 517      *
 518      * \param buf       A winsys buffer object
 519      * \return          whether \p buf was created via buffer_from_ptr
 520      */
 521     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 522
 523     /**
 524      * Get a winsys handle from a winsys buffer. The internal structure
 525      * of the handle is platform-specific and only a winsys should access it.
 526      *
 527      * \param buf       A winsys buffer object to get the handle from.
 528      * \param whandle   A winsys handle pointer.
 529      * \param stride    A stride of the buffer in bytes, for texturing.
 530      * \return          TRUE on success.
 531      */
 532     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 533                                  unsigned stride,
 534                                  struct winsys_handle *whandle);
 535
 536     /**
 537      * Return the virtual address of a buffer.
 538      *
 539      * \param buf       A winsys buffer object
 540      * \return          virtual address
 541      */
 542     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 543
 544     /**
 545      * Query the initial placement of the buffer from the kernel driver.
 546      */
 547     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 548
 549     /**************************************************************************
 550      * Command submission.
 551      *
 552      * Each pipe context should create its own command stream and submit
 553      * commands independently of other contexts.
 554      *************************************************************************/
 555
 556     /**
 557      * Create a command submission context.
 558      * Various command streams can be submitted to the same context.
 559      */
 560     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 561
 562     /**
 563      * Destroy a context.
 564      */
 565     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 566
 567     /**
 568      * Query a GPU reset status.
 569      */
 570     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 571
 572     /**
 573      * Create a command stream.
 574      *
 575      * \param ctx       The submission context
 576      * \param ring_type The ring type (GFX, DMA, UVD)
 577      * \param flush     Flush callback function associated with the command stream.
 578      * \param user      User pointer that will be passed to the flush callback.
 579      * \param trace_buf Trace buffer when tracing is enabled
 580      */
 581     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 582                                           enum ring_type ring_type,
 583                                           void (*flush)(void *ctx, unsigned flags,
 584                                                         struct pipe_fence_handle **fence),
 585                                           void *flush_ctx,
 586                                           struct pb_buffer *trace_buf);
 587
 588     /**
 589      * Destroy a command stream.
 590      *
 591      * \param cs        A command stream to destroy.
 592      */
 593     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 594
 595     /**
 596      * Add a buffer. Each buffer used by a CS must be added using this function.
 597      *
 598      * \param cs      Command stream
 599      * \param buf     Buffer
 600      * \param usage   Whether the buffer is used for read and/or write.
 601      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 602      * \param priority  A higher number means a greater chance of being
 603      *                  placed in the requested domain. 15 is the maximum.
 604      * \return Buffer index.
 605      */
 606     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 607                              struct pb_buffer *buf,
 608                              enum radeon_bo_usage usage,
 609                              enum radeon_bo_domain domain,
 610                              enum radeon_bo_priority priority);
 611
 612     /**
 613      * Return the index of an already-added buffer.
 614      *
 615      * \param cs        Command stream
 616      * \param buf       Buffer
 617      * \return          The buffer index, or -1 if the buffer has not been added.
 618      */
 619     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 620                             struct pb_buffer *buf);
 621
 622     /**
 623      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 624      * added so far. If the validation fails, all buffers which have
 625      * been added since the last call of cs_validate will be removed and
 626      * the CS will be flushed (provided there are still any buffers).
 627      *
 628      * \param cs        A command stream to validate.
 629      */
 630     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 631
 632     /**
 633      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 634      * added so far.
 635      *
 636      * \param cs        A command stream to validate.
 637      * \param vram      VRAM memory size pending to be use
 638      * \param gtt       GTT memory size pending to be use
 639      */
 640     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 641
 642     /**
 643      * Return the buffer list.
 644      *
 645      * \param cs    Command stream
 646      * \param list  Returned buffer list. Set to NULL to query the count only.
 647      * \return      The buffer count.
 648      */
 649     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 650                                    struct radeon_bo_list_item *list);
 651
 652     /**
 653      * Flush a command stream.
 654      *
 655      * \param cs          A command stream to flush.
 656      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 657      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 658      *                    after the CS and is returned through this parameter.
 659      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 660      */
 661     void (*cs_flush)(struct radeon_winsys_cs *cs,
 662                      unsigned flags,
 663                      struct pipe_fence_handle **fence,
 664                      uint32_t cs_trace_id);
 665
 666     /**
 667      * Return TRUE if a buffer is referenced by a command stream.
 668      *
 669      * \param cs        A command stream.
 670      * \param buf       A winsys buffer.
 671      */
 672     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 673                                        struct pb_buffer *buf,
 674                                        enum radeon_bo_usage usage);
 675
 676     /**
 677      * Request access to a feature for a command stream.
 678      *
 679      * \param cs        A command stream.
 680      * \param fid       Feature ID, one of RADEON_FID_*
 681      * \param enable    Whether to enable or disable the feature.
 682      */
 683     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 684                                   enum radeon_feature_id fid,
 685                                   boolean enable);
 686      /**
 687       * Make sure all asynchronous flush of the cs have completed
 688       *
 689       * \param cs        A command stream.
 690       */
 691     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 692
 693     /**
 694      * Wait for the fence and return true if the fence has been signalled.
 695      * The timeout of 0 will only return the status.
 696      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 697      * is signalled.
 698      */
 699     bool (*fence_wait)(struct radeon_winsys *ws,
 700                        struct pipe_fence_handle *fence,
 701                        uint64_t timeout);
 702
 703     /**
 704      * Reference counting for fences.
 705      */
 706     void (*fence_reference)(struct pipe_fence_handle **dst,
 707                             struct pipe_fence_handle *src);
 708
 709     /**
 710      * Initialize surface
 711      *
 712      * \param ws        The winsys this function is called from.
 713      * \param surf      Surface structure ptr
 714      */
 715     int (*surface_init)(struct radeon_winsys *ws,
 716                         struct radeon_surf *surf);
 717
 718     /**
 719      * Find best values for a surface
 720      *
 721      * \param ws        The winsys this function is called from.
 722      * \param surf      Surface structure ptr
 723      */
 724     int (*surface_best)(struct radeon_winsys *ws,
 725                         struct radeon_surf *surf);
 726
 727     uint64_t (*query_value)(struct radeon_winsys *ws,
 728                             enum radeon_value_id value);
 729
 730     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 731                            unsigned num_registers, uint32_t *out);
 732 };
 733
 734
 735 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 736 {
 737     cs->buf[cs->cdw++] = value;
 738 }
 739
 740 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 741                                      const uint32_t *values, unsigned count)
 742 {
 743     memcpy(cs->buf+cs->cdw, values, count * 4);
 744     cs->cdw += count;
 745 }
 746
 747 #endif