src/gallium/drivers/radeon/radeon_winsys.h

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  23
  24 #ifndef RADEON_WINSYS_H
  25 #define RADEON_WINSYS_H
  26
  27 /* The public winsys interface header for the radeon driver. */
  28
  29 /* R300 features in DRM.
  30  *
  31  * 2.6.0:
  32  * - Hyper-Z
  33  * - GB_Z_PEQ_CONFIG on rv350->r4xx
  34  * - R500 FG_ALPHA_VALUE
  35  *
  36  * 2.8.0:
  37  * - R500 US_FORMAT regs
  38  * - R500 ARGB2101010 colorbuffer
  39  * - CMask and AA regs
  40  * - R16F/RG16F
  41  */
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #define RADEON_FLUSH_ASYNC              (1 << 0)
  46 #define RADEON_FLUSH_KEEP_TILING_FLAGS  (1 << 1) /* needs DRM 2.12.0 */
  47 #define RADEON_FLUSH_END_OF_FRAME       (1 << 2)
  48
  49 /* Tiling flags. */
  50 enum radeon_bo_layout {
  51     RADEON_LAYOUT_LINEAR = 0,
  52     RADEON_LAYOUT_TILED,
  53     RADEON_LAYOUT_SQUARETILED,
  54
  55     RADEON_LAYOUT_UNKNOWN
  56 };
  57
  58 enum radeon_bo_domain { /* bitfield */
  59     RADEON_DOMAIN_GTT  = 2,
  60     RADEON_DOMAIN_VRAM = 4,
  61     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  62 };
  63
  64 enum radeon_bo_flag { /* bitfield */
  65     RADEON_FLAG_GTT_WC =        (1 << 0),
  66     RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  67     RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  68 };
  69
  70 enum radeon_bo_usage { /* bitfield */
  71     RADEON_USAGE_READ = 2,
  72     RADEON_USAGE_WRITE = 4,
  73     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  74 };
  75
  76 enum radeon_family {
  77     CHIP_UNKNOWN = 0,
  78     CHIP_R300, /* R3xx-based cores. */
  79     CHIP_R350,
  80     CHIP_RV350,
  81     CHIP_RV370,
  82     CHIP_RV380,
  83     CHIP_RS400,
  84     CHIP_RC410,
  85     CHIP_RS480,
  86     CHIP_R420,     /* R4xx-based cores. */
  87     CHIP_R423,
  88     CHIP_R430,
  89     CHIP_R480,
  90     CHIP_R481,
  91     CHIP_RV410,
  92     CHIP_RS600,
  93     CHIP_RS690,
  94     CHIP_RS740,
  95     CHIP_RV515,    /* R5xx-based cores. */
  96     CHIP_R520,
  97     CHIP_RV530,
  98     CHIP_R580,
  99     CHIP_RV560,
 100     CHIP_RV570,
 101     CHIP_R600,
 102     CHIP_RV610,
 103     CHIP_RV630,
 104     CHIP_RV670,
 105     CHIP_RV620,
 106     CHIP_RV635,
 107     CHIP_RS780,
 108     CHIP_RS880,
 109     CHIP_RV770,
 110     CHIP_RV730,
 111     CHIP_RV710,
 112     CHIP_RV740,
 113     CHIP_CEDAR,
 114     CHIP_REDWOOD,
 115     CHIP_JUNIPER,
 116     CHIP_CYPRESS,
 117     CHIP_HEMLOCK,
 118     CHIP_PALM,
 119     CHIP_SUMO,
 120     CHIP_SUMO2,
 121     CHIP_BARTS,
 122     CHIP_TURKS,
 123     CHIP_CAICOS,
 124     CHIP_CAYMAN,
 125     CHIP_ARUBA,
 126     CHIP_TAHITI,
 127     CHIP_PITCAIRN,
 128     CHIP_VERDE,
 129     CHIP_OLAND,
 130     CHIP_HAINAN,
 131     CHIP_BONAIRE,
 132     CHIP_KAVERI,
 133     CHIP_KABINI,
 134     CHIP_HAWAII,
 135     CHIP_MULLINS,
 136     CHIP_TONGA,
 137     CHIP_ICELAND,
 138     CHIP_CARRIZO,
 139     CHIP_FIJI,
 140     CHIP_STONEY,
 141     CHIP_LAST,
 142 };
 143
 144 enum chip_class {
 145     CLASS_UNKNOWN = 0,
 146     R300,
 147     R400,
 148     R500,
 149     R600,
 150     R700,
 151     EVERGREEN,
 152     CAYMAN,
 153     SI,
 154     CIK,
 155     VI,
 156 };
 157
 158 enum ring_type {
 159     RING_GFX = 0,
 160     RING_COMPUTE,
 161     RING_DMA,
 162     RING_UVD,
 163     RING_VCE,
 164     RING_LAST,
 165 };
 166
 167 enum radeon_value_id {
 168     RADEON_REQUESTED_VRAM_MEMORY,
 169     RADEON_REQUESTED_GTT_MEMORY,
 170     RADEON_BUFFER_WAIT_TIME_NS,
 171     RADEON_TIMESTAMP,
 172     RADEON_NUM_CS_FLUSHES,
 173     RADEON_NUM_BYTES_MOVED,
 174     RADEON_VRAM_USAGE,
 175     RADEON_GTT_USAGE,
 176     RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
 177     RADEON_CURRENT_SCLK,
 178     RADEON_CURRENT_MCLK,
 179     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 180 };
 181
 182 /* Each group of four has the same priority. */
 183 enum radeon_bo_priority {
 184     RADEON_PRIO_FENCE = 0,
 185     RADEON_PRIO_TRACE,
 186     RADEON_PRIO_SO_FILLED_SIZE,
 187     RADEON_PRIO_QUERY,
 188
 189     RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
 190     RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
 191     RADEON_PRIO_DRAW_INDIRECT,
 192     RADEON_PRIO_INDEX_BUFFER,
 193
 194     RADEON_PRIO_CP_DMA = 8,
 195
 196     RADEON_PRIO_VCE = 12,
 197     RADEON_PRIO_UVD,
 198     RADEON_PRIO_SDMA_BUFFER,
 199     RADEON_PRIO_SDMA_TEXTURE,
 200
 201     RADEON_PRIO_USER_SHADER = 16,
 202     RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
 203
 204     /* gap: 20 */
 205
 206     RADEON_PRIO_CONST_BUFFER = 24,
 207     RADEON_PRIO_DESCRIPTORS,
 208     RADEON_PRIO_BORDER_COLORS,
 209
 210     RADEON_PRIO_SAMPLER_BUFFER = 28,
 211     RADEON_PRIO_VERTEX_BUFFER,
 212
 213     RADEON_PRIO_SHADER_RW_BUFFER = 32,
 214     RADEON_PRIO_RINGS_STREAMOUT,
 215     RADEON_PRIO_SCRATCH_BUFFER,
 216     RADEON_PRIO_COMPUTE_GLOBAL,
 217
 218     RADEON_PRIO_SAMPLER_TEXTURE = 36,
 219     RADEON_PRIO_SHADER_RW_IMAGE,
 220
 221     RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
 222
 223     RADEON_PRIO_COLOR_BUFFER = 44,
 224
 225     RADEON_PRIO_DEPTH_BUFFER = 48,
 226
 227     RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
 228
 229     RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
 230
 231     RADEON_PRIO_CMASK = 60,
 232     RADEON_PRIO_DCC,
 233     RADEON_PRIO_HTILE,
 234     /* 63 is the maximum value */
 235 };
 236
 237 struct winsys_handle;
 238 struct radeon_winsys_ctx;
 239
 240 struct radeon_winsys_cs {
 241     unsigned                    cdw;  /* Number of used dwords. */
 242     unsigned                    max_dw; /* Maximum number of dwords. */
 243     uint32_t                    *buf; /* The command buffer. */
 244     enum ring_type              ring_type;
 245 };
 246
 247 struct radeon_info {
 248     /* Device info. */
 249     uint32_t                    pci_id;
 250     enum radeon_family          family;
 251     enum chip_class             chip_class;
 252     uint64_t                    gart_size;
 253     uint64_t                    vram_size;
 254     boolean                     has_virtual_memory;
 255     bool                        gfx_ib_pad_with_type2;
 256     boolean                     has_sdma;
 257     boolean                     has_uvd;
 258     uint32_t                    vce_fw_version;
 259     uint32_t                    vce_harvest_config;
 260     uint32_t                    clock_crystal_freq;
 261
 262     /* Kernel info. */
 263     uint32_t                    drm_major; /* version */
 264     uint32_t                    drm_minor;
 265     uint32_t                    drm_patchlevel;
 266     boolean                     has_userptr;
 267
 268     /* Shader cores. */
 269     uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 270     uint32_t                    max_shader_clock;
 271     uint32_t                    num_good_compute_units;
 272     uint32_t                    max_se; /* shader engines */
 273     uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 274
 275     /* Render backends (color + depth blocks). */
 276     uint32_t                    r300_num_gb_pipes;
 277     uint32_t                    r300_num_z_pipes;
 278     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 279     boolean                     r600_gb_backend_map_valid;
 280     uint32_t                    r600_num_banks;
 281     uint32_t                    num_render_backends;
 282     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 283     uint32_t                    pipe_interleave_bytes;
 284     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 285
 286     /* Tile modes. */
 287     boolean                     si_tile_mode_array_valid;
 288     uint32_t                    si_tile_mode_array[32];
 289     boolean                     cik_macrotile_mode_array_valid;
 290     uint32_t                    cik_macrotile_mode_array[16];
 291 };
 292
 293 enum radeon_feature_id {
 294     RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
 295     RADEON_FID_R300_CMASK_ACCESS,
 296 };
 297
 298 #define RADEON_SURF_MAX_LEVEL                   32
 299
 300 #define RADEON_SURF_TYPE_MASK                   0xFF
 301 #define RADEON_SURF_TYPE_SHIFT                  0
 302 #define     RADEON_SURF_TYPE_1D                     0
 303 #define     RADEON_SURF_TYPE_2D                     1
 304 #define     RADEON_SURF_TYPE_3D                     2
 305 #define     RADEON_SURF_TYPE_CUBEMAP                3
 306 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 307 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 308 #define RADEON_SURF_MODE_MASK                   0xFF
 309 #define RADEON_SURF_MODE_SHIFT                  8
 310 #define     RADEON_SURF_MODE_LINEAR                 0
 311 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 312 #define     RADEON_SURF_MODE_1D                     2
 313 #define     RADEON_SURF_MODE_2D                     3
 314 #define RADEON_SURF_SCANOUT                     (1 << 16)
 315 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 316 #define RADEON_SURF_SBUFFER                     (1 << 18)
 317 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 318 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 319 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 320 #define RADEON_SURF_FMASK                       (1 << 21)
 321
 322 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 323 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 324 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 325
 326 struct radeon_surf_level {
 327     uint64_t                    offset;
 328     uint64_t                    slice_size;
 329     uint32_t                    npix_x;
 330     uint32_t                    npix_y;
 331     uint32_t                    npix_z;
 332     uint32_t                    nblk_x;
 333     uint32_t                    nblk_y;
 334     uint32_t                    nblk_z;
 335     uint32_t                    pitch_bytes;
 336     uint32_t                    mode;
 337     uint64_t                    dcc_offset;
 338 };
 339
 340 struct radeon_surf {
 341     /* These are inputs to the calculator. */
 342     uint32_t                    npix_x;
 343     uint32_t                    npix_y;
 344     uint32_t                    npix_z;
 345     uint32_t                    blk_w;
 346     uint32_t                    blk_h;
 347     uint32_t                    blk_d;
 348     uint32_t                    array_size;
 349     uint32_t                    last_level;
 350     uint32_t                    bpe;
 351     uint32_t                    nsamples;
 352     uint32_t                    flags;
 353
 354     /* These are return values. Some of them can be set by the caller, but
 355      * they will be treated as hints (e.g. bankw, bankh) and might be
 356      * changed by the calculator.
 357      */
 358     uint64_t                    bo_size;
 359     uint64_t                    bo_alignment;
 360     /* This applies to EG and later. */
 361     uint32_t                    bankw;
 362     uint32_t                    bankh;
 363     uint32_t                    mtilea;
 364     uint32_t                    tile_split;
 365     uint32_t                    stencil_tile_split;
 366     uint64_t                    stencil_offset;
 367     struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 368     struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 369     uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 370     uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 371     uint32_t                    pipe_config;
 372     uint32_t                    num_banks;
 373
 374     uint64_t                    dcc_size;
 375     uint64_t                    dcc_alignment;
 376 };
 377
 378 struct radeon_bo_list_item {
 379     struct pb_buffer *buf;
 380     uint64_t vm_address;
 381     uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 382 };
 383
 384 struct radeon_winsys {
 385     /**
 386      * The screen object this winsys was created for
 387      */
 388     struct pipe_screen *screen;
 389
 390     /**
 391      * Decrement the winsys reference count.
 392      *
 393      * \param ws  The winsys this function is called for.
 394      * \return    True if the winsys and screen should be destroyed.
 395      */
 396     bool (*unref)(struct radeon_winsys *ws);
 397
 398     /**
 399      * Destroy this winsys.
 400      *
 401      * \param ws        The winsys this function is called from.
 402      */
 403     void (*destroy)(struct radeon_winsys *ws);
 404
 405     /**
 406      * Query an info structure from winsys.
 407      *
 408      * \param ws        The winsys this function is called from.
 409      * \param info      Return structure
 410      */
 411     void (*query_info)(struct radeon_winsys *ws,
 412                        struct radeon_info *info);
 413
 414     /**************************************************************************
 415      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
 416      *
 417      * Remember that gallium gets to choose the interface it needs, and the
 418      * window systems must then implement that interface (rather than the
 419      * other way around...).
 420      *************************************************************************/
 421
 422     /**
 423      * Create a buffer object.
 424      *
 425      * \param ws        The winsys this function is called from.
 426      * \param size      The size to allocate.
 427      * \param alignment An alignment of the buffer in memory.
 428      * \param use_reusable_pool Whether the cache buffer manager should be used.
 429      * \param domain    A bitmask of the RADEON_DOMAIN_* flags.
 430      * \return          The created buffer object.
 431      */
 432     struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
 433                                        unsigned size,
 434                                        unsigned alignment,
 435                                        boolean use_reusable_pool,
 436                                        enum radeon_bo_domain domain,
 437                                        enum radeon_bo_flag flags);
 438
 439     /**
 440      * Map the entire data store of a buffer object into the client's address
 441      * space.
 442      *
 443      * \param buf       A winsys buffer object to map.
 444      * \param cs        A command stream to flush if the buffer is referenced by it.
 445      * \param usage     A bitmask of the PIPE_TRANSFER_* flags.
 446      * \return          The pointer at the beginning of the buffer.
 447      */
 448     void *(*buffer_map)(struct pb_buffer *buf,
 449                         struct radeon_winsys_cs *cs,
 450                         enum pipe_transfer_usage usage);
 451
 452     /**
 453      * Unmap a buffer object from the client's address space.
 454      *
 455      * \param buf       A winsys buffer object to unmap.
 456      */
 457     void (*buffer_unmap)(struct pb_buffer *buf);
 458
 459     /**
 460      * Wait for the buffer and return true if the buffer is not used
 461      * by the device.
 462      *
 463      * The timeout of 0 will only return the status.
 464      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the buffer
 465      * is idle.
 466      */
 467     bool (*buffer_wait)(struct pb_buffer *buf, uint64_t timeout,
 468                         enum radeon_bo_usage usage);
 469
 470     /**
 471      * Return tiling flags describing a memory layout of a buffer object.
 472      *
 473      * \param buf       A winsys buffer object to get the flags from.
 474      * \param macrotile A pointer to the return value of the microtile flag.
 475      * \param microtile A pointer to the return value of the macrotile flag.
 476      *
 477      * \note microtile and macrotile are not bitmasks!
 478      */
 479     void (*buffer_get_tiling)(struct pb_buffer *buf,
 480                               enum radeon_bo_layout *microtile,
 481                               enum radeon_bo_layout *macrotile,
 482                               unsigned *bankw, unsigned *bankh,
 483                               unsigned *tile_split,
 484                               unsigned *stencil_tile_split,
 485                               unsigned *mtilea,
 486                               bool *scanout);
 487
 488     /**
 489      * Set tiling flags describing a memory layout of a buffer object.
 490      *
 491      * \param buf       A winsys buffer object to set the flags for.
 492      * \param cs        A command stream to flush if the buffer is referenced by it.
 493      * \param macrotile A macrotile flag.
 494      * \param microtile A microtile flag.
 495      * \param stride    A stride of the buffer in bytes, for texturing.
 496      *
 497      * \note microtile and macrotile are not bitmasks!
 498      */
 499     void (*buffer_set_tiling)(struct pb_buffer *buf,
 500                               struct radeon_winsys_cs *rcs,
 501                               enum radeon_bo_layout microtile,
 502                               enum radeon_bo_layout macrotile,
 503                               unsigned pipe_config,
 504                               unsigned bankw, unsigned bankh,
 505                               unsigned tile_split,
 506                               unsigned stencil_tile_split,
 507                               unsigned mtilea, unsigned num_banks,
 508                               unsigned stride,
 509                               bool scanout);
 510
 511     /**
 512      * Get a winsys buffer from a winsys handle. The internal structure
 513      * of the handle is platform-specific and only a winsys should access it.
 514      *
 515      * \param ws        The winsys this function is called from.
 516      * \param whandle   A winsys handle pointer as was received from a state
 517      *                  tracker.
 518      * \param stride    The returned buffer stride in bytes.
 519      */
 520     struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
 521                                             struct winsys_handle *whandle,
 522                                             unsigned *stride);
 523
 524     /**
 525      * Get a winsys buffer from a user pointer. The resulting buffer can't
 526      * be exported. Both pointer and size must be page aligned.
 527      *
 528      * \param ws        The winsys this function is called from.
 529      * \param pointer   User pointer to turn into a buffer object.
 530      * \param Size      Size in bytes for the new buffer.
 531      */
 532     struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
 533                                          void *pointer, unsigned size);
 534
 535     /**
 536      * Whether the buffer was created from a user pointer.
 537      *
 538      * \param buf       A winsys buffer object
 539      * \return          whether \p buf was created via buffer_from_ptr
 540      */
 541     bool (*buffer_is_user_ptr)(struct pb_buffer *buf);
 542
 543     /**
 544      * Get a winsys handle from a winsys buffer. The internal structure
 545      * of the handle is platform-specific and only a winsys should access it.
 546      *
 547      * \param buf       A winsys buffer object to get the handle from.
 548      * \param whandle   A winsys handle pointer.
 549      * \param stride    A stride of the buffer in bytes, for texturing.
 550      * \return          TRUE on success.
 551      */
 552     boolean (*buffer_get_handle)(struct pb_buffer *buf,
 553                                  unsigned stride,
 554                                  struct winsys_handle *whandle);
 555
 556     /**
 557      * Return the virtual address of a buffer.
 558      *
 559      * \param buf       A winsys buffer object
 560      * \return          virtual address
 561      */
 562     uint64_t (*buffer_get_virtual_address)(struct pb_buffer *buf);
 563
 564     /**
 565      * Query the initial placement of the buffer from the kernel driver.
 566      */
 567     enum radeon_bo_domain (*buffer_get_initial_domain)(struct pb_buffer *buf);
 568
 569     /**************************************************************************
 570      * Command submission.
 571      *
 572      * Each pipe context should create its own command stream and submit
 573      * commands independently of other contexts.
 574      *************************************************************************/
 575
 576     /**
 577      * Create a command submission context.
 578      * Various command streams can be submitted to the same context.
 579      */
 580     struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 581
 582     /**
 583      * Destroy a context.
 584      */
 585     void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 586
 587     /**
 588      * Query a GPU reset status.
 589      */
 590     enum pipe_reset_status (*ctx_query_reset_status)(struct radeon_winsys_ctx *ctx);
 591
 592     /**
 593      * Create a command stream.
 594      *
 595      * \param ctx       The submission context
 596      * \param ring_type The ring type (GFX, DMA, UVD)
 597      * \param flush     Flush callback function associated with the command stream.
 598      * \param user      User pointer that will be passed to the flush callback.
 599      * \param trace_buf Trace buffer when tracing is enabled
 600      */
 601     struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys_ctx *ctx,
 602                                           enum ring_type ring_type,
 603                                           void (*flush)(void *ctx, unsigned flags,
 604                                                         struct pipe_fence_handle **fence),
 605                                           void *flush_ctx,
 606                                           struct pb_buffer *trace_buf);
 607
 608     /**
 609      * Destroy a command stream.
 610      *
 611      * \param cs        A command stream to destroy.
 612      */
 613     void (*cs_destroy)(struct radeon_winsys_cs *cs);
 614
 615     /**
 616      * Add a buffer. Each buffer used by a CS must be added using this function.
 617      *
 618      * \param cs      Command stream
 619      * \param buf     Buffer
 620      * \param usage   Whether the buffer is used for read and/or write.
 621      * \param domain  Bitmask of the RADEON_DOMAIN_* flags.
 622      * \param priority  A higher number means a greater chance of being
 623      *                  placed in the requested domain. 15 is the maximum.
 624      * \return Buffer index.
 625      */
 626     unsigned (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 627                              struct pb_buffer *buf,
 628                              enum radeon_bo_usage usage,
 629                              enum radeon_bo_domain domain,
 630                              enum radeon_bo_priority priority);
 631
 632     /**
 633      * Return the index of an already-added buffer.
 634      *
 635      * \param cs        Command stream
 636      * \param buf       Buffer
 637      * \return          The buffer index, or -1 if the buffer has not been added.
 638      */
 639     int (*cs_lookup_buffer)(struct radeon_winsys_cs *cs,
 640                             struct pb_buffer *buf);
 641
 642     /**
 643      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 644      * added so far. If the validation fails, all buffers which have
 645      * been added since the last call of cs_validate will be removed and
 646      * the CS will be flushed (provided there are still any buffers).
 647      *
 648      * \param cs        A command stream to validate.
 649      */
 650     boolean (*cs_validate)(struct radeon_winsys_cs *cs);
 651
 652     /**
 653      * Return TRUE if there is enough memory in VRAM and GTT for the buffers
 654      * added so far.
 655      *
 656      * \param cs        A command stream to validate.
 657      * \param vram      VRAM memory size pending to be use
 658      * \param gtt       GTT memory size pending to be use
 659      */
 660     boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
 661
 662     /**
 663      * Return the buffer list.
 664      *
 665      * \param cs    Command stream
 666      * \param list  Returned buffer list. Set to NULL to query the count only.
 667      * \return      The buffer count.
 668      */
 669     unsigned (*cs_get_buffer_list)(struct radeon_winsys_cs *cs,
 670                                    struct radeon_bo_list_item *list);
 671
 672     /**
 673      * Flush a command stream.
 674      *
 675      * \param cs          A command stream to flush.
 676      * \param flags,      RADEON_FLUSH_ASYNC or 0.
 677      * \param fence       Pointer to a fence. If non-NULL, a fence is inserted
 678      *                    after the CS and is returned through this parameter.
 679      * \param cs_trace_id A unique identifier of the cs, used for tracing.
 680      */
 681     void (*cs_flush)(struct radeon_winsys_cs *cs,
 682                      unsigned flags,
 683                      struct pipe_fence_handle **fence,
 684                      uint32_t cs_trace_id);
 685
 686     /**
 687      * Return TRUE if a buffer is referenced by a command stream.
 688      *
 689      * \param cs        A command stream.
 690      * \param buf       A winsys buffer.
 691      */
 692     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
 693                                        struct pb_buffer *buf,
 694                                        enum radeon_bo_usage usage);
 695
 696     /**
 697      * Request access to a feature for a command stream.
 698      *
 699      * \param cs        A command stream.
 700      * \param fid       Feature ID, one of RADEON_FID_*
 701      * \param enable    Whether to enable or disable the feature.
 702      */
 703     boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
 704                                   enum radeon_feature_id fid,
 705                                   boolean enable);
 706      /**
 707       * Make sure all asynchronous flush of the cs have completed
 708       *
 709       * \param cs        A command stream.
 710       */
 711     void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
 712
 713     /**
 714      * Wait for the fence and return true if the fence has been signalled.
 715      * The timeout of 0 will only return the status.
 716      * The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
 717      * is signalled.
 718      */
 719     bool (*fence_wait)(struct radeon_winsys *ws,
 720                        struct pipe_fence_handle *fence,
 721                        uint64_t timeout);
 722
 723     /**
 724      * Reference counting for fences.
 725      */
 726     void (*fence_reference)(struct pipe_fence_handle **dst,
 727                             struct pipe_fence_handle *src);
 728
 729     /**
 730      * Initialize surface
 731      *
 732      * \param ws        The winsys this function is called from.
 733      * \param surf      Surface structure ptr
 734      */
 735     int (*surface_init)(struct radeon_winsys *ws,
 736                         struct radeon_surf *surf);
 737
 738     /**
 739      * Find best values for a surface
 740      *
 741      * \param ws        The winsys this function is called from.
 742      * \param surf      Surface structure ptr
 743      */
 744     int (*surface_best)(struct radeon_winsys *ws,
 745                         struct radeon_surf *surf);
 746
 747     uint64_t (*query_value)(struct radeon_winsys *ws,
 748                             enum radeon_value_id value);
 749
 750     bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 751                            unsigned num_registers, uint32_t *out);
 752 };
 753
 754
 755 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 756 {
 757     cs->buf[cs->cdw++] = value;
 758 }
 759
 760 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 761                                      const uint32_t *values, unsigned count)
 762 {
 763     memcpy(cs->buf+cs->cdw, values, count * 4);
 764     cs->cdw += count;
 765 }
 766
 767 #endif